From: Jagan Date: Mon, 28 May 2012 11:34:56 +0000 (+0530) Subject: Xilinx: ARM: Renamed XDF* to XZYNQ* X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=3550d0ad327f82165574a19ee5e54c9a68605347;p=thirdparty%2Fu-boot.git Xilinx: ARM: Renamed XDF* to XZYNQ* This patch is a part of cleanup activity. Signed-off-by: Jagan --- diff --git a/board/xilinx/zynq_common/xgmac.h b/board/xilinx/zynq_common/xgmac.h index ad05ada802c..58b225266cc 100644 --- a/board/xilinx/zynq_common/xgmac.h +++ b/board/xilinx/zynq_common/xgmac.h @@ -2,223 +2,245 @@ * Harvested from Cadence driver. */ -#ifndef __XDFETH_H__ -#define __XDFETH_H__ - -#define XDFETH_RX_BUF_SIZE 128 - -#define XDFETH_RBQ_LENGTH 128 -#define XDFETH_TBQ_LENGTH 128 - -#define XDFETH_MDIO_ENABLED (GEM_MDIO_EN) - -#define XDFETH_DEF_PCLK_DIV (MDC_DIV_32) - -#define XDFETH_DEF_AHB_WIDTH (AMBA_AHB_32) - -#define XDFETH_DEF_DUPLEX (GEM_FULL_DUPLEX) - -#define XDFETH_DEF_SPEED (SPEED_100M) - -#define XDFETH_DEF_LOOP (LB_NONE) - -#define XDFETH_READ_SNAP (1<<14) /* Read snapshot register */ -#define XDFETH_TAKE_SNAP (1<<13) /* Take a snapshot */ -#define XDFETH_TX_0Q_PAUSE (1<<12) /* Transmit zero quantum pause frame */ -#define XDFETH_TX_PAUSE (1<<11) /* Transmit pause frame */ -#define XDFETH_TX_HALT (1<<10) /* Halt transmission after curr frame */ -#define XDFETH_TX_START (1<<9) /* Start tx (tx_go) */ -#define XDFETH_STATS_WR_EN (1<<7) /* Enable writing to stat registers */ -#define XDFETH_STATS_INC (1<<6) /* Increment statistic registers */ -#define XDFETH_STATS_CLR (1<<5) /* Clear statistic registers */ -#define XDFETH_MDIO_EN (1<<4) /* Enable MDIO port */ -#define XDFETH_TX_EN (1<<3) /* Enable transmit circuits */ -#define XDFETH_RX_EN (1<<2) /* Enable receive circuits */ -#define XDFETH_LB_MAC (1<<1) /* Perform local loopback at MAC */ -#define XDFETH_LB_PHY (1<<0) /* Perform ext loopback through PHY */ - -#define XDFETH_RX_NO_PAUSE (1<<23) /* Do not copy pause frames to memory */ -#define XDFETH_AHB_WIDTH1 (1<<22) /* Bit 1 for defining AHB width */ -#define XDFETH_AHB_WIDTH0 (1<<21) /* Bit 0 for defining AHB width */ -#define XDFETH_MDC_DIV2 (1<<20) /* PCLK divisor for MDC, bit 2 */ -#define XDFETH_MDC_DIV1 (1<<19) /* PCLK divisor for MDC, bit 1 */ -#define XDFETH_MDC_DIV0 (1<<18) /* PCLK divisor for MDC, bit 0 */ -#define XDFETH_RX_NO_FCS (1<<17) /* Discard FCS from received frames. */ -#define XDFETH_RX_LEN_CHK (1<<16) /* Receive length check. */ -#define XDFETH_RX_OFFSET_BASE 14 /* Pos of LSB for rx buffer offsets. */ -#define XDFETH_RX_OFFSET1 (1<<(GEM_RX_OFFSET_BASE + 1)) /* RX offset bit 1 */ -#define XDFETH_RX_OFFSET0 (1<tbq_end) #define gem_get_tbq_current(mac) ((mac)->tbq_current) diff --git a/drivers/serial/serial_xpssuart.c b/drivers/serial/serial_xpssuart.c index dffae7d1486..7c30a472da6 100644 --- a/drivers/serial/serial_xpssuart.c +++ b/drivers/serial/serial_xpssuart.c @@ -28,11 +28,11 @@ void serial_setbrg(void) /* Find acceptable values for baud generation. */ for (bdiv = 4; bdiv < 255; bdiv++) { - bgen = XDFUART_MASTER / (baud * (bdiv + 1)); + bgen = XZYNQUART_MASTER / (baud * (bdiv + 1)); if (bgen < 2 || bgen > 65535) continue; - calc_baud = XDFUART_MASTER / (bgen * (bdiv + 1)); + calc_baud = XZYNQUART_MASTER / (bgen * (bdiv + 1)); /* Use first calculated baudrate with an acceptable * (<3%) error. @@ -62,10 +62,12 @@ int serial_init(void) /* Write a char to the Tx buffer */ void serial_putc(char c) { - while ((xdfuart_readl(SR) & XDFUART_SR_TXFULL) != 0); + while ((xdfuart_readl(SR) & XZYNQUART_SR_TXFULL) != 0) + ; if (c == '\n') { xdfuart_writel(FIFO,'\r'); - while ((xdfuart_readl(SR) & XDFUART_SR_TXFULL) != 0); + while ((xdfuart_readl(SR) & XZYNQUART_SR_TXFULL) != 0) + ; } xdfuart_writel(FIFO,c); } @@ -87,5 +89,5 @@ int serial_getc(void) /* Test character presence in Rx buffer */ int serial_tstc(void) { - return (xdfuart_readl(SR) & XDFUART_SR_RXEMPTY) == 0; + return (xdfuart_readl(SR) & XZYNQUART_SR_RXEMPTY) == 0; } diff --git a/drivers/serial/serial_xpssuart.h b/drivers/serial/serial_xpssuart.h index cd0295407d1..0c809c25bb1 100644 --- a/drivers/serial/serial_xpssuart.h +++ b/drivers/serial/serial_xpssuart.h @@ -4,78 +4,79 @@ * as of svn rev 1377. */ -#ifndef __XILINX_DF_UART_H__ -#define __XILINX_DF_UART_H__ +#ifndef __XILINX_ZYNQ_UART_H__ +#define __XILINX_ZYNQ_UART_H__ #include #if defined(CONFIG_UART0) # define UART_ID 0 # define UART_BASE XPSS_UART0_BASEADDR -# define XDFUART_MASTER XPAR_XUARTPSS_0_CLOCK_HZ +# define XZYNQUART_MASTER XPAR_XUARTPSS_0_CLOCK_HZ #elif defined(CONFIG_UART1) # define UART_ID 1 # define UART_BASE XPSS_UART1_BASEADDR -# define XDFUART_MASTER XPAR_XUARTPSS_1_CLOCK_HZ +# define XZYNQUART_MASTER XPAR_XUARTPSS_1_CLOCK_HZ #else # error "Need to configure a UART (0 or 1)" #endif /* UART register offsets */ -#define XDFUART_CR_OFFSET 0x00 /* Control Register [8:0] */ -#define XDFUART_MR_OFFSET 0x04 /* Mode Register [10:0] */ -#define XDFUART_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */ -#define XDFUART_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */ -#define XDFUART_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */ -#define XDFUART_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/ -#define XDFUART_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */ -#define XDFUART_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */ -#define XDFUART_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */ -#define XDFUART_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */ -#define XDFUART_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */ -#define XDFUART_SR_OFFSET 0x2C /* Channel Status [11:0] */ -#define XDFUART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */ -#define XDFUART_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */ -#define XDFUART_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */ +#define XZYNQUART_CR_OFFSET 0x00 /* Control Register [8:0] */ +#define XZYNQUART_MR_OFFSET 0x04 /* Mode Register [10:0] */ +#define XZYNQUART_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */ +#define XZYNQUART_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */ +#define XZYNQUART_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */ +#define XZYNQUART_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/ +#define XZYNQUART_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */ +#define XZYNQUART_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */ +#define XZYNQUART_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */ +#define XZYNQUART_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */ +#define XZYNQUART_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */ +#define XZYNQUART_SR_OFFSET 0x2C /* Channel Status [11:0] */ +#define XZYNQUART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */ +#define XZYNQUART_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */ +#define XZYNQUART_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */ /* Control register bits */ -#define XDFUART_CR_STOPBRK 0x00000100 /* Stop transmission of break */ -#define XDFUART_CR_STARTBRK 0x00000080 /* Set break */ -#define XDFUART_CR_TORST 0x00000040 /* RX timeout counter restart */ -#define XDFUART_CR_TX_DIS 0x00000020 /* TX disabled. */ -#define XDFUART_CR_TX_EN 0x00000010 /* TX enabled */ -#define XDFUART_CR_RX_DIS 0x00000008 /* RX disabled. */ -#define XDFUART_CR_RX_EN 0x00000004 /* RX enabled */ -#define XDFUART_CR_EN_DIS_MASK 0x0000003C /* Enable/disable Mask */ -#define XDFUART_CR_TXRST 0x00000002 /* TX logic reset */ -#define XDFUART_CR_RXRST 0x00000001 /* RX logic reset */ +#define XZYNQUART_CR_STOPBRK 0x00000100 /* Stop transmission of break */ +#define XZYNQUART_CR_STARTBRK 0x00000080 /* Set break */ +#define XZYNQUART_CR_TORST 0x00000040 /* RX timeout counter restart */ +#define XZYNQUART_CR_TX_DIS 0x00000020 /* TX disabled. */ +#define XZYNQUART_CR_TX_EN 0x00000010 /* TX enabled */ +#define XZYNQUART_CR_RX_DIS 0x00000008 /* RX disabled. */ +#define XZYNQUART_CR_RX_EN 0x00000004 /* RX enabled */ +#define XZYNQUART_CR_EN_DIS_MASK 0x0000003C /* Enable/disable Mask */ +#define XZYNQUART_CR_TXRST 0x00000002 /* TX logic reset */ +#define XZYNQUART_CR_RXRST 0x00000001 /* RX logic reset */ /* Mode register bits */ -#define XDFUART_MR_CCLK 0x00000400 /* Input clock selection */ -#define XDFUART_MR_CHMODE_R_LOOP 0x00000300 /* Remote loopback mode */ -#define XDFUART_MR_CHMODE_L_LOOP 0x00000200 /* Local loopback mode */ -#define XDFUART_MR_CHMODE_ECHO 0x00000100 /* Auto echo mode */ -#define XDFUART_MR_CHMODE_NORM 0x00000000 /* Normal mode */ -#define XDFUART_MR_CHMODE_SHIFT 8 /* Mode shift */ -#define XDFUART_MR_CHMODE_MASK 0x00000300 /* Mode mask */ -#define XDFUART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ -#define XDFUART_MR_STOPMODE_1_5_BIT 0x00000040 /* 1.5 stop bits */ -#define XDFUART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ -#define XDFUART_MR_STOPMODE_SHIFT 6 /* Stop bits setting shift */ -#define XDFUART_MR_STOPMODE_MASK 0x000000A0 /* Stop bits setting mask */ -#define XDFUART_MR_PARITY_NONE 0x00000020 /* No parity mode */ -#define XDFUART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ -#define XDFUART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ -#define XDFUART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ -#define XDFUART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ -#define XDFUART_MR_PARITY_SHIFT 3 /* Parity setting shift */ -#define XDFUART_MR_PARITY_MASK 0x00000038 /* Parity mask */ -#define XDFUART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ -#define XDFUART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ -#define XDFUART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ -#define XDFUART_MR_CHARLEN_SHIFT 1 /* data Length setting shift */ -#define XDFUART_MR_CHARLEN_MASK 0x00000006 /* Data length mask. */ -#define XDFUART_MR_CLKSEL 0x00000001 /* Input clock selection */ +#define XZYNQUART_MR_CCLK 0x00000400 /* Input clock selection */ +#define XZYNQUART_MR_CHMODE_R_LOOP 0x00000300 /* Remote loopback mode */ +#define XZYNQUART_MR_CHMODE_L_LOOP 0x00000200 /* Local loopback mode */ +#define XZYNQUART_MR_CHMODE_ECHO 0x00000100 /* Auto echo mode */ +#define XZYNQUART_MR_CHMODE_NORM 0x00000000 /* Normal mode */ +#define XZYNQUART_MR_CHMODE_SHIFT 8 /* Mode shift */ +#define XZYNQUART_MR_CHMODE_MASK 0x00000300 /* Mode mask */ +#define XZYNQUART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ +#define XZYNQUART_MR_STOPMODE_1_5_BIT 0x00000040 /* 1.5 stop bits */ +#define XZYNQUART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ +#define XZYNQUART_MR_STOPMODE_SHIFT 6 /* Stop bits setting shift */ +#define XZYNQUART_MR_STOPMODE_MASK 0x000000A0 /* Stop bits setting mask */ +#define XZYNQUART_MR_PARITY_NONE 0x00000020 /* No parity mode */ +#define XZYNQUART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ +#define XZYNQUART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ +#define XZYNQUART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ +#define XZYNQUART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ +#define XZYNQUART_MR_PARITY_SHIFT 3 /* Parity setting shift */ +#define XZYNQUART_MR_PARITY_MASK 0x00000038 /* Parity mask */ +#define XZYNQUART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ +#define XZYNQUART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ +#define XZYNQUART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ +/* data Length setting shift */ +#define XZYNQUART_MR_CHARLEN_SHIFT 1 +#define XZYNQUART_MR_CHARLEN_MASK 0x00000006 /* Data length mask. */ +#define XZYNQUART_MR_CLKSEL 0x00000001 /* Input clock selection */ /* @@ -91,17 +92,18 @@ * * All four registers have the same bit definitions. */ -#define XDFUART_IXR_DMS 0x00000200 /* Modem status change interrupt */ -#define XDFUART_IXR_TOUT 0x00000100 /* Timeout error interrupt */ -#define XDFUART_IXR_PARITY 0x00000080 /* Parity error interrupt */ -#define XDFUART_IXR_FRAMING 0x00000040 /* Framing error interrupt */ -#define XDFUART_IXR_OVER 0x00000020 /* Overrun error interrupt */ -#define XDFUART_IXR_TXFULL 0x00000010 /* TX FIFO full interrupt. */ -#define XDFUART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt. */ -#define XDFUART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ -#define XDFUART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ -#define XDFUART_IXR_RXOVR 0x00000001 /* RX FIFO trigger interrupt. */ -#define XDFUART_IXR_MASK 0x000003FF /* Valid bit mask */ +/* Modem status change interrupt */ +#define XZYNQUART_IXR_DMS 0x00000200 +#define XZYNQUART_IXR_TOUT 0x00000100 /* Timeout error interrupt */ +#define XZYNQUART_IXR_PARITY 0x00000080 /* Parity error interrupt */ +#define XZYNQUART_IXR_FRAMING 0x00000040 /* Framing error interrupt */ +#define XZYNQUART_IXR_OVER 0x00000020 /* Overrun error interrupt */ +#define XZYNQUART_IXR_TXFULL 0x00000010 /* TX FIFO full interrupt. */ +#define XZYNQUART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt. */ +#define XZYNQUART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ +#define XZYNQUART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ +#define XZYNQUART_IXR_RXOVR 0x00000001 /* RX FIFO trigger interrupt. */ +#define XZYNQUART_IXR_MASK 0x000003FF /* Valid bit mask */ /* Baud rate generator register @@ -113,8 +115,8 @@ * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit * in the MR register. */ -#define XDFUART_BAUDGEN_DISABLE 0x00000000 /* Disable clock */ -#define XDFUART_BAUDGEN_MASK 0x0000FFFF /* Valid bits mask */ +#define XZYNQUART_BAUDGEN_DISABLE 0x00000000 /* Disable clock */ +#define XZYNQUART_BAUDGEN_MASK 0x0000FFFF /* Valid bits mask */ /* Baud divisor rate register * @@ -125,7 +127,7 @@ * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by * the MR_CCLK bit in the MR register. */ -#define XDFUART_BAUDDIV_MASK 0x000000FF /* 8 bit baud divider mask */ +#define XZYNQUART_BAUDDIV_MASK 0x000000FF /* 8 bit baud divider mask */ /* Receiver timeout register @@ -134,16 +136,16 @@ * the receiver data line. * */ -#define XDFUART_RXTOUT_DISABLE 0x00000000 /* Disable time out */ -#define XDFUART_RXTOUT_MASK 0x000000FF /* Valid bits mask */ +#define XZYNQUART_RXTOUT_DISABLE 0x00000000 /* Disable time out */ +#define XZYNQUART_RXTOUT_MASK 0x000000FF /* Valid bits mask */ /* Receiver fifo trigger level register * * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at * which the RX FIFO triggers an interrupt event. */ -#define XDFUART_RXWM_DISABLE 0x00000000 /* Disable RX trigger interrupt */ -#define XDFUART_RXWM_MASK 0x0000001F /* Valid bits mask */ +#define XZYNQUART_RXWM_DISABLE 0x00000000 /* Disable RX trigger interrupt */ +#define XZYNQUART_RXWM_MASK 0x0000001F /* Valid bits mask */ /* Modem control register * @@ -151,9 +153,9 @@ * or a peripheral device emulating a modem. * */ -#define XDFUART_MODEMCR_FCM 0x00000010 /* Flow control mode */ -#define XDFUART_MODEMCR_RTS 0x00000002 /* Request to send */ -#define XDFUART_MODEMCR_DTR 0x00000001 /* Data terminal ready */ +#define XZYNQUART_MODEMCR_FCM 0x00000010 /* Flow control mode */ +#define XZYNQUART_MODEMCR_RTS 0x00000002 /* Request to send */ +#define XZYNQUART_MODEMCR_DTR 0x00000001 /* Data terminal ready */ /* Modem status register * @@ -167,15 +169,15 @@ * register. * */ -#define XDFUART_MODEMSR_FCMS 0x00000100 /* Flow control mode (FCMS) */ -#define XDFUART_MODEMSR_DCD 0x00000080 /* Complement of DCD input */ -#define XDFUART_MODEMSR_RI 0x00000040 /* Complement of RI input */ -#define XDFUART_MODEMSR_DSR 0x00000020 /* Complement of DSR input */ -#define XDFUART_MODEMSR_CTS 0x00000010 /* Complement of CTS input */ -#define XDFUART_MEDEMSR_DCDX 0x00000008 /* Delta DCD indicator */ -#define XDFUART_MEDEMSR_RIX 0x00000004 /* Change of RI */ -#define XDFUART_MEDEMSR_DSRX 0x00000002 /* Change of DSR */ -#define XDFUART_MEDEMSR_CTSX 0x00000001 /* Change of CTS */ +#define XZYNQUART_MODEMSR_FCMS 0x00000100 /* Flow control mode (FCMS) */ +#define XZYNQUART_MODEMSR_DCD 0x00000080 /* Complement of DCD input */ +#define XZYNQUART_MODEMSR_RI 0x00000040 /* Complement of RI input */ +#define XZYNQUART_MODEMSR_DSR 0x00000020 /* Complement of DSR input */ +#define XZYNQUART_MODEMSR_CTS 0x00000010 /* Complement of CTS input */ +#define XZYNQUART_MEDEMSR_DCDX 0x00000008 /* Delta DCD indicator */ +#define XZYNQUART_MEDEMSR_RIX 0x00000004 /* Change of RI */ +#define XZYNQUART_MEDEMSR_DSRX 0x00000002 /* Change of DSR */ +#define XZYNQUART_MEDEMSR_CTSX 0x00000001 /* Change of CTS */ /* Channel status register * @@ -184,19 +186,20 @@ * even if these are masked out by the interrupt mask register. * */ -#define XDFUART_SR_FLOWDEL 0x00001000 /* RX FIFO fill over flow delay */ -#define XDFUART_SR_TACTIVE 0x00000800 /* TX active */ -#define XDFUART_SR_RACTIVE 0x00000400 /* RX active */ -#define XDFUART_SR_DMS 0x00000200 /* Delta modem status change */ -#define XDFUART_SR_TOUT 0x00000100 /* RX timeout */ -#define XDFUART_SR_PARITY 0x00000080 /* RX parity error */ -#define XDFUART_SR_FRAME 0x00000040 /* RX frame error */ -#define XDFUART_SR_OVER 0x00000020 /* RX overflow error */ -#define XDFUART_SR_TXFULL 0x00000010 /* TX FIFO full */ -#define XDFUART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ -#define XDFUART_SR_RXFULL 0x00000004 /* RX FIFO full */ -#define XDFUART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ -#define XDFUART_SR_RXOVR 0x00000001 /* RX FIFO fill over trigger */ +/* RX FIFO fill over flow delay */ +#define XZYNQUART_SR_FLOWDEL 0x00001000 +#define XZYNQUART_SR_TACTIVE 0x00000800 /* TX active */ +#define XZYNQUART_SR_RACTIVE 0x00000400 /* RX active */ +#define XZYNQUART_SR_DMS 0x00000200 /* Delta modem status change */ +#define XZYNQUART_SR_TOUT 0x00000100 /* RX timeout */ +#define XZYNQUART_SR_PARITY 0x00000080 /* RX parity error */ +#define XZYNQUART_SR_FRAME 0x00000040 /* RX frame error */ +#define XZYNQUART_SR_OVER 0x00000020 /* RX overflow error */ +#define XZYNQUART_SR_TXFULL 0x00000010 /* TX FIFO full */ +#define XZYNQUART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ +#define XZYNQUART_SR_RXFULL 0x00000004 /* RX FIFO full */ +#define XZYNQUART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ +#define XZYNQUART_SR_RXOVR 0x00000001 /* RX FIFO fill over trigger */ /* Flow delay register * @@ -209,12 +212,12 @@ * level of the flow delay trigger and the flow delay trigger is not activated. * A value less than 4 disables the flow delay. */ -#define XDFUART_FLOWDEL_MASK XDFUART_RXWM_MASK /* Valid bit mask */ +#define XZYNQUART_FLOWDEL_MASK XZYNQUART_RXWM_MASK /* Valid bit mask */ /* Some access macros */ #define xdfuart_readl(reg) \ - readl((void*)UART_BASE + XDFUART_##reg##_OFFSET) + readl((void *)UART_BASE + XZYNQUART_##reg##_OFFSET) #define xdfuart_writel(reg,value) \ - writel((value),(void*)UART_BASE + XDFUART_##reg##_OFFSET) + writel((value), (void *)UART_BASE + XZYNQUART_##reg##_OFFSET) -#endif /* __XILINX_DF_UART_H__ */ +#endif /* __XILINX_ZYNQ_UART_H__ */