From: Sasha Levin Date: Sat, 14 Jan 2023 14:23:23 +0000 (-0500) Subject: Fixes for 6.1 X-Git-Tag: v4.14.303~63^2~5 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=35b2cbddaabbe34094ab0acce90183b75e798b2e;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 6.1 Signed-off-by: Sasha Levin --- diff --git a/queue-6.1/drm-amd-pm-enable-bad-memory-page-channel-recording-.patch b/queue-6.1/drm-amd-pm-enable-bad-memory-page-channel-recording-.patch new file mode 100644 index 00000000000..857489131bc --- /dev/null +++ b/queue-6.1/drm-amd-pm-enable-bad-memory-page-channel-recording-.patch @@ -0,0 +1,124 @@ +From 436d13fbe94c2da4d9cb4d85528258df5de4fa9a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 17 Nov 2022 20:34:15 +0800 +Subject: drm/amd/pm: Enable bad memory page/channel recording support for smu + v13_0_0 + +From: Candice Li + +[ Upstream commit 48aa62f07467c8fcd4b4ec7851e13c83e89a1558 ] + +Send message to SMU to update bad memory page and bad channel info. + +Signed-off-by: Candice Li +Reviewed-by: Evan Quan +Signed-off-by: Alex Deucher +Stable-dep-of: 1794f6a9535b ("drm/amd/pm: enable GPO dynamic control support for SMU13.0.0") +Signed-off-by: Sasha Levin +--- + .../pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h | 8 +++- + drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 4 +- + .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 39 +++++++++++++++++++ + 3 files changed, 49 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h +index 9ebb8f39732a..8b8266890a10 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h ++++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h +@@ -131,7 +131,13 @@ + #define PPSMC_MSG_EnableAudioStutterWA 0x44 + #define PPSMC_MSG_PowerUpUmsch 0x45 + #define PPSMC_MSG_PowerDownUmsch 0x46 +-#define PPSMC_Message_Count 0x47 ++#define PPSMC_MSG_SetDcsArch 0x47 ++#define PPSMC_MSG_TriggerVFFLR 0x48 ++#define PPSMC_MSG_SetNumBadMemoryPagesRetired 0x49 ++#define PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel 0x4A ++#define PPSMC_MSG_SetPriorityDeltaGain 0x4B ++#define PPSMC_MSG_AllowIHHostInterrupt 0x4C ++#define PPSMC_Message_Count 0x4D + + //Debug Dump Message + #define DEBUGSMC_MSG_TestMessage 0x1 +diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +index 58098b82df66..a4e3425b1027 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h ++++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +@@ -239,7 +239,9 @@ + __SMU_DUMMY_MAP(DriverMode2Reset), \ + __SMU_DUMMY_MAP(GetGfxOffStatus), \ + __SMU_DUMMY_MAP(GetGfxOffEntryCount), \ +- __SMU_DUMMY_MAP(LogGfxOffResidency), ++ __SMU_DUMMY_MAP(LogGfxOffResidency), \ ++ __SMU_DUMMY_MAP(SetNumBadMemoryPagesRetired), \ ++ __SMU_DUMMY_MAP(SetBadMemoryPagesRetiredFlagsPerChannel), + + #undef __SMU_DUMMY_MAP + #define __SMU_DUMMY_MAP(type) SMU_MSG_##type +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +index 73bae7eaefa2..884d4176b412 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +@@ -141,6 +141,9 @@ static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = + MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), + MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0), + MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), ++ MSG_MAP(SetNumBadMemoryPagesRetired, PPSMC_MSG_SetNumBadMemoryPagesRetired, 0), ++ MSG_MAP(SetBadMemoryPagesRetiredFlagsPerChannel, ++ PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel, 0), + }; + + static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = { +@@ -1928,6 +1931,40 @@ static void smu_v13_0_0_set_smu_mailbox_registers(struct smu_context *smu) + smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54); + } + ++static int smu_v13_0_0_smu_send_bad_mem_page_num(struct smu_context *smu, ++ uint32_t size) ++{ ++ int ret = 0; ++ ++ /* message SMU to update the bad page number on SMUBUS */ ++ ret = smu_cmn_send_smc_msg_with_param(smu, ++ SMU_MSG_SetNumBadMemoryPagesRetired, ++ size, NULL); ++ if (ret) ++ dev_err(smu->adev->dev, ++ "[%s] failed to message SMU to update bad memory pages number\n", ++ __func__); ++ ++ return ret; ++} ++ ++static int smu_v13_0_0_send_bad_mem_channel_flag(struct smu_context *smu, ++ uint32_t size) ++{ ++ int ret = 0; ++ ++ /* message SMU to update the bad channel info on SMUBUS */ ++ ret = smu_cmn_send_smc_msg_with_param(smu, ++ SMU_MSG_SetBadMemoryPagesRetiredFlagsPerChannel, ++ size, NULL); ++ if (ret) ++ dev_err(smu->adev->dev, ++ "[%s] failed to message SMU to update bad memory pages channel info\n", ++ __func__); ++ ++ return ret; ++} ++ + static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { + .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask, + .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table, +@@ -1998,6 +2035,8 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { + .mode1_reset = smu_v13_0_0_mode1_reset, + .set_mp1_state = smu_v13_0_0_set_mp1_state, + .set_df_cstate = smu_v13_0_0_set_df_cstate, ++ .send_hbm_bad_pages_num = smu_v13_0_0_smu_send_bad_mem_page_num, ++ .send_hbm_bad_channel_flag = smu_v13_0_0_send_bad_mem_channel_flag, + }; + + void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu) +-- +2.35.1 + diff --git a/queue-6.1/drm-amd-pm-enable-gpo-dynamic-control-support-for-sm.patch b/queue-6.1/drm-amd-pm-enable-gpo-dynamic-control-support-for-sm.patch new file mode 100644 index 00000000000..7e84078439e --- /dev/null +++ b/queue-6.1/drm-amd-pm-enable-gpo-dynamic-control-support-for-sm.patch @@ -0,0 +1,101 @@ +From 76577e866a8ed6b0931419d424842aeeaad37337 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 2 Dec 2022 13:56:35 +0800 +Subject: drm/amd/pm: enable GPO dynamic control support for SMU13.0.0 + +From: Evan Quan + +[ Upstream commit 1794f6a9535bb5234c2b747d1bc6dad03249245a ] + +To better support UMD pstate profilings, the GPO feature needs +to be switched on/off accordingly. + +Signed-off-by: Evan Quan +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.0.x +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 ++- + drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 3 +++ + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 15 +++++++++++++++ + .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++ + 4 files changed, 22 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +index a4e3425b1027..4180c71d930f 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h ++++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +@@ -241,7 +241,8 @@ + __SMU_DUMMY_MAP(GetGfxOffEntryCount), \ + __SMU_DUMMY_MAP(LogGfxOffResidency), \ + __SMU_DUMMY_MAP(SetNumBadMemoryPagesRetired), \ +- __SMU_DUMMY_MAP(SetBadMemoryPagesRetiredFlagsPerChannel), ++ __SMU_DUMMY_MAP(SetBadMemoryPagesRetiredFlagsPerChannel), \ ++ __SMU_DUMMY_MAP(AllowGpo), + + #undef __SMU_DUMMY_MAP + #define __SMU_DUMMY_MAP(type) SMU_MSG_##type +diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h +index a9122b3b1532..e8c6febb8b64 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h ++++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h +@@ -273,6 +273,9 @@ int smu_v13_0_init_pptable_microcode(struct smu_context *smu); + + int smu_v13_0_run_btc(struct smu_context *smu); + ++int smu_v13_0_gpo_control(struct smu_context *smu, ++ bool enablement); ++ + int smu_v13_0_deep_sleep_control(struct smu_context *smu, + bool enablement); + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +index cfb7f4475c82..9f9f64c5cdd8 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +@@ -2148,6 +2148,21 @@ int smu_v13_0_run_btc(struct smu_context *smu) + return res; + } + ++int smu_v13_0_gpo_control(struct smu_context *smu, ++ bool enablement) ++{ ++ int res; ++ ++ res = smu_cmn_send_smc_msg_with_param(smu, ++ SMU_MSG_AllowGpo, ++ enablement ? 1 : 0, ++ NULL); ++ if (res) ++ dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement); ++ ++ return res; ++} ++ + int smu_v13_0_deep_sleep_control(struct smu_context *smu, + bool enablement) + { +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +index 884d4176b412..4c20d17e7416 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +@@ -144,6 +144,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = + MSG_MAP(SetNumBadMemoryPagesRetired, PPSMC_MSG_SetNumBadMemoryPagesRetired, 0), + MSG_MAP(SetBadMemoryPagesRetiredFlagsPerChannel, + PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel, 0), ++ MSG_MAP(AllowGpo, PPSMC_MSG_SetGpoAllow, 0), + }; + + static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = { +@@ -2037,6 +2038,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { + .set_df_cstate = smu_v13_0_0_set_df_cstate, + .send_hbm_bad_pages_num = smu_v13_0_0_smu_send_bad_mem_page_num, + .send_hbm_bad_channel_flag = smu_v13_0_0_send_bad_mem_channel_flag, ++ .gpo_control = smu_v13_0_gpo_control, + }; + + void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu) +-- +2.35.1 + diff --git a/queue-6.1/drm-amd-pm-enable-gpo-dynamic-control-support-for-sm.patch-18688 b/queue-6.1/drm-amd-pm-enable-gpo-dynamic-control-support-for-sm.patch-18688 new file mode 100644 index 00000000000..81e66ea2339 --- /dev/null +++ b/queue-6.1/drm-amd-pm-enable-gpo-dynamic-control-support-for-sm.patch-18688 @@ -0,0 +1,44 @@ +From f1d223787a8e124a35263e0e6a6cc4c7402327b7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 2 Dec 2022 14:03:45 +0800 +Subject: drm/amd/pm: enable GPO dynamic control support for SMU13.0.7 + +From: Evan Quan + +[ Upstream commit 62b9f835a6c60171845642afec4ce4b44865f10f ] + +To better support UMD pstate profilings, the GPO feature needs +to be switched on/off accordingly. + +Signed-off-by: Evan Quan +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.0.x +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +index 31deec2ce4b3..eea06939e7da 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +@@ -123,6 +123,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] = + MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), + MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0), + MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), ++ MSG_MAP(AllowGpo, PPSMC_MSG_SetGpoAllow, 0), + }; + + static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = { +@@ -1712,6 +1713,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { + .mode1_reset = smu_v13_0_mode1_reset, + .set_mp1_state = smu_v13_0_7_set_mp1_state, + .set_df_cstate = smu_v13_0_7_set_df_cstate, ++ .gpo_control = smu_v13_0_gpo_control, + }; + + void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu) +-- +2.35.1 + diff --git a/queue-6.1/drm-amd-pm-enable-mode1-reset-on-smu_v13_0_10.patch b/queue-6.1/drm-amd-pm-enable-mode1-reset-on-smu_v13_0_10.patch new file mode 100644 index 00000000000..6b2465fb01a --- /dev/null +++ b/queue-6.1/drm-amd-pm-enable-mode1-reset-on-smu_v13_0_10.patch @@ -0,0 +1,190 @@ +From e6f3d2c3e4a37978027c5d5d04d677a3228f02fb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 8 Nov 2022 08:30:36 +0800 +Subject: drm/amd/pm: enable mode1 reset on smu_v13_0_10 + +From: Kenneth Feng + +[ Upstream commit 60cfad329ab877cb62975ea78ed442c2496990ba ] + +enable mode1 reset and prioritize debug port on smu_v13_0_10 +as a more reliable message processing + +v2 - move mode1 reset callback to smu_v13_0_0_ppt.c + +Signed-off-by: Kenneth Feng +Reviewed-by: Yang Wang +Signed-off-by: Alex Deucher +Stable-dep-of: 1794f6a9535b ("drm/amd/pm: enable GPO dynamic control support for SMU13.0.0") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/soc21.c | 1 + + drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 4 ++ + .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 53 ++++++++++++++++++- + drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 18 +++++++ + drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 3 ++ + 5 files changed, 77 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c +index 8b297ade69a2..f1913d879811 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc21.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc21.c +@@ -322,6 +322,7 @@ soc21_asic_reset_method(struct amdgpu_device *adev) + switch (adev->ip_versions[MP1_HWIP][0]) { + case IP_VERSION(13, 0, 0): + case IP_VERSION(13, 0, 7): ++ case IP_VERSION(13, 0, 10): + return AMD_RESET_METHOD_MODE1; + case IP_VERSION(13, 0, 4): + return AMD_RESET_METHOD_MODE2; +diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +index f816b1dd110e..44bbf17e4bef 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h ++++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +@@ -568,6 +568,10 @@ struct smu_context + u32 param_reg; + u32 msg_reg; + u32 resp_reg; ++ ++ u32 debug_param_reg; ++ u32 debug_msg_reg; ++ u32 debug_resp_reg; + }; + + struct i2c_adapter; +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +index be43de9dd496..73bae7eaefa2 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +@@ -70,6 +70,26 @@ + + #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000 + ++#define mmMP1_SMN_C2PMSG_66 0x0282 ++#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 ++ ++#define mmMP1_SMN_C2PMSG_82 0x0292 ++#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 ++ ++#define mmMP1_SMN_C2PMSG_90 0x029a ++#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 ++ ++#define mmMP1_SMN_C2PMSG_75 0x028b ++#define mmMP1_SMN_C2PMSG_75_BASE_IDX 0 ++ ++#define mmMP1_SMN_C2PMSG_53 0x0275 ++#define mmMP1_SMN_C2PMSG_53_BASE_IDX 0 ++ ++#define mmMP1_SMN_C2PMSG_54 0x0276 ++#define mmMP1_SMN_C2PMSG_54_BASE_IDX 0 ++ ++#define DEBUGSMC_MSG_Mode1Reset 2 ++ + static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = { + MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), + MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), +@@ -1879,6 +1899,35 @@ static int smu_v13_0_0_set_df_cstate(struct smu_context *smu, + NULL); + } + ++static int smu_v13_0_0_mode1_reset(struct smu_context *smu) ++{ ++ int ret; ++ struct amdgpu_device *adev = smu->adev; ++ ++ if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10)) ++ ret = smu_cmn_send_debug_smc_msg(smu, DEBUGSMC_MSG_Mode1Reset); ++ else ++ ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); ++ ++ if (!ret) ++ msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); ++ ++ return ret; ++} ++ ++static void smu_v13_0_0_set_smu_mailbox_registers(struct smu_context *smu) ++{ ++ struct amdgpu_device *adev = smu->adev; ++ ++ smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); ++ smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); ++ smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); ++ ++ smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53); ++ smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75); ++ smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54); ++} ++ + static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { + .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask, + .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table, +@@ -1946,7 +1995,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { + .baco_enter = smu_v13_0_0_baco_enter, + .baco_exit = smu_v13_0_0_baco_exit, + .mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported, +- .mode1_reset = smu_v13_0_mode1_reset, ++ .mode1_reset = smu_v13_0_0_mode1_reset, + .set_mp1_state = smu_v13_0_0_set_mp1_state, + .set_df_cstate = smu_v13_0_0_set_df_cstate, + }; +@@ -1960,5 +2009,5 @@ void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu) + smu->table_map = smu_v13_0_0_table_map; + smu->pwr_src_map = smu_v13_0_0_pwr_src_map; + smu->workload_map = smu_v13_0_0_workload_map; +- smu_v13_0_set_smu_mailbox_registers(smu); ++ smu_v13_0_0_set_smu_mailbox_registers(smu); + } +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +index e4f8f90ac5aa..768b6e7dbd77 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +@@ -233,6 +233,18 @@ static void __smu_cmn_send_msg(struct smu_context *smu, + WREG32(smu->msg_reg, msg); + } + ++static int __smu_cmn_send_debug_msg(struct smu_context *smu, ++ u32 msg, ++ u32 param) ++{ ++ struct amdgpu_device *adev = smu->adev; ++ ++ WREG32(smu->debug_param_reg, param); ++ WREG32(smu->debug_msg_reg, msg); ++ WREG32(smu->debug_resp_reg, 0); ++ ++ return 0; ++} + /** + * smu_cmn_send_msg_without_waiting -- send the message; don't wait for status + * @smu: pointer to an SMU context +@@ -386,6 +398,12 @@ int smu_cmn_send_smc_msg(struct smu_context *smu, + read_arg); + } + ++int smu_cmn_send_debug_smc_msg(struct smu_context *smu, ++ uint32_t msg) ++{ ++ return __smu_cmn_send_debug_msg(smu, msg, 0); ++} ++ + int smu_cmn_to_asic_specific_index(struct smu_context *smu, + enum smu_cmn2asic_mapping_type type, + uint32_t index) +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h +index 1526ce09c399..f82cf76dd3a4 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h +@@ -42,6 +42,9 @@ int smu_cmn_send_smc_msg(struct smu_context *smu, + enum smu_message_type msg, + uint32_t *read_arg); + ++int smu_cmn_send_debug_smc_msg(struct smu_context *smu, ++ uint32_t msg); ++ + int smu_cmn_wait_for_response(struct smu_context *smu); + + int smu_cmn_to_asic_specific_index(struct smu_context *smu, +-- +2.35.1 + diff --git a/queue-6.1/drm-amdgpu-add-soc21-common-ip-block-support-for-gc-.patch b/queue-6.1/drm-amdgpu-add-soc21-common-ip-block-support-for-gc-.patch new file mode 100644 index 00000000000..03401a7134a --- /dev/null +++ b/queue-6.1/drm-amdgpu-add-soc21-common-ip-block-support-for-gc-.patch @@ -0,0 +1,40 @@ +From 42f150dd9c219a6fbeaeb284d6931a301a4f6eec Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 12 Oct 2022 12:54:52 +0800 +Subject: drm/amdgpu: add soc21 common ip block support for GC 11.0.4 + +From: Yifan Zhang + +[ Upstream commit 311d52367d0a7985ee1132662bad46f09169eed2 ] + +Add common soc21 ip block support for GC 11.0.4. + +Signed-off-by: Yifan Zhang +Reviewed-by: Aaron Liu +Signed-off-by: Alex Deucher +Stable-dep-of: e1d900df63ad ("drm/amdgpu: enable VCN DPG for GC IP v11.0.4") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/soc21.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c +index f1913d879811..26f1e4edb4d5 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc21.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc21.c +@@ -653,6 +653,12 @@ static int soc21_common_early_init(void *handle) + } + adev->external_rev_id = adev->rev_id + 0x20; + break; ++ case IP_VERSION(11, 0, 4): ++ adev->cg_flags = 0; ++ adev->pg_flags = 0; ++ adev->external_rev_id = adev->rev_id + 0x1; ++ break; ++ + default: + /* FIXME: not supported yet */ + return -EINVAL; +-- +2.35.1 + diff --git a/queue-6.1/drm-amdgpu-enable-pg-cg-flags-on-gc11_0_4-for-vcn.patch b/queue-6.1/drm-amdgpu-enable-pg-cg-flags-on-gc11_0_4-for-vcn.patch new file mode 100644 index 00000000000..9a3228b7f19 --- /dev/null +++ b/queue-6.1/drm-amdgpu-enable-pg-cg-flags-on-gc11_0_4-for-vcn.patch @@ -0,0 +1,43 @@ +From 5c13066e1bbd6bdae933def4742f593817196eb9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 8 Nov 2022 11:24:48 +0530 +Subject: drm/amdgpu: Enable pg/cg flags on GC11_0_4 for VCN + +From: Saleemkhan Jamadar + +[ Upstream commit 2a0fe2ca6e9c9bf9c47a9f9f0d67c13281a13f8c ] + +This enable VCN PG, CG and JPEG PG, CG + +Signed-off-by: Saleemkhan Jamadar +Reviewed-by: Leo Liu +Signed-off-by: Yifan Zhang +Reviewed-by: Aaron Liu +Signed-off-by: Alex Deucher +Stable-dep-of: e1d900df63ad ("drm/amdgpu: enable VCN DPG for GC IP v11.0.4") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/soc21.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c +index 26f1e4edb4d5..599ddc28d8e1 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc21.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc21.c +@@ -654,8 +654,11 @@ static int soc21_common_early_init(void *handle) + adev->external_rev_id = adev->rev_id + 0x20; + break; + case IP_VERSION(11, 0, 4): +- adev->cg_flags = 0; +- adev->pg_flags = 0; ++ adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | ++ AMD_CG_SUPPORT_JPEG_MGCG; ++ adev->pg_flags = AMD_PG_SUPPORT_VCN | ++ AMD_PG_SUPPORT_GFX_PG | ++ AMD_PG_SUPPORT_JPEG; + adev->external_rev_id = adev->rev_id + 0x1; + break; + +-- +2.35.1 + diff --git a/queue-6.1/drm-amdgpu-enable-vcn-dpg-for-gc-ip-v11.0.4.patch b/queue-6.1/drm-amdgpu-enable-vcn-dpg-for-gc-ip-v11.0.4.patch new file mode 100644 index 00000000000..ae92498ac73 --- /dev/null +++ b/queue-6.1/drm-amdgpu-enable-vcn-dpg-for-gc-ip-v11.0.4.patch @@ -0,0 +1,35 @@ +From 7224116d448a0397838a0279e6399d1cb016aa7b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 20 Dec 2022 13:21:44 +0530 +Subject: drm/amdgpu: enable VCN DPG for GC IP v11.0.4 + +From: Saleemkhan Jamadar + +[ Upstream commit e1d900df63adcb748905131dd6258e570e11aed1 ] + +Enable VCN Dynamic Power Gating control for GC IP v11.0.4. + +Signed-off-by: Saleemkhan Jamadar +Reviewed-by: Veerabadhran Gopalakrishnan +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.0, 6.1 +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/soc21.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c +index 599ddc28d8e1..909cf9f220c1 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc21.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc21.c +@@ -657,6 +657,7 @@ static int soc21_common_early_init(void *handle) + adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | + AMD_CG_SUPPORT_JPEG_MGCG; + adev->pg_flags = AMD_PG_SUPPORT_VCN | ++ AMD_PG_SUPPORT_VCN_DPG | + AMD_PG_SUPPORT_GFX_PG | + AMD_PG_SUPPORT_JPEG; + adev->external_rev_id = adev->rev_id + 0x1; +-- +2.35.1 + diff --git a/queue-6.1/drm-i915-gt-cleanup-partial-engine-discovery-failure.patch b/queue-6.1/drm-i915-gt-cleanup-partial-engine-discovery-failure.patch new file mode 100644 index 00000000000..bb854788ade --- /dev/null +++ b/queue-6.1/drm-i915-gt-cleanup-partial-engine-discovery-failure.patch @@ -0,0 +1,50 @@ +From 75d54bd2ce66ac81d037caa35953cd7e4cb6c759 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 15 Sep 2022 16:26:51 -0700 +Subject: drm/i915/gt: Cleanup partial engine discovery failures + +From: Chris Wilson + +[ Upstream commit 78a033433a5ae4fee85511ee075bc9a48312c79e ] + +If we abort driver initialisation in the middle of gt/engine discovery, +some engines will be fully setup and some not. Those incompletely setup +engines only have 'engine->release == NULL' and so will leak any of the +common objects allocated. + +v2: + - Drop the destroy_pinned_context() helper for now. It's not really + worth it with just a single callsite at the moment. (Janusz) + +Signed-off-by: Chris Wilson +Cc: Janusz Krzysztofik +Signed-off-by: Matt Roper +Reviewed-by: Janusz Krzysztofik +Link: https://patchwork.freedesktop.org/patch/msgid/20220915232654.3283095-2-matthew.d.roper@intel.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c +index 83bfeb872bda..fcbccd8d244e 100644 +--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c ++++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c +@@ -1343,8 +1343,13 @@ int intel_engines_init(struct intel_gt *gt) + return err; + + err = setup(engine); +- if (err) ++ if (err) { ++ intel_engine_cleanup_common(engine); + return err; ++ } ++ ++ /* The backend should now be responsible for cleanup */ ++ GEM_BUG_ON(engine->release == NULL); + + err = engine_init_common(engine); + if (err) +-- +2.35.1 + diff --git a/queue-6.1/series b/queue-6.1/series index 560118415cf..710c7e46fcc 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -35,3 +35,12 @@ drm-amd-pm-correct-the-reference-clock-for-fan-speed-rpm-calculation.patch drm-amd-pm-add-the-missing-mapping-for-ppt-feature-on-smu13.0.0-and-13.0.7.patch drm-amd-display-move-remaining-fpu-code-to-dml-folder.patch revert-drm-amdgpu-revert-drm-amdgpu-getting-fan-speed-pwm-for-vega10-properly.patch +drm-i915-gt-cleanup-partial-engine-discovery-failure.patch +usb-ulpi-defer-ulpi_register-on-ulpi_read_id-timeout.patch +drm-amd-pm-enable-mode1-reset-on-smu_v13_0_10.patch +drm-amd-pm-enable-bad-memory-page-channel-recording-.patch +drm-amd-pm-enable-gpo-dynamic-control-support-for-sm.patch +drm-amd-pm-enable-gpo-dynamic-control-support-for-sm.patch-18688 +drm-amdgpu-add-soc21-common-ip-block-support-for-gc-.patch +drm-amdgpu-enable-pg-cg-flags-on-gc11_0_4-for-vcn.patch +drm-amdgpu-enable-vcn-dpg-for-gc-ip-v11.0.4.patch diff --git a/queue-6.1/usb-ulpi-defer-ulpi_register-on-ulpi_read_id-timeout.patch b/queue-6.1/usb-ulpi-defer-ulpi_register-on-ulpi_read_id-timeout.patch new file mode 100644 index 00000000000..4a5605672df --- /dev/null +++ b/queue-6.1/usb-ulpi-defer-ulpi_register-on-ulpi_read_id-timeout.patch @@ -0,0 +1,49 @@ +From 4e33eed8a2052a6ea00c2f47c990e6e2e47b0e0a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 5 Dec 2022 21:15:26 +0100 +Subject: usb: ulpi: defer ulpi_register on ulpi_read_id timeout + +From: Ferry Toth + +[ Upstream commit 8a7b31d545d3a15f0e6f5984ae16f0ca4fd76aac ] + +Since commit 0f0101719138 ("usb: dwc3: Don't switch OTG -> peripheral +if extcon is present") Dual Role support on Intel Merrifield platform +broke due to rearranging the call to dwc3_get_extcon(). + +It appears to be caused by ulpi_read_id() on the first test write failing +with -ETIMEDOUT. Currently ulpi_read_id() expects to discover the phy via +DT when the test write fails and returns 0 in that case, even if DT does not +provide the phy. As a result usb probe completes without phy. + +Make ulpi_read_id() return -ETIMEDOUT to its user if the first test write +fails. The user should then handle it appropriately. A follow up patch +will make dwc3_core_init() set -EPROBE_DEFER in this case and bail out. + +Fixes: ef6a7bcfb01c ("usb: ulpi: Support device discovery via DT") +Cc: stable@vger.kernel.org +Acked-by: Heikki Krogerus +Signed-off-by: Ferry Toth +Link: https://lore.kernel.org/r/20221205201527.13525-2-ftoth@exalondelft.nl +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/usb/common/ulpi.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/usb/common/ulpi.c b/drivers/usb/common/ulpi.c +index d7c8461976ce..60e8174686a1 100644 +--- a/drivers/usb/common/ulpi.c ++++ b/drivers/usb/common/ulpi.c +@@ -207,7 +207,7 @@ static int ulpi_read_id(struct ulpi *ulpi) + /* Test the interface */ + ret = ulpi_write(ulpi, ULPI_SCRATCH, 0xaa); + if (ret < 0) +- goto err; ++ return ret; + + ret = ulpi_read(ulpi, ULPI_SCRATCH); + if (ret < 0) +-- +2.35.1 +