From: Siva Durga Prasad Paladugu Date: Wed, 26 Mar 2014 13:25:36 +0000 (+0530) Subject: fpga: Add support to load partial and compressed bitstreams X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=369ea213f18a103c3665933a44070dc304c39383;p=thirdparty%2Fu-boot.git fpga: Add support to load partial and compressed bitstreams Added support to load partial and compressed bitstreams. The partial bitstreams can be loaded using the below commands Commands: fpga loadp fpga loadbp The compressed and full bit streams can be loaded using the old commands(fpga load and fpga loadb). Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- diff --git a/board/matrix_vision/common/mv_common.c b/board/matrix_vision/common/mv_common.c index 70133b5118b..1be5aba2e94 100644 --- a/board/matrix_vision/common/mv_common.c +++ b/board/matrix_vision/common/mv_common.c @@ -77,7 +77,7 @@ int mv_load_fpga(void) return -1; } - result = fpga_load(0, fpga_data, data_size); + result = fpga_load(0, fpga_data, data_size, BIT_FULL); if (!result) bootstage_mark(BOOTSTAGE_ID_START); diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index d8d2401299c..9c39b2ce817 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -27,6 +27,8 @@ static int fpga_get_op(char *opstr); #define FPGA_DUMP 3 #define FPGA_LOADMK 4 #define FPGA_LOADFS 5 +#define FPGA_LOADP 6 +#define FPGA_LOADBP 7 /* ------------------------------------------------------------------------- */ /* command form: @@ -148,7 +150,9 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) wrong_parms = 1; #endif case FPGA_LOAD: + case FPGA_LOADP: case FPGA_LOADB: + case FPGA_LOADBP: case FPGA_DUMP: if (!fpga_data || !data_size) wrong_parms = 1; @@ -173,12 +177,21 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) break; case FPGA_LOAD: - rc = fpga_load(dev, fpga_data, data_size); + rc = fpga_load(dev, fpga_data, data_size, BIT_FULL); + break; + + case FPGA_LOADP: + rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL); break; case FPGA_LOADB: - rc = fpga_loadbitstream(dev, fpga_data, data_size); + rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL); break; + + case FPGA_LOADBP: + rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL); + break; + #ifdef CONFIG_FPGA_LOADFS case FPGA_LOADFS: rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo); @@ -289,6 +302,10 @@ static int fpga_get_op(char *opstr) op = FPGA_LOADB; else if (!strcmp("load", opstr)) op = FPGA_LOAD; + else if (!strcmp("loadp", opstr)) + op = FPGA_LOADP; + else if (!strcmp("loadbp", opstr)) + op = FPGA_LOADBP; #ifdef CONFIG_FPGA_LOADFS else if (!strcmp("loadfs", opstr)) op = FPGA_LOADFS; @@ -314,8 +331,13 @@ U_BOOT_CMD(fpga, 6, 1, do_fpga, " dump\t[dev]\t\t\tLoad device to memory buffer\n" " info\t[dev]\t\t\tlist known device information\n" " load\t[dev] [address] [size]\tLoad device from memory buffer\n" + " loadp\t[dev] [address] [size]\t" + "Load device from memory buffer with partial bitstream\n" " loadb\t[dev] [address] [size]\t" "Load device from bitstream buffer (Xilinx only)\n" + " loadbp\t[dev] [address] [size]\t" + "Load device from bitstream buffer with partial bitstream" + "(Xilinx only)\n" " loadmk [dev] [address]\tLoad device generated with mkimage" #if defined(CONFIG_FIT) "\n" diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 35eedcc47e6..e18ee648897 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -92,10 +92,10 @@ static int mmc_load_fpga_image_fat(struct mmc *mmc) } #ifdef CONFIG_SPL_FPGA_BIT return fpga_loadbitstream(devnum, (char *)CONFIG_SPL_FPGA_LOAD_ADDR, - desc_xilinx->size); + desc_xilinx->size, BIT_FULL); #else return fpga_load(devnum, (const void *)CONFIG_SPL_FPGA_LOAD_ADDR, - desc_xilinx->size); + desc_xilinx->size, BIT_FULL); #endif } #endif diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index 1f61e7d10dc..914690cdbc7 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -173,7 +173,8 @@ int fpga_add(fpga_type devtype, void *desc) /* * Convert bitstream data and load into the fpga */ -int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size) +int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size, + bitstream_type bstype) { printf("Bitstream support not implemented for this FPGA device\n"); return FPGA_FAIL; @@ -210,7 +211,7 @@ int fpga_fsload(int devnum, const void *buf, size_t size, /* * Generic multiplexing code */ -int fpga_load(int devnum, const void *buf, size_t bsize) +int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype) { int ret_val = FPGA_FAIL; /* assume failure */ const fpga_desc *desc = fpga_validate(devnum, buf, bsize, @@ -220,7 +221,8 @@ int fpga_load(int devnum, const void *buf, size_t bsize) switch (desc->devtype) { case fpga_xilinx: #if defined(CONFIG_FPGA_XILINX) - ret_val = xilinx_load(desc->devdesc, buf, bsize); + ret_val = xilinx_load(desc->devdesc, buf, bsize, + bstype); #else fpga_no_sup((char *)__func__, "Xilinx devices"); #endif diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 8e9b1a2324d..224e245ae1c 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -35,7 +35,8 @@ static int xilinx_validate (Xilinx_desc * desc, char *fn); /* ------------------------------------------------------------------------- */ -int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) +int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, + bitstream_type bstype) { unsigned int length; unsigned int swapsize; @@ -138,7 +139,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) dataptr += 4; printf(" bytes in bitstream = %d\n", swapsize); - return fpga_load(devnum, dataptr, swapsize); + return fpga_load(devnum, dataptr, swapsize, bstype); } #ifdef CONFIG_FPGA_LOADFS @@ -172,7 +173,8 @@ int xilinx_fsload(Xilinx_desc *desc, const void *buf, size_t bsize, } #endif -int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) { int ret_val = FPGA_FAIL; /* assume a failure */ @@ -214,7 +216,7 @@ int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) #if defined(CONFIG_FPGA_ZYNQPL) PRINTF("%s: Launching the Zynq PL Loader...\n", __func__); - ret_val = zynq_load(desc, buf, bsize); + ret_val = zynq_load(desc, buf, bsize, bstype); #else printf("%s: No support for Zynq devices.\n", __func__); diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 3572bc9c1fa..e098d1389a1 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -198,7 +198,7 @@ static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen) return FPGA_SUCCESS; } -static int zynq_dma_xfer_init(u32 partialbit) +static int zynq_dma_xfer_init(bitstream_type bstype) { u32 status, control, isr_status; unsigned long ts; @@ -206,7 +206,7 @@ static int zynq_dma_xfer_init(u32 partialbit) /* Clear loopback bit */ clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK); - if (!partialbit) { + if (bstype != BIT_PARTIAL) { zynq_slcr_devcfg_disable(); /* Setting PCFG_PROG_B signal to high */ @@ -326,16 +326,11 @@ static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap) static int zynq_validate_bitstream(Xilinx_desc *desc, const void *buf, size_t bsize, u32 blocksize, u32 *swap, - u32 *partialbit) + bitstream_type *bstype) { u32 *buf_start; u32 diff; - /* Detect if we are going working with partial or full bitstream */ - if (bsize != desc->size) { - printf("%s: Working with partial bitstream\n", __func__); - *partialbit = 1; - } buf_start = check_data((u8 *)buf, blocksize, swap); if (!buf_start) @@ -355,7 +350,7 @@ static int zynq_validate_bitstream(Xilinx_desc *desc, const void *buf, return FPGA_FAIL; } - if (zynq_dma_xfer_init(*partialbit)) + if (zynq_dma_xfer_init(*bstype)) return FPGA_FAIL; return 0; @@ -367,7 +362,7 @@ int zynq_fsload(Xilinx_desc *desc, const void *buf, size_t bsize, { unsigned long ts; /* Timestamp */ u32 isr_status, swap; - u32 partialbit = 0; + bitstream_type bstype; u32 blocksize; u32 pos = 0; int fstype; @@ -385,8 +380,10 @@ int zynq_fsload(Xilinx_desc *desc, const void *buf, size_t bsize, if (fs_read(filename, (u32) buf, pos, blocksize) < 0) return FPGA_FAIL; + bstype = BIT_FULL; + if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap, - &partialbit)) + &bstype)) return FPGA_FAIL; dcache_disable(); @@ -435,17 +432,17 @@ int zynq_fsload(Xilinx_desc *desc, const void *buf, size_t bsize, debug("%s: FPGA config done\n", __func__); - if (!partialbit) + if (bstype != BIT_PARTIAL) zynq_slcr_devcfg_enable(); return FPGA_SUCCESS; } #endif -int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) { unsigned long ts; /* Timestamp */ - u32 partialbit = 0; u32 isr_status, swap; /* @@ -453,7 +450,7 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) * in chunks */ if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap, - &partialbit)) + &bstype)) return FPGA_FAIL; buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap); @@ -482,7 +479,7 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) debug("%s: FPGA config done\n", __func__); - if (!partialbit) + if (bstype != BIT_PARTIAL) zynq_slcr_devcfg_enable(); return FPGA_SUCCESS; diff --git a/include/fpga.h b/include/fpga.h index 615d453963e..16f0f6940fc 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -45,17 +45,25 @@ typedef struct { /* typedef fpga_desc */ } fpga_fs_info; #endif +typedef enum { + BIT_FULL = 0, + BIT_PARTIAL, + BIT_COMPRESSED +} bitstream_type; + /* root function definitions */ extern void fpga_init(void); extern int fpga_add(fpga_type devtype, void *desc); extern int fpga_count(void); extern const fpga_desc *const fpga_get_desc(int devnum); -extern int fpga_load(int devnum, const void *buf, size_t bsize); +extern int fpga_load(int devnum, const void *buf, size_t bsize, + bitstream_type bstype); #ifdef CONFIG_FPGA_LOADFS extern int fpga_fsload(int devnum, const void *buf, size_t size, fpga_fs_info *fpga_fsinfo); #endif -extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size); +extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, + bitstream_type bstype); extern int fpga_dump(int devnum, const void *buf, size_t bsize); extern int fpga_info(int devnum); extern const fpga_desc *const fpga_validate(int devnum, const void *buf, diff --git a/include/xilinx.h b/include/xilinx.h index 2d8f0e225c8..ecc5d6a2189 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -45,7 +45,8 @@ typedef struct { /* typedef Xilinx_desc */ /* Generic Xilinx Functions *********************************************************************/ -extern int xilinx_load(Xilinx_desc *desc, const void *image, size_t size); +extern int xilinx_load(Xilinx_desc *desc, const void *image, size_t size, + bitstream_type bstype); #ifdef CONFIG_FPGA_LOADFS extern int xilinx_fsload(Xilinx_desc *desc, const void *buf, size_t bsize, fpga_fs_info *fpga_fsinfo); diff --git a/include/zynqpl.h b/include/zynqpl.h index 224c841b550..4b46a720906 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -12,7 +12,8 @@ #include -extern int zynq_load(Xilinx_desc *desc, const void *image, size_t size); +extern int zynq_load(Xilinx_desc *desc, const void *image, size_t size, + bitstream_type bstype); #ifdef CONFIG_FPGA_LOADFS extern int zynq_fsload(Xilinx_desc *desc, const void *buf, size_t bsize, fpga_fs_info *fsinfo);