From: Irina Ryapolova <irina.ryapolova@syntacore.com>
Date: Wed, 20 Mar 2024 17:28:28 +0000 (+0300)
Subject: target/riscv: Fix mode in riscv_tlb_fill
X-Git-Tag: v8.2.3~47
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=38f36fc56855de889c1569d02a238867253aac21;p=thirdparty%2Fqemu.git

target/riscv: Fix mode in riscv_tlb_fill

Need to convert mmu_idx to privilege mode for PMP function.

Signed-off-by: Irina Ryapolova <irina.ryapolova@syntacore.com>
Fixes: b297129ae1 ("target/riscv: propagate PMP permission to TLB page")
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240320172828.23965-1-irina.ryapolova@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
(cherry picked from commit e06adebb08325c39e4c9b652139426c10f021abb)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
---

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e7e23b34f45..da1a153abf7 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1301,7 +1301,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     bool two_stage_lookup = mmuidx_2stage(mmu_idx);
     bool two_stage_indirect_error = false;
     int ret = TRANSLATE_FAIL;
-    int mode = mmu_idx;
+    int mode = mmuidx_priv(mmu_idx);
     /* default TLB page size */
     target_ulong tlb_size = TARGET_PAGE_SIZE;