From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 15 Feb 2017 09:13:22 +0000 (+0100)
Subject: arm64: zynqmp: Fix psu_init* external functions
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=393856b8638a9c6b31c9700c9ae4e81b5def2265;p=thirdparty%2Fu-boot.git

arm64: zynqmp: Fix psu_init* external functions

In older vivado version some psu_init* files didn't contain prog_reg
function that's why it was added to xil_io.h.
The same with mask*() which were missing.

From some pre v2017.1 these issues were fixed that's why
some functions were commented in origin psu_init* files.

This patch adds prog_reg() and mask*() to psu_init* files
where it is missing and remove comment from files which have
prog_reg() already.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h
index eeff0ab3f8d..679d234b070 100644
--- a/board/xilinx/zynqmp/xil_io.h
+++ b/board/xilinx/zynqmp/xil_io.h
@@ -33,23 +33,9 @@ int Xil_In32(unsigned long addr)
 	return readl(addr);
 }
 
-__weak void prog_reg(unsigned long addr, unsigned long mask,
-		     unsigned long shift, unsigned long value)
-{
-	int rdata = 0;
-
-	rdata = Xil_In32(addr);
-	rdata = rdata & (~mask);
-	rdata = rdata | (value << shift);
-	Xil_Out32(addr,rdata);
-}
-
-void mask_delay(u32 delay);
 void usleep(u32 sleep)
 {
 	udelay(sleep);
 }
-int mask_poll(u32 add, u32 mask);
-int mask_pollOnValue(u32 add, u32 mask, u32 value);
 
 #endif /* XIL_IO_H */
diff --git a/board/xilinx/zynqmp/zynqmp-ep108/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-ep108/psu_init_gpl.c
index bb98c120f92..bad074fdc6b 100644
--- a/board/xilinx/zynqmp/zynqmp-ep108/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-ep108/psu_init_gpl.c
@@ -30,6 +30,22 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
 	Xil_Out32 (offset, RegVal);
 }
 
+int mask_pollOnValue(u32 add, u32 mask, u32 value);
+int mask_poll(u32 add, u32 mask);
+void mask_delay(u32 delay);
+u32 mask_read(u32 add, u32 mask);
+
+void prog_reg(unsigned long addr, unsigned long mask,
+		     unsigned long shift, unsigned long value)
+{
+	int rdata = 0;
+
+	rdata = Xil_In32(addr);
+	rdata = rdata & (~mask);
+	rdata = rdata | (value << shift);
+	Xil_Out32(addr,rdata);
+}
+
 unsigned long psu_pll_init_data() {
 		// : RPLL INIT
 		/*Register : RPLL_CFG @ 0XFF5E0034</p>
diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c
index 99681d51144..e14c43b0623 100644
--- a/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c
@@ -30,6 +30,22 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
 	Xil_Out32 (offset, RegVal);
 }
 
+int mask_pollOnValue(u32 add, u32 mask, u32 value);
+int mask_poll(u32 add, u32 mask);
+void mask_delay(u32 delay);
+u32 mask_read(u32 add, u32 mask);
+
+void prog_reg(unsigned long addr, unsigned long mask,
+		     unsigned long shift, unsigned long value)
+{
+	int rdata = 0;
+
+	rdata = Xil_In32(addr);
+	rdata = rdata & (~mask);
+	rdata = rdata | (value << shift);
+	Xil_Out32(addr,rdata);
+}
+
 unsigned long psu_pll_init_data() {
 		// : RPLL INIT
 		/*Register : RPLL_CFG @ 0XFF5E0034</p>
diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c
index ebd93d789be..d0b0674c816 100644
--- a/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c
@@ -30,6 +30,22 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
 	Xil_Out32 (offset, RegVal);
 }
 
+int mask_pollOnValue(u32 add, u32 mask, u32 value);
+int mask_poll(u32 add, u32 mask);
+void mask_delay(u32 delay);
+u32 mask_read(u32 add, u32 mask);
+
+void prog_reg(unsigned long addr, unsigned long mask,
+		     unsigned long shift, unsigned long value)
+{
+	int rdata = 0;
+
+	rdata = Xil_In32(addr);
+	rdata = rdata & (~mask);
+	rdata = rdata | (value << shift);
+	Xil_Out32(addr,rdata);
+}
+
 unsigned long psu_pll_init_data() {
 		// : RPLL INIT
 		/*Register : RPLL_CFG @ 0XFF5E0034</p>
diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c
index 6b3d75e9dc7..2f86cb14081 100644
--- a/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c
@@ -30,6 +30,22 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
 	Xil_Out32 (offset, RegVal);
 }
 
+int mask_pollOnValue(u32 add, u32 mask, u32 value);
+int mask_poll(u32 add, u32 mask);
+void mask_delay(u32 delay);
+u32 mask_read(u32 add, u32 mask);
+
+void prog_reg(unsigned long addr, unsigned long mask,
+		     unsigned long shift, unsigned long value)
+{
+	int rdata = 0;
+
+	rdata = Xil_In32(addr);
+	rdata = rdata & (~mask);
+	rdata = rdata | (value << shift);
+	Xil_Out32(addr,rdata);
+}
+
 unsigned long psu_pll_init_data() {
 		// : RPLL INIT
 		/*Register : RPLL_CFG @ 0XFF5E0034</p>
diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c
index e02361dbf1a..0827dd5f65e 100644
--- a/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c
@@ -30,6 +30,22 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
 	Xil_Out32 (offset, RegVal);
 }
 
+int mask_pollOnValue(u32 add, u32 mask, u32 value);
+int mask_poll(u32 add, u32 mask);
+void mask_delay(u32 delay);
+u32 mask_read(u32 add, u32 mask);
+
+void prog_reg(unsigned long addr, unsigned long mask,
+		     unsigned long shift, unsigned long value)
+{
+	int rdata = 0;
+
+	rdata = Xil_In32(addr);
+	rdata = rdata & (~mask);
+	rdata = rdata | (value << shift);
+	Xil_Out32(addr,rdata);
+}
+
 unsigned long psu_pll_init_data() {
 		// : RPLL INIT
 		/*Register : RPLL_CFG @ 0XFF5E0034</p>
diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c
index 85b31be046f..0d3f0d66701 100644
--- a/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c
@@ -30,6 +30,22 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
 	Xil_Out32 (offset, RegVal);
 }
 
+int mask_pollOnValue(u32 add, u32 mask, u32 value);
+int mask_poll(u32 add, u32 mask);
+void mask_delay(u32 delay);
+u32 mask_read(u32 add, u32 mask);
+
+void prog_reg(unsigned long addr, unsigned long mask,
+		     unsigned long shift, unsigned long value)
+{
+	int rdata = 0;
+
+	rdata = Xil_In32(addr);
+	rdata = rdata & (~mask);
+	rdata = rdata | (value << shift);
+	Xil_Out32(addr,rdata);
+}
+
 unsigned long psu_pll_init_data() {
 		// : RPLL INIT
 		/*Register : RPLL_CFG @ 0XFF5E0034</p>
diff --git a/board/xilinx/zynqmp/zynqmp-zcu100-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu100-revA/psu_init_gpl.c
index d0546390560..b84f819556b 100644
--- a/board/xilinx/zynqmp/zynqmp-zcu100-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu100-revA/psu_init_gpl.c
@@ -38,7 +38,7 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
 	RegVal |= (val & mask);
 	Xil_Out32 (offset, RegVal);
 }
-/*
+
 	void prog_reg (unsigned long addr, unsigned long mask, unsigned long shift, unsigned long value) {
 	    int rdata =0;
 	    rdata  = Xil_In32(addr);
@@ -46,7 +46,7 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
 	    rdata  = rdata | (value << shift);
 	    Xil_Out32(addr,rdata);
 	    }
-*/
+
 unsigned long psu_pll_init_data() {
 		// : RPLL INIT
 		/*Register : RPLL_CFG @ 0XFF5E0034</p>
diff --git a/board/xilinx/zynqmp/zynqmp-zcu100-revB/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu100-revB/psu_init_gpl.c
index 4760d957e23..d7e538998f6 100644
--- a/board/xilinx/zynqmp/zynqmp-zcu100-revB/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu100-revB/psu_init_gpl.c
@@ -38,7 +38,7 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
 	RegVal |= (val & mask);
 	Xil_Out32 (offset, RegVal);
 }
-/*
+
 	void prog_reg (unsigned long addr, unsigned long mask, unsigned long shift, unsigned long value) {
 	    int rdata =0;
 	    rdata  = Xil_In32(addr);
@@ -46,7 +46,7 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
 	    rdata  = rdata | (value << shift);
 	    Xil_Out32(addr,rdata);
 	    }
-*/
+
 unsigned long psu_pll_init_data() {
 		// : RPLL INIT
 		/*Register : RPLL_CFG @ 0XFF5E0034</p>
diff --git a/board/xilinx/zynqmp/zynqmp-zcu102/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu102/psu_init_gpl.c
index 6f6a516315e..4bc732f69e2 100644
--- a/board/xilinx/zynqmp/zynqmp-zcu102/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu102/psu_init_gpl.c
@@ -38,7 +38,7 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
 	RegVal |= (val & mask);
 	Xil_Out32 (offset, RegVal);
 }
-/*
+
 	void prog_reg (unsigned long addr, unsigned long mask, unsigned long shift, unsigned long value) {
 	    int rdata =0;
 	    rdata  = Xil_In32(addr);
@@ -46,7 +46,7 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
 	    rdata  = rdata | (value << shift);
 	    Xil_Out32(addr,rdata);
 	    }
-*/
+
 unsigned long psu_pll_init_data() {
 		// : RPLL INIT
 		/*Register : RPLL_CFG @ 0XFF5E0034</p>
diff --git a/board/xilinx/zynqmp/zynqmp-zcu106/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106/psu_init_gpl.c
index 2146fe005f4..58da9584b84 100644
--- a/board/xilinx/zynqmp/zynqmp-zcu106/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu106/psu_init_gpl.c
@@ -38,7 +38,7 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
 	RegVal |= (val & mask);
 	Xil_Out32 (offset, RegVal);
 }
-/*
+
 	void prog_reg (unsigned long addr, unsigned long mask, unsigned long shift, unsigned long value) {
 	    int rdata =0;
 	    rdata  = Xil_In32(addr);
@@ -46,7 +46,7 @@ static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned l
 	    rdata  = rdata | (value << shift);
 	    Xil_Out32(addr,rdata);
 	    }
-*/
+
 unsigned long psu_pll_init_data() {
 		// : RPLL INIT
 		/*Register : RPLL_CFG @ 0XFF5E0034</p>