From: Qiuxu Zhuo Date: Wed, 19 Nov 2025 20:11:40 +0000 (-0800) Subject: EDAC/skx_common: Extend the maximum number of DRAM chip row bits X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=39abdcbdad597b1ac3dabd44a757de91b87c683a;p=thirdparty%2Fkernel%2Flinux.git EDAC/skx_common: Extend the maximum number of DRAM chip row bits The allowed maximum number of row bits for DRAM chips in the Diamond Rapids server processor is up to 19. Extend the current maximum row bits from 18 to 19. Tested-by: Yi Lai Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck Link: https://patch.msgid.link/20251119134132.2389472-6-qiuxu.zhuo@intel.com --- diff --git a/drivers/edac/skx_common.c b/drivers/edac/skx_common.c index 32a4ef27a987b..3276afe439223 100644 --- a/drivers/edac/skx_common.c +++ b/drivers/edac/skx_common.c @@ -451,7 +451,7 @@ static int skx_get_dimm_attr(u32 reg, int lobit, int hibit, int add, } #define numrank(reg) skx_get_dimm_attr(reg, 12, 13, 0, 0, 2, "ranks") -#define numrow(reg) skx_get_dimm_attr(reg, 2, 4, 12, 1, 6, "rows") +#define numrow(reg) skx_get_dimm_attr(reg, 2, 4, 12, 1, 7, "rows") #define numcol(reg) skx_get_dimm_attr(reg, 0, 1, 10, 0, 2, "cols") int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,