From: Jonas Jelonek Date: Sun, 19 Jul 2026 18:53:38 +0000 (+0000) Subject: realtek: pcs: rtl931x: fix 1000Base-X config X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=39cd3f8954af90ebd20fc90eb77d1b519b320b39;p=thirdparty%2Fopenwrt.git realtek: pcs: rtl931x: fix 1000Base-X config Commit 7899dfa6ef71 ("realtek: pcs: rtl931x: separate and reuse 1000base-x config") introduced an issue by accident, using the register value 0x12 instead of 0x13. A regression hasn't been noticed before, for yet unknown reasons the 1000Base-X still worked here and there. Probably due to some external setup. However, this currently breaks 1000Base-X functionality on at least one switch. Correcting the register value instantly restores 1000Base-X, allowing the link to come up. It is unclear yet what this field means, according to the SerDes register defines from related RTL8295 this might be TX mode configuration field. Also add another write which is present in several SDK versions. Referring from related RTL8295, this might be a field called EN_LINK_FIB1G, enabling 1000Base-X operation. Fixes: 7899dfa6ef71 ("realtek: pcs: rtl931x: separate and reuse 1000base-x config") Link: https://github.com/openwrt/openwrt/pull/24310 Signed-off-by: Jonas Jelonek --- diff --git a/target/linux/realtek/files-6.18/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.18/drivers/net/pcs/pcs-rtl-otto.c index 12f411db48c..9da31a8bab6 100644 --- a/target/linux/realtek/files-6.18/drivers/net/pcs/pcs-rtl-otto.c +++ b/target/linux/realtek/files-6.18/drivers/net/pcs/pcs-rtl-otto.c @@ -3658,10 +3658,11 @@ static int rtpcs_931x_sds_config_attachment(struct rtpcs_serdes *sds, static int rtpcs_931x_sds_config_fiber_1g(struct rtpcs_serdes *sds) { - rtpcs_sds_write_bits(sds, DIGI_1(PAGE_FIB_EXT), 0x12, 15, 14, 0x0); + rtpcs_sds_write_bits(sds, DIGI_1(PAGE_FIB_EXT), 0x13, 15, 14, 0x0); rtpcs_sds_write_bits(sds, DIGI_1(PAGE_FIB), 0x0, 6, 6, 0x1); rtpcs_sds_write_bits(sds, DIGI_1(PAGE_FIB), 0x0, 13, 13, 0x0); + rtpcs_sds_write_bits(sds, DIGI_1(PAGE_SDS), 0x4, 2, 2, 0x1); /* EN_LINK_FIB1G */ return 0; }