From: Mauro Lima Date: Wed, 12 Oct 2022 15:21:35 +0000 (-0300) Subject: spi: intel: Fix the offset to get the 64K erase opcode X-Git-Tag: v6.0.10~303 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=3c8412afceb8b69fa58173d2b27d5073438a08b1;p=thirdparty%2Fkernel%2Fstable.git spi: intel: Fix the offset to get the 64K erase opcode [ Upstream commit 6a43cd02ddbc597dc9a1f82c1e433f871a2f6f06 ] According to documentation, the 64K erase opcode is located in VSCC range [16:23] instead of [8:15]. Use the proper value to shift the mask over the correct range. Signed-off-by: Mauro Lima Reviewed-by: Mika Westerberg Link: https://lore.kernel.org/r/20221012152135.28353-1-mauro.lima@eclypsium.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- diff --git a/drivers/spi/spi-intel.c b/drivers/spi/spi-intel.c index 3f6db482b6c71..a1dbd71bf83ef 100644 --- a/drivers/spi/spi-intel.c +++ b/drivers/spi/spi-intel.c @@ -114,7 +114,7 @@ #define ERASE_OPCODE_SHIFT 8 #define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) #define ERASE_64K_OPCODE_SHIFT 16 -#define ERASE_64K_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) +#define ERASE_64K_OPCODE_MASK (0xff << ERASE_64K_OPCODE_SHIFT) #define INTEL_SPI_TIMEOUT 5000 /* ms */ #define INTEL_SPI_FIFO_SZ 64