From: Jim Shu <jim.shu@sifive.com>
Date: Mon, 19 May 2025 14:35:17 +0000 (+0800)
Subject: target/riscv: Fix VSTIP bit in sstc extension.
X-Git-Tag: v10.1.0-rc0~31^2~37
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=3cb2edae740121cf5da3a9adb8190051e866eb01;p=thirdparty%2Fqemu.git

target/riscv: Fix VSTIP bit in sstc extension.

VSTIP is only writable when both [mh]envcfg.STCE is enabled, or it will
revert it's defined behavior as if sstc extension is not implemented.

Signed-off-by: Jim Shu <jim.shu@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250519143518.11086-4-jim.shu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index fb149721691..d8102943dde 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3651,7 +3651,14 @@ static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
     if (riscv_cpu_cfg(env)->ext_sstc && (env->priv == PRV_M) &&
         get_field(env->menvcfg, MENVCFG_STCE)) {
         /* sstc extension forbids STIP & VSTIP to be writeable in mip */
-        mask = mask & ~(MIP_STIP | MIP_VSTIP);
+
+        /* STIP is not writable when menvcfg.STCE is enabled. */
+        mask = mask & ~MIP_STIP;
+
+        /* VSTIP is not writable when both [mh]envcfg.STCE are enabled. */
+        if (get_field(env->henvcfg, HENVCFG_STCE)) {
+            mask = mask & ~MIP_VSTIP;
+        }
     }
 
     if (mask) {