From: Greg Kroah-Hartman Date: Wed, 1 Apr 2020 15:17:03 +0000 (+0200) Subject: 4.19-stable patches X-Git-Tag: v5.6.2~3 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=3ec5473712098f4ff4ffe14527712cb07c7d9f4c;p=thirdparty%2Fkernel%2Fstable-queue.git 4.19-stable patches added patches: arm-bcm2835-rpi-zero-w-add-missing-pinctrl-name.patch arm-dts-imx6-phycore-som-fix-arm-and-soc-minimum-voltage.patch arm-dts-n900-fix-onenand-timings.patch arm-dts-oxnas-fix-clear-mask-property.patch arm64-alternative-fix-build-with-clang-integrated-assembler.patch arm64-dts-ls1043a-rdb-correct-rgmii-delay-mode-to-rgmii-id.patch arm64-dts-ls1046ardb-set-rgmii-interfaces-to-rgmii_id-mode.patch gpiolib-acpi-add-quirk-to-ignore-ec-wakeups-on-hp-x2-10-cht-axp288-model.patch net-ks8851-ml-fix-io-operations-again.patch perf-map-fix-off-by-one-in-strncpy-size-argument.patch --- diff --git a/queue-4.19/arm-bcm2835-rpi-zero-w-add-missing-pinctrl-name.patch b/queue-4.19/arm-bcm2835-rpi-zero-w-add-missing-pinctrl-name.patch new file mode 100644 index 00000000000..1826f835b1f --- /dev/null +++ b/queue-4.19/arm-bcm2835-rpi-zero-w-add-missing-pinctrl-name.patch @@ -0,0 +1,31 @@ +From 6687c201fdc3139315c2ea7ef96c157672805cdc Mon Sep 17 00:00:00 2001 +From: Nick Hudson +Date: Thu, 12 Mar 2020 09:03:45 +0000 +Subject: ARM: bcm2835-rpi-zero-w: Add missing pinctrl name + +From: Nick Hudson + +commit 6687c201fdc3139315c2ea7ef96c157672805cdc upstream. + +Define the sdhci pinctrl state as "default" so it gets applied +correctly and to match all other RPis. + +Fixes: 2c7c040c73e9 ("ARM: dts: bcm2835: Add Raspberry Pi Zero W") +Signed-off-by: Nick Hudson +Signed-off-by: Florian Fainelli +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/boot/dts/bcm2835-rpi-zero-w.dts | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts ++++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts +@@ -118,6 +118,7 @@ + &sdhci { + #address-cells = <1>; + #size-cells = <0>; ++ pinctrl-names = "default"; + pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; diff --git a/queue-4.19/arm-dts-imx6-phycore-som-fix-arm-and-soc-minimum-voltage.patch b/queue-4.19/arm-dts-imx6-phycore-som-fix-arm-and-soc-minimum-voltage.patch new file mode 100644 index 00000000000..623d1ad5c52 --- /dev/null +++ b/queue-4.19/arm-dts-imx6-phycore-som-fix-arm-and-soc-minimum-voltage.patch @@ -0,0 +1,45 @@ +From 636b45b8efa91db05553840b6c0120d6fa6b94fa Mon Sep 17 00:00:00 2001 +From: Marco Felsch +Date: Thu, 27 Feb 2020 12:02:46 +0100 +Subject: ARM: dts: imx6: phycore-som: fix arm and soc minimum voltage +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Marco Felsch + +commit 636b45b8efa91db05553840b6c0120d6fa6b94fa upstream. + +The current set minimum voltage of 730000µV seems to be wrong. I don't +know the document which specifies that but the imx6qdl datasheets says +that the minimum voltage should be 0.925V for VDD_ARM (LDO bypassed, +lowest opp) and 1.15V for VDD_SOC (LDO bypassed, lowest opp). + +Fixes: ddec5d1c0047 ("ARM: dts: imx6: Add initial support for phyCORE-i.MX 6 SOM") +Signed-off-by: Marco Felsch +Signed-off-by: Shawn Guo +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi +@@ -107,14 +107,14 @@ + regulators { + vdd_arm: buck1 { + regulator-name = "vdd_arm"; +- regulator-min-microvolt = <730000>; ++ regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1380000>; + regulator-always-on; + }; + + vdd_soc: buck2 { + regulator-name = "vdd_soc"; +- regulator-min-microvolt = <730000>; ++ regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1380000>; + regulator-always-on; + }; diff --git a/queue-4.19/arm-dts-n900-fix-onenand-timings.patch b/queue-4.19/arm-dts-n900-fix-onenand-timings.patch new file mode 100644 index 00000000000..3f66f84adea --- /dev/null +++ b/queue-4.19/arm-dts-n900-fix-onenand-timings.patch @@ -0,0 +1,92 @@ +From 0c5220a3c1242c7a2451570ed5f5af69620aac75 Mon Sep 17 00:00:00 2001 +From: Arthur Demchenkov +Date: Sun, 8 Mar 2020 22:19:33 +0300 +Subject: ARM: dts: N900: fix onenand timings + +From: Arthur Demchenkov + +commit 0c5220a3c1242c7a2451570ed5f5af69620aac75 upstream. + +Commit a758f50f10cf ("mtd: onenand: omap2: Configure driver from DT") +started using DT specified timings for GPMC, and as a result the +OneNAND stopped working on N900 as we had wrong values in the DT. +Fix by updating the values to bootloader timings that have been tested +to be working on Nokia N900 with OneNAND manufacturers: Samsung, +Numonyx. + +Fixes: a758f50f10cf ("mtd: onenand: omap2: Configure driver from DT") +Signed-off-by: Arthur Demchenkov +Tested-by: Merlijn Wajer +Reviewed-by: Roger Quadros +Signed-off-by: Tony Lindgren +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/boot/dts/omap3-n900.dts | 44 ++++++++++++++++++++++++--------------- + 1 file changed, 28 insertions(+), 16 deletions(-) + +--- a/arch/arm/boot/dts/omap3-n900.dts ++++ b/arch/arm/boot/dts/omap3-n900.dts +@@ -852,34 +852,46 @@ + compatible = "ti,omap2-onenand"; + reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ + ++ /* ++ * These timings are based on CONFIG_OMAP_GPMC_DEBUG=y reported ++ * bootloader set values when booted with v5.1 ++ * (OneNAND Manufacturer: Samsung): ++ * ++ * cs0 GPMC_CS_CONFIG1: 0xfb001202 ++ * cs0 GPMC_CS_CONFIG2: 0x00111100 ++ * cs0 GPMC_CS_CONFIG3: 0x00020200 ++ * cs0 GPMC_CS_CONFIG4: 0x11001102 ++ * cs0 GPMC_CS_CONFIG5: 0x03101616 ++ * cs0 GPMC_CS_CONFIG6: 0x90060000 ++ */ + gpmc,sync-read; + gpmc,sync-write; + gpmc,burst-length = <16>; + gpmc,burst-read; + gpmc,burst-wrap; + gpmc,burst-write; +- gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ +- gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */ ++ gpmc,device-width = <2>; ++ gpmc,mux-add-data = <2>; + gpmc,cs-on-ns = <0>; +- gpmc,cs-rd-off-ns = <87>; +- gpmc,cs-wr-off-ns = <87>; ++ gpmc,cs-rd-off-ns = <102>; ++ gpmc,cs-wr-off-ns = <102>; + gpmc,adv-on-ns = <0>; +- gpmc,adv-rd-off-ns = <10>; +- gpmc,adv-wr-off-ns = <10>; +- gpmc,oe-on-ns = <15>; +- gpmc,oe-off-ns = <87>; ++ gpmc,adv-rd-off-ns = <12>; ++ gpmc,adv-wr-off-ns = <12>; ++ gpmc,oe-on-ns = <12>; ++ gpmc,oe-off-ns = <102>; + gpmc,we-on-ns = <0>; +- gpmc,we-off-ns = <87>; +- gpmc,rd-cycle-ns = <112>; +- gpmc,wr-cycle-ns = <112>; +- gpmc,access-ns = <81>; +- gpmc,page-burst-access-ns = <15>; ++ gpmc,we-off-ns = <102>; ++ gpmc,rd-cycle-ns = <132>; ++ gpmc,wr-cycle-ns = <132>; ++ gpmc,access-ns = <96>; ++ gpmc,page-burst-access-ns = <18>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,wait-monitoring-ns = <0>; +- gpmc,clk-activation-ns = <5>; +- gpmc,wr-data-mux-bus-ns = <30>; +- gpmc,wr-access-ns = <81>; ++ gpmc,clk-activation-ns = <6>; ++ gpmc,wr-data-mux-bus-ns = <36>; ++ gpmc,wr-access-ns = <96>; + gpmc,sync-clk-ps = <15000>; + + /* diff --git a/queue-4.19/arm-dts-oxnas-fix-clear-mask-property.patch b/queue-4.19/arm-dts-oxnas-fix-clear-mask-property.patch new file mode 100644 index 00000000000..ac8d1b6ea5b --- /dev/null +++ b/queue-4.19/arm-dts-oxnas-fix-clear-mask-property.patch @@ -0,0 +1,50 @@ +From deeabb4c1341a12bf8b599e6a2f4cfa4fd74738c Mon Sep 17 00:00:00 2001 +From: Sungbo Eo +Date: Sat, 21 Mar 2020 23:36:53 +0900 +Subject: ARM: dts: oxnas: Fix clear-mask property + +From: Sungbo Eo + +commit deeabb4c1341a12bf8b599e6a2f4cfa4fd74738c upstream. + +Disable all rps-irq interrupts during driver initialization to prevent +an accidental interrupt on GIC. + +Fixes: 84316f4ef141 ("ARM: boot: dts: Add Oxford Semiconductor OX810SE dtsi") +Fixes: 38d4a53733f5 ("ARM: dts: Add support for OX820 and Pogoplug V3") +Signed-off-by: Sungbo Eo +Acked-by: Neil Armstrong +Signed-off-by: Neil Armstrong +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/boot/dts/ox810se.dtsi | 4 ++-- + arch/arm/boot/dts/ox820.dtsi | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +--- a/arch/arm/boot/dts/ox810se.dtsi ++++ b/arch/arm/boot/dts/ox810se.dtsi +@@ -322,8 +322,8 @@ + interrupt-controller; + reg = <0 0x200>; + #interrupt-cells = <1>; +- valid-mask = <0xFFFFFFFF>; +- clear-mask = <0>; ++ valid-mask = <0xffffffff>; ++ clear-mask = <0xffffffff>; + }; + + timer0: timer@200 { +--- a/arch/arm/boot/dts/ox820.dtsi ++++ b/arch/arm/boot/dts/ox820.dtsi +@@ -239,8 +239,8 @@ + reg = <0 0x200>; + interrupts = ; + #interrupt-cells = <1>; +- valid-mask = <0xFFFFFFFF>; +- clear-mask = <0>; ++ valid-mask = <0xffffffff>; ++ clear-mask = <0xffffffff>; + }; + + timer0: timer@200 { diff --git a/queue-4.19/arm64-alternative-fix-build-with-clang-integrated-assembler.patch b/queue-4.19/arm64-alternative-fix-build-with-clang-integrated-assembler.patch new file mode 100644 index 00000000000..3ae6074d132 --- /dev/null +++ b/queue-4.19/arm64-alternative-fix-build-with-clang-integrated-assembler.patch @@ -0,0 +1,47 @@ +From 6f5459da2b8736720afdbd67c4bd2d1edba7d0e3 Mon Sep 17 00:00:00 2001 +From: Ilie Halip +Date: Thu, 19 Mar 2020 23:45:28 +0200 +Subject: arm64: alternative: fix build with clang integrated assembler + +From: Ilie Halip + +commit 6f5459da2b8736720afdbd67c4bd2d1edba7d0e3 upstream. + +Building an arm64 defconfig with clang's integrated assembler, this error +occurs: + :2:2: error: unrecognized instruction mnemonic + _ASM_EXTABLE 9999b, 9f + ^ + arch/arm64/mm/cache.S:50:1: note: while in macro instantiation + user_alt 9f, "dc cvau, x4", "dc civac, x4", 0 + ^ + +While GNU as seems fine with case-sensitive macro instantiations, clang +doesn't, so use the actual macro name (_asm_extable) as in the rest of +the file. + +Also checked that the generated assembly matches the GCC output. + +Reviewed-by: Nick Desaulniers +Tested-by: Nick Desaulniers +Fixes: 290622efc76e ("arm64: fix "dc cvau" cache operation on errata-affected core") +Link: https://github.com/ClangBuiltLinux/linux/issues/924 +Signed-off-by: Ilie Halip +Signed-off-by: Will Deacon +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm64/include/asm/alternative.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/include/asm/alternative.h ++++ b/arch/arm64/include/asm/alternative.h +@@ -221,7 +221,7 @@ alternative_endif + + .macro user_alt, label, oldinstr, newinstr, cond + 9999: alternative_insn "\oldinstr", "\newinstr", \cond +- _ASM_EXTABLE 9999b, \label ++ _asm_extable 9999b, \label + .endm + + /* diff --git a/queue-4.19/arm64-dts-ls1043a-rdb-correct-rgmii-delay-mode-to-rgmii-id.patch b/queue-4.19/arm64-dts-ls1043a-rdb-correct-rgmii-delay-mode-to-rgmii-id.patch new file mode 100644 index 00000000000..db8e9705d31 --- /dev/null +++ b/queue-4.19/arm64-dts-ls1043a-rdb-correct-rgmii-delay-mode-to-rgmii-id.patch @@ -0,0 +1,50 @@ +From 4022d808c45277693ea86478fab1f081ebf997e8 Mon Sep 17 00:00:00 2001 +From: Madalin Bucur +Date: Mon, 16 Mar 2020 14:05:57 +0200 +Subject: arm64: dts: ls1043a-rdb: correct RGMII delay mode to rgmii-id + +From: Madalin Bucur + +commit 4022d808c45277693ea86478fab1f081ebf997e8 upstream. + +The correct setting for the RGMII ports on LS1043ARDB is to +enable delay on both Rx and Tx so the interface mode used must +be PHY_INTERFACE_MODE_RGMII_ID. + +Since commit 1b3047b5208a80 ("net: phy: realtek: add support for +configuring the RX delay on RTL8211F") the Realtek 8211F PHY driver +has control over the RGMII RX delay and it is disabling it for +RGMII_TXID. The LS1043ARDB uses two such PHYs in RGMII_ID mode but +in the device tree the mode was described as "rgmii_txid". +This issue was not apparent at the time as the PHY driver took the +same action for RGMII_TXID and RGMII_ID back then but it became +visible (RX no longer working) after the above patch. + +Changing the phy-connection-type to "rgmii-id" to address the issue. + +Fixes: bf02f2ffe59c ("arm64: dts: add LS1043A DPAA FMan support") +Signed-off-by: Madalin Bucur +Signed-off-by: David S. Miller +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts +@@ -118,12 +118,12 @@ + + ethernet@e4000 { + phy-handle = <&rgmii_phy1>; +- phy-connection-type = "rgmii-txid"; ++ phy-connection-type = "rgmii-id"; + }; + + ethernet@e6000 { + phy-handle = <&rgmii_phy2>; +- phy-connection-type = "rgmii-txid"; ++ phy-connection-type = "rgmii-id"; + }; + + ethernet@e8000 { diff --git a/queue-4.19/arm64-dts-ls1046ardb-set-rgmii-interfaces-to-rgmii_id-mode.patch b/queue-4.19/arm64-dts-ls1046ardb-set-rgmii-interfaces-to-rgmii_id-mode.patch new file mode 100644 index 00000000000..688e94812fe --- /dev/null +++ b/queue-4.19/arm64-dts-ls1046ardb-set-rgmii-interfaces-to-rgmii_id-mode.patch @@ -0,0 +1,47 @@ +From d79e9d7c1e4ba5f95f2ff3541880c40ea9722212 Mon Sep 17 00:00:00 2001 +From: Madalin Bucur +Date: Mon, 16 Mar 2020 14:05:58 +0200 +Subject: arm64: dts: ls1046ardb: set RGMII interfaces to RGMII_ID mode + +From: Madalin Bucur + +commit d79e9d7c1e4ba5f95f2ff3541880c40ea9722212 upstream. + +The correct setting for the RGMII ports on LS1046ARDB is to +enable delay on both Rx and Tx so the interface mode used must +be PHY_INTERFACE_MODE_RGMII_ID. + +Since commit 1b3047b5208a80 ("net: phy: realtek: add support for +configuring the RX delay on RTL8211F") the Realtek 8211F PHY driver +has control over the RGMII RX delay and it is disabling it for +RGMII_TXID. The LS1046ARDB uses two such PHYs in RGMII_ID mode but +in the device tree the mode was described as "rgmii". + +Changing the phy-connection-type to "rgmii-id" to address the issue. + +Fixes: 3fa395d2c48a ("arm64: dts: add LS1046A DPAA FMan nodes") +Signed-off-by: Madalin Bucur +Signed-off-by: David S. Miller +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts +@@ -125,12 +125,12 @@ + &fman0 { + ethernet@e4000 { + phy-handle = <&rgmii_phy1>; +- phy-connection-type = "rgmii"; ++ phy-connection-type = "rgmii-id"; + }; + + ethernet@e6000 { + phy-handle = <&rgmii_phy2>; +- phy-connection-type = "rgmii"; ++ phy-connection-type = "rgmii-id"; + }; + + ethernet@e8000 { diff --git a/queue-4.19/gpiolib-acpi-add-quirk-to-ignore-ec-wakeups-on-hp-x2-10-cht-axp288-model.patch b/queue-4.19/gpiolib-acpi-add-quirk-to-ignore-ec-wakeups-on-hp-x2-10-cht-axp288-model.patch new file mode 100644 index 00000000000..61306c51984 --- /dev/null +++ b/queue-4.19/gpiolib-acpi-add-quirk-to-ignore-ec-wakeups-on-hp-x2-10-cht-axp288-model.patch @@ -0,0 +1,59 @@ +From 0c625ccfe6f754d0896b8881f5c85bcb81699f1f Mon Sep 17 00:00:00 2001 +From: Hans de Goede +Date: Mon, 2 Mar 2020 12:12:25 +0100 +Subject: gpiolib: acpi: Add quirk to ignore EC wakeups on HP x2 10 CHT + AXP288 model + +From: Hans de Goede + +commit 0c625ccfe6f754d0896b8881f5c85bcb81699f1f upstream. + +There are at least 3 models of the HP x2 10 models: + +Bay Trail SoC + AXP288 PMIC +Cherry Trail SoC + AXP288 PMIC +Cherry Trail SoC + TI PMIC + +Like on the other HP x2 10 models we need to ignore wakeup for ACPI GPIO +events on the external embedded-controller pin to avoid spurious wakeups +on the HP x2 10 CHT + AXP288 model too. + +This commit adds an extra DMI based quirk for the HP x2 10 CHT + AXP288 +model, ignoring wakeups for ACPI GPIO events on the EC interrupt pin +on this model. This fixes spurious wakeups from suspend on this model. + +Fixes: aa23ca3d98f7 ("gpiolib: acpi: Add honor_wakeup module-option + quirk mechanism") +Reported-and-tested-by: Marc Lehmann +Signed-off-by: Hans de Goede +Link: https://lore.kernel.org/r/20200302111225.6641-4-hdegoede@redhat.com +Acked-by: Mika Westerberg +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpio/gpiolib-acpi.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/drivers/gpio/gpiolib-acpi.c ++++ b/drivers/gpio/gpiolib-acpi.c +@@ -1391,6 +1391,21 @@ static const struct dmi_system_id gpioli + .ignore_wake = "INT33FC:02@28", + }, + }, ++ { ++ /* ++ * HP X2 10 models with Cherry Trail SoC + AXP288 PMIC use an ++ * external embedded-controller connected via I2C + an ACPI GPIO ++ * event handler on INT33FF:01 pin 0, causing spurious wakeups. ++ */ ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "HP"), ++ DMI_MATCH(DMI_PRODUCT_NAME, "HP Pavilion x2 Detachable"), ++ DMI_MATCH(DMI_BOARD_NAME, "813E"), ++ }, ++ .driver_data = &(struct acpi_gpiolib_dmi_quirk) { ++ .ignore_wake = "INT33FF:01@0", ++ }, ++ }, + {} /* Terminating entry */ + }; + diff --git a/queue-4.19/net-ks8851-ml-fix-io-operations-again.patch b/queue-4.19/net-ks8851-ml-fix-io-operations-again.patch new file mode 100644 index 00000000000..d5cb198896b --- /dev/null +++ b/queue-4.19/net-ks8851-ml-fix-io-operations-again.patch @@ -0,0 +1,137 @@ +From 8262e6f9b1034ede34548a04dec4c302d92c9497 Mon Sep 17 00:00:00 2001 +From: Marek Vasut +Date: Wed, 25 Mar 2020 15:25:47 +0100 +Subject: net: ks8851-ml: Fix IO operations, again + +From: Marek Vasut + +commit 8262e6f9b1034ede34548a04dec4c302d92c9497 upstream. + +This patch reverts 58292104832f ("net: ks8851-ml: Fix 16-bit IO operation") +and edacb098ea9c ("net: ks8851-ml: Fix 16-bit data access"), because it +turns out these were only necessary due to buggy hardware. This patch adds +a check for such a buggy hardware to prevent any such mistakes again. + +While working further on the KS8851 driver, it came to light that the +KS8851-16MLL is capable of switching bus endianness by a hardware strap, +EESK pin. If this strap is incorrect, the IO accesses require such endian +swapping as is being reverted by this patch. Such swapping also impacts +the performance significantly. + +Hence, in addition to removing it, detect that the hardware is broken, +report to user, and fail to bind with such hardware. + +Fixes: 58292104832f ("net: ks8851-ml: Fix 16-bit IO operation") +Fixes: edacb098ea9c ("net: ks8851-ml: Fix 16-bit data access") +Signed-off-by: Marek Vasut +Cc: David S. Miller +Cc: Lukas Wunner +Cc: Petr Stetiar +Cc: YueHaibing +Signed-off-by: David S. Miller +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/net/ethernet/micrel/ks8851_mll.c | 56 ++++++++++++++++++++++++++++--- + 1 file changed, 52 insertions(+), 4 deletions(-) + +--- a/drivers/net/ethernet/micrel/ks8851_mll.c ++++ b/drivers/net/ethernet/micrel/ks8851_mll.c +@@ -476,6 +476,50 @@ static int msg_enable; + */ + + /** ++ * ks_check_endian - Check whether endianness of the bus is correct ++ * @ks : The chip information ++ * ++ * The KS8851-16MLL EESK pin allows selecting the endianness of the 16bit ++ * bus. To maintain optimum performance, the bus endianness should be set ++ * such that it matches the endianness of the CPU. ++ */ ++ ++static int ks_check_endian(struct ks_net *ks) ++{ ++ u16 cider; ++ ++ /* ++ * Read CIDER register first, however read it the "wrong" way around. ++ * If the endian strap on the KS8851-16MLL in incorrect and the chip ++ * is operating in different endianness than the CPU, then the meaning ++ * of BE[3:0] byte-enable bits is also swapped such that: ++ * BE[3,2,1,0] becomes BE[1,0,3,2] ++ * ++ * Luckily for us, the byte-enable bits are the top four MSbits of ++ * the address register and the CIDER register is at offset 0xc0. ++ * Hence, by reading address 0xc0c0, which is not impacted by endian ++ * swapping, we assert either BE[3:2] or BE[1:0] while reading the ++ * CIDER register. ++ * ++ * If the bus configuration is correct, reading 0xc0c0 asserts ++ * BE[3:2] and this read returns 0x0000, because to read register ++ * with bottom two LSbits of address set to 0, BE[1:0] must be ++ * asserted. ++ * ++ * If the bus configuration is NOT correct, reading 0xc0c0 asserts ++ * BE[1:0] and this read returns non-zero 0x8872 value. ++ */ ++ iowrite16(BE3 | BE2 | KS_CIDER, ks->hw_addr_cmd); ++ cider = ioread16(ks->hw_addr); ++ if (!cider) ++ return 0; ++ ++ netdev_err(ks->netdev, "incorrect EESK endian strap setting\n"); ++ ++ return -EINVAL; ++} ++ ++/** + * ks_rdreg16 - read 16 bit register from device + * @ks : The chip information + * @offset: The register address +@@ -485,7 +529,7 @@ static int msg_enable; + + static u16 ks_rdreg16(struct ks_net *ks, int offset) + { +- ks->cmd_reg_cache = (u16)offset | ((BE3 | BE2) >> (offset & 0x02)); ++ ks->cmd_reg_cache = (u16)offset | ((BE1 | BE0) << (offset & 0x02)); + iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd); + return ioread16(ks->hw_addr); + } +@@ -500,7 +544,7 @@ static u16 ks_rdreg16(struct ks_net *ks, + + static void ks_wrreg16(struct ks_net *ks, int offset, u16 value) + { +- ks->cmd_reg_cache = (u16)offset | ((BE3 | BE2) >> (offset & 0x02)); ++ ks->cmd_reg_cache = (u16)offset | ((BE1 | BE0) << (offset & 0x02)); + iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd); + iowrite16(value, ks->hw_addr); + } +@@ -516,7 +560,7 @@ static inline void ks_inblk(struct ks_ne + { + len >>= 1; + while (len--) +- *wptr++ = be16_to_cpu(ioread16(ks->hw_addr)); ++ *wptr++ = (u16)ioread16(ks->hw_addr); + } + + /** +@@ -530,7 +574,7 @@ static inline void ks_outblk(struct ks_n + { + len >>= 1; + while (len--) +- iowrite16(cpu_to_be16(*wptr++), ks->hw_addr); ++ iowrite16(*wptr++, ks->hw_addr); + } + + static void ks_disable_int(struct ks_net *ks) +@@ -1540,6 +1584,10 @@ static int ks8851_probe(struct platform_ + goto err_free; + } + ++ err = ks_check_endian(ks); ++ if (err) ++ goto err_free; ++ + netdev->irq = platform_get_irq(pdev, 0); + + if ((int)netdev->irq < 0) { diff --git a/queue-4.19/perf-map-fix-off-by-one-in-strncpy-size-argument.patch b/queue-4.19/perf-map-fix-off-by-one-in-strncpy-size-argument.patch new file mode 100644 index 00000000000..bd4dbf860da --- /dev/null +++ b/queue-4.19/perf-map-fix-off-by-one-in-strncpy-size-argument.patch @@ -0,0 +1,55 @@ +From db2c549407d4a76563c579e4768f7d6d32afefba Mon Sep 17 00:00:00 2001 +From: disconnect3d +Date: Mon, 9 Mar 2020 11:48:53 +0100 +Subject: perf map: Fix off by one in strncpy() size argument + +From: disconnect3d + +commit db2c549407d4a76563c579e4768f7d6d32afefba upstream. + +This patch fixes an off-by-one error in strncpy size argument in +tools/perf/util/map.c. The issue is that in: + + strncmp(filename, "/system/lib/", 11) + +the passed string literal: "/system/lib/" has 12 bytes (without the NULL +byte) and the passed size argument is 11. As a result, the logic won't +match the ending "/" byte and will pass filepaths that are stored in +other directories e.g. "/system/libmalicious/bin" or just +"/system/libmalicious". + +This functionality seems to be present only on Android. I assume the +/system/ directory is only writable by the root user, so I don't think +this bug has much (or any) security impact. + +Fixes: eca818369996 ("perf tools: Add automatic remapping of Android libraries") +Signed-off-by: disconnect3d +Cc: Alexander Shishkin +Cc: Changbin Du +Cc: Jiri Olsa +Cc: John Keeping +Cc: Mark Rutland +Cc: Michael Lentine +Cc: Namhyung Kim +Cc: Peter Zijlstra +Cc: Song Liu +Cc: Stephane Eranian +Link: http://lore.kernel.org/lkml/20200309104855.3775-1-dominik.b.czarnota@gmail.com +Signed-off-by: Arnaldo Carvalho de Melo +Signed-off-by: Greg Kroah-Hartman + +--- + tools/perf/util/map.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/tools/perf/util/map.c ++++ b/tools/perf/util/map.c +@@ -85,7 +85,7 @@ static inline bool replace_android_lib(c + return true; + } + +- if (!strncmp(filename, "/system/lib/", 11)) { ++ if (!strncmp(filename, "/system/lib/", 12)) { + char *ndk, *app; + const char *arch; + size_t ndk_length; diff --git a/queue-4.19/series b/queue-4.19/series index 95f20a96c92..665afd0c23b 100644 --- a/queue-4.19/series +++ b/queue-4.19/series @@ -104,3 +104,13 @@ vt-vt_ioctl-fix-use-after-free-in-vt_in_use.patch platform-x86-pmc_atom-add-lex-2i385sw-to-critclk_systems-dmi-table.patch bpf-explicitly-memset-the-bpf_attr-structure.patch bpf-explicitly-memset-some-bpf-info-structures-declared-on-the-stack.patch +gpiolib-acpi-add-quirk-to-ignore-ec-wakeups-on-hp-x2-10-cht-axp288-model.patch +net-ks8851-ml-fix-io-operations-again.patch +arm64-alternative-fix-build-with-clang-integrated-assembler.patch +perf-map-fix-off-by-one-in-strncpy-size-argument.patch +arm-dts-oxnas-fix-clear-mask-property.patch +arm-bcm2835-rpi-zero-w-add-missing-pinctrl-name.patch +arm-dts-imx6-phycore-som-fix-arm-and-soc-minimum-voltage.patch +arm-dts-n900-fix-onenand-timings.patch +arm64-dts-ls1043a-rdb-correct-rgmii-delay-mode-to-rgmii-id.patch +arm64-dts-ls1046ardb-set-rgmii-interfaces-to-rgmii_id-mode.patch