From: Sasha Levin Date: Tue, 1 Aug 2023 01:06:58 +0000 (-0400) Subject: Fixes for 4.14 X-Git-Tag: v5.15.124~51 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=3ece514a68712f77fca6f04ff08771eec1924072;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 4.14 Signed-off-by: Sasha Levin --- diff --git a/queue-4.14/irq-bcm6345-l1-do-not-assume-a-fixed-block-to-cpu-ma.patch b/queue-4.14/irq-bcm6345-l1-do-not-assume-a-fixed-block-to-cpu-ma.patch new file mode 100644 index 00000000000..4b8be23b9fb --- /dev/null +++ b/queue-4.14/irq-bcm6345-l1-do-not-assume-a-fixed-block-to-cpu-ma.patch @@ -0,0 +1,91 @@ +From 1f89449121f2039b2c79ffeb9002cbb4ae1efa07 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 29 Jun 2023 09:26:20 +0200 +Subject: irq-bcm6345-l1: Do not assume a fixed block to cpu mapping +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Jonas Gorski + +[ Upstream commit 55ad24857341c36616ecc1d9580af5626c226cf1 ] + +The irq to block mapping is fixed, and interrupts from the first block +will always be routed to the first parent IRQ. But the parent interrupts +themselves can be routed to any available CPU. + +This is used by the bootloader to map the first parent interrupt to the +boot CPU, regardless wether the boot CPU is the first one or the second +one. + +When booting from the second CPU, the assumption that the first block's +IRQ is mapped to the first CPU breaks, and the system hangs because +interrupts do not get routed correctly. + +Fix this by passing the appropriate bcm6434_l1_cpu to the interrupt +handler instead of the chip itself, so the handler always has the right +block. + +Fixes: c7c42ec2baa1 ("irqchips/bmips: Add bcm6345-l1 interrupt controller") +Signed-off-by: Jonas Gorski +Reviewed-by: Philippe Mathieu-Daudé +Reviewed-by: Florian Fainelli +Signed-off-by: Marc Zyngier +Link: https://lore.kernel.org/r/20230629072620.62527-1-jonas.gorski@gmail.com +Signed-off-by: Sasha Levin +--- + drivers/irqchip/irq-bcm6345-l1.c | 14 +++++--------- + 1 file changed, 5 insertions(+), 9 deletions(-) + +diff --git a/drivers/irqchip/irq-bcm6345-l1.c b/drivers/irqchip/irq-bcm6345-l1.c +index 31ea6332ecb83..60dc64b4ac6d2 100644 +--- a/drivers/irqchip/irq-bcm6345-l1.c ++++ b/drivers/irqchip/irq-bcm6345-l1.c +@@ -85,6 +85,7 @@ struct bcm6345_l1_chip { + }; + + struct bcm6345_l1_cpu { ++ struct bcm6345_l1_chip *intc; + void __iomem *map_base; + unsigned int parent_irq; + u32 enable_cache[]; +@@ -118,17 +119,11 @@ static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc, + + static void bcm6345_l1_irq_handle(struct irq_desc *desc) + { +- struct bcm6345_l1_chip *intc = irq_desc_get_handler_data(desc); +- struct bcm6345_l1_cpu *cpu; ++ struct bcm6345_l1_cpu *cpu = irq_desc_get_handler_data(desc); ++ struct bcm6345_l1_chip *intc = cpu->intc; + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned int idx; + +-#ifdef CONFIG_SMP +- cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; +-#else +- cpu = intc->cpus[0]; +-#endif +- + chained_irq_enter(chip, desc); + + for (idx = 0; idx < intc->n_words; idx++) { +@@ -260,6 +255,7 @@ static int __init bcm6345_l1_init_one(struct device_node *dn, + if (!cpu) + return -ENOMEM; + ++ cpu->intc = intc; + cpu->map_base = ioremap(res.start, sz); + if (!cpu->map_base) + return -ENOMEM; +@@ -275,7 +271,7 @@ static int __init bcm6345_l1_init_one(struct device_node *dn, + return -EINVAL; + } + irq_set_chained_handler_and_data(cpu->parent_irq, +- bcm6345_l1_irq_handle, intc); ++ bcm6345_l1_irq_handle, cpu); + + return 0; + } +-- +2.40.1 + diff --git a/queue-4.14/series b/queue-4.14/series index 7db131a6d4f..cd5890e4ce4 100644 --- a/queue-4.14/series +++ b/queue-4.14/series @@ -170,3 +170,4 @@ documentation-security-bugs.rst-update-preferences-when-dealing-with-the-linux-d staging-ks7010-potential-buffer-overflow-in-ks_wlan_set_encode_ext.patch hwmon-nct7802-fix-for-temp6-peci1-processed-even-if-peci1-disabled.patch tpm_tis-explicitly-check-for-error-code.patch +irq-bcm6345-l1-do-not-assume-a-fixed-block-to-cpu-ma.patch