From: Greg Kroah-Hartman Date: Mon, 11 Dec 2023 12:57:10 +0000 (+0100) Subject: 5.15-stable patches X-Git-Tag: v4.14.333~38 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=3ee1060094282b2fb49ab162d3a7ee2d95b14033;p=thirdparty%2Fkernel%2Fstable-queue.git 5.15-stable patches added patches: arm-pl011-fix-dma-support.patch kvm-s390-mm-properly-reset-no-dat.patch kvm-svm-update-efer-software-model-on-cr0-trap-for-sev-es.patch mips-loongson64-enable-dma-noncoherent-support.patch mips-loongson64-reserve-vgabios-memory-on-boot.patch parport-add-support-for-brainboxes-ix-uc-px-parallel-cards.patch revert-xhci-loosen-rpm-as-default-policy-to-cover-for-amd-xhc-1.1.patch serial-8250-8250_omap-clear-uart_has_rhr_it_dis-bit.patch serial-8250-8250_omap-do-not-start-rx-dma-on-thri-interrupt.patch serial-8250_omap-add-earlycon-support-for-the-am654-uart-controller.patch serial-sc16is7xx-address-rx-timeout-interrupt-errata.patch usb-gadget-f_hid-fix-report-descriptor-allocation.patch usb-typec-class-fix-typec_altmode_put_partner-to-put-plugs.patch x86-cpu-amd-check-vendor-in-the-amd-microcode-callback.patch --- diff --git a/queue-5.15/arm-pl011-fix-dma-support.patch b/queue-5.15/arm-pl011-fix-dma-support.patch new file mode 100644 index 00000000000..917ad548c1a --- /dev/null +++ b/queue-5.15/arm-pl011-fix-dma-support.patch @@ -0,0 +1,335 @@ +From 58ac1b3799799069d53f5bf95c093f2fe8dd3cc5 Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Wed, 22 Nov 2023 18:15:03 +0100 +Subject: ARM: PL011: Fix DMA support + +From: Arnd Bergmann + +commit 58ac1b3799799069d53f5bf95c093f2fe8dd3cc5 upstream. + +Since there is no guarantee that the memory returned by +dma_alloc_coherent() is associated with a 'struct page', using the +architecture specific phys_to_page() is wrong, but using +virt_to_page() would be as well. + +Stop using sg lists altogether and just use the *_single() functions +instead. This also simplifies the code a bit since the scatterlists in +this driver always have only one entry anyway. + +https://lore.kernel.org/lkml/86db0fe5-930d-4cbb-bd7d-03367da38951@app.fastmail.com/ + Use consistent names for dma buffers + +gc: Add a commit log from the initial thread: +https://lore.kernel.org/lkml/86db0fe5-930d-4cbb-bd7d-03367da38951@app.fastmail.com/ + Use consistent names for dma buffers + +Fixes: cb06ff102e2d7 ("ARM: PL011: Add support for Rx DMA buffer polling.") +Signed-off-by: Arnd Bergmann +Tested-by: Gregory CLEMENT +Signed-off-by: Gregory CLEMENT +Cc: stable +Link: https://lore.kernel.org/r/20231122171503.235649-1-gregory.clement@bootlin.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/tty/serial/amba-pl011.c | 112 +++++++++++++++++++--------------------- + 1 file changed, 54 insertions(+), 58 deletions(-) + +--- a/drivers/tty/serial/amba-pl011.c ++++ b/drivers/tty/serial/amba-pl011.c +@@ -222,17 +222,18 @@ static struct vendor_data vendor_zte = { + + /* Deals with DMA transactions */ + +-struct pl011_sgbuf { +- struct scatterlist sg; +- char *buf; ++struct pl011_dmabuf { ++ dma_addr_t dma; ++ size_t len; ++ char *buf; + }; + + struct pl011_dmarx_data { + struct dma_chan *chan; + struct completion complete; + bool use_buf_b; +- struct pl011_sgbuf sgbuf_a; +- struct pl011_sgbuf sgbuf_b; ++ struct pl011_dmabuf dbuf_a; ++ struct pl011_dmabuf dbuf_b; + dma_cookie_t cookie; + bool running; + struct timer_list timer; +@@ -245,7 +246,8 @@ struct pl011_dmarx_data { + + struct pl011_dmatx_data { + struct dma_chan *chan; +- struct scatterlist sg; ++ dma_addr_t dma; ++ size_t len; + char *buf; + bool queued; + }; +@@ -370,32 +372,24 @@ static int pl011_fifo_to_tty(struct uart + + #define PL011_DMA_BUFFER_SIZE PAGE_SIZE + +-static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, ++static int pl011_dmabuf_init(struct dma_chan *chan, struct pl011_dmabuf *db, + enum dma_data_direction dir) + { +- dma_addr_t dma_addr; +- +- sg->buf = dma_alloc_coherent(chan->device->dev, +- PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL); +- if (!sg->buf) ++ db->buf = dma_alloc_coherent(chan->device->dev, PL011_DMA_BUFFER_SIZE, ++ &db->dma, GFP_KERNEL); ++ if (!db->buf) + return -ENOMEM; +- +- sg_init_table(&sg->sg, 1); +- sg_set_page(&sg->sg, phys_to_page(dma_addr), +- PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr)); +- sg_dma_address(&sg->sg) = dma_addr; +- sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE; ++ db->len = PL011_DMA_BUFFER_SIZE; + + return 0; + } + +-static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, ++static void pl011_dmabuf_free(struct dma_chan *chan, struct pl011_dmabuf *db, + enum dma_data_direction dir) + { +- if (sg->buf) { ++ if (db->buf) { + dma_free_coherent(chan->device->dev, +- PL011_DMA_BUFFER_SIZE, sg->buf, +- sg_dma_address(&sg->sg)); ++ PL011_DMA_BUFFER_SIZE, db->buf, db->dma); + } + } + +@@ -556,8 +550,8 @@ static void pl011_dma_tx_callback(void * + + spin_lock_irqsave(&uap->port.lock, flags); + if (uap->dmatx.queued) +- dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, +- DMA_TO_DEVICE); ++ dma_unmap_single(dmatx->chan->device->dev, dmatx->dma, ++ dmatx->len, DMA_TO_DEVICE); + + dmacr = uap->dmacr; + uap->dmacr = dmacr & ~UART011_TXDMAE; +@@ -643,18 +637,19 @@ static int pl011_dma_tx_refill(struct ua + memcpy(&dmatx->buf[first], &xmit->buf[0], second); + } + +- dmatx->sg.length = count; +- +- if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { ++ dmatx->len = count; ++ dmatx->dma = dma_map_single(dma_dev->dev, dmatx->buf, count, ++ DMA_TO_DEVICE); ++ if (dmatx->dma == DMA_MAPPING_ERROR) { + uap->dmatx.queued = false; + dev_dbg(uap->port.dev, "unable to map TX DMA\n"); + return -EBUSY; + } + +- desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, ++ desc = dmaengine_prep_slave_single(chan, dmatx->dma, dmatx->len, DMA_MEM_TO_DEV, + DMA_PREP_INTERRUPT | DMA_CTRL_ACK); + if (!desc) { +- dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); ++ dma_unmap_single(dma_dev->dev, dmatx->dma, dmatx->len, DMA_TO_DEVICE); + uap->dmatx.queued = false; + /* + * If DMA cannot be used right now, we complete this +@@ -818,8 +813,8 @@ __acquires(&uap->port.lock) + dmaengine_terminate_async(uap->dmatx.chan); + + if (uap->dmatx.queued) { +- dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, +- DMA_TO_DEVICE); ++ dma_unmap_single(uap->dmatx.chan->device->dev, uap->dmatx.dma, ++ uap->dmatx.len, DMA_TO_DEVICE); + uap->dmatx.queued = false; + uap->dmacr &= ~UART011_TXDMAE; + pl011_write(uap->dmacr, uap, REG_DMACR); +@@ -833,15 +828,15 @@ static int pl011_dma_rx_trigger_dma(stru + struct dma_chan *rxchan = uap->dmarx.chan; + struct pl011_dmarx_data *dmarx = &uap->dmarx; + struct dma_async_tx_descriptor *desc; +- struct pl011_sgbuf *sgbuf; ++ struct pl011_dmabuf *dbuf; + + if (!rxchan) + return -EIO; + + /* Start the RX DMA job */ +- sgbuf = uap->dmarx.use_buf_b ? +- &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; +- desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1, ++ dbuf = uap->dmarx.use_buf_b ? ++ &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; ++ desc = dmaengine_prep_slave_single(rxchan, dbuf->dma, dbuf->len, + DMA_DEV_TO_MEM, + DMA_PREP_INTERRUPT | DMA_CTRL_ACK); + /* +@@ -881,8 +876,8 @@ static void pl011_dma_rx_chars(struct ua + bool readfifo) + { + struct tty_port *port = &uap->port.state->port; +- struct pl011_sgbuf *sgbuf = use_buf_b ? +- &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; ++ struct pl011_dmabuf *dbuf = use_buf_b ? ++ &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; + int dma_count = 0; + u32 fifotaken = 0; /* only used for vdbg() */ + +@@ -891,7 +886,7 @@ static void pl011_dma_rx_chars(struct ua + + if (uap->dmarx.poll_rate) { + /* The data can be taken by polling */ +- dmataken = sgbuf->sg.length - dmarx->last_residue; ++ dmataken = dbuf->len - dmarx->last_residue; + /* Recalculate the pending size */ + if (pending >= dmataken) + pending -= dmataken; +@@ -905,7 +900,7 @@ static void pl011_dma_rx_chars(struct ua + * Note that tty_insert_flip_buf() tries to take as many chars + * as it can. + */ +- dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, ++ dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken, + pending); + + uap->port.icount.rx += dma_count; +@@ -916,7 +911,7 @@ static void pl011_dma_rx_chars(struct ua + + /* Reset the last_residue for Rx DMA poll */ + if (uap->dmarx.poll_rate) +- dmarx->last_residue = sgbuf->sg.length; ++ dmarx->last_residue = dbuf->len; + + /* + * Only continue with trying to read the FIFO if all DMA chars have +@@ -951,8 +946,8 @@ static void pl011_dma_rx_irq(struct uart + { + struct pl011_dmarx_data *dmarx = &uap->dmarx; + struct dma_chan *rxchan = dmarx->chan; +- struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? +- &dmarx->sgbuf_b : &dmarx->sgbuf_a; ++ struct pl011_dmabuf *dbuf = dmarx->use_buf_b ? ++ &dmarx->dbuf_b : &dmarx->dbuf_a; + size_t pending; + struct dma_tx_state state; + enum dma_status dmastat; +@@ -974,7 +969,7 @@ static void pl011_dma_rx_irq(struct uart + pl011_write(uap->dmacr, uap, REG_DMACR); + uap->dmarx.running = false; + +- pending = sgbuf->sg.length - state.residue; ++ pending = dbuf->len - state.residue; + BUG_ON(pending > PL011_DMA_BUFFER_SIZE); + /* Then we terminate the transfer - we now know our residue */ + dmaengine_terminate_all(rxchan); +@@ -1001,8 +996,8 @@ static void pl011_dma_rx_callback(void * + struct pl011_dmarx_data *dmarx = &uap->dmarx; + struct dma_chan *rxchan = dmarx->chan; + bool lastbuf = dmarx->use_buf_b; +- struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? +- &dmarx->sgbuf_b : &dmarx->sgbuf_a; ++ struct pl011_dmabuf *dbuf = dmarx->use_buf_b ? ++ &dmarx->dbuf_b : &dmarx->dbuf_a; + size_t pending; + struct dma_tx_state state; + int ret; +@@ -1020,7 +1015,7 @@ static void pl011_dma_rx_callback(void * + * the DMA irq handler. So we check the residue here. + */ + rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); +- pending = sgbuf->sg.length - state.residue; ++ pending = dbuf->len - state.residue; + BUG_ON(pending > PL011_DMA_BUFFER_SIZE); + /* Then we terminate the transfer - we now know our residue */ + dmaengine_terminate_all(rxchan); +@@ -1072,16 +1067,16 @@ static void pl011_dma_rx_poll(struct tim + unsigned long flags; + unsigned int dmataken = 0; + unsigned int size = 0; +- struct pl011_sgbuf *sgbuf; ++ struct pl011_dmabuf *dbuf; + int dma_count; + struct dma_tx_state state; + +- sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; ++ dbuf = dmarx->use_buf_b ? &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; + rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); + if (likely(state.residue < dmarx->last_residue)) { +- dmataken = sgbuf->sg.length - dmarx->last_residue; ++ dmataken = dbuf->len - dmarx->last_residue; + size = dmarx->last_residue - state.residue; +- dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, ++ dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken, + size); + if (dma_count == size) + dmarx->last_residue = state.residue; +@@ -1128,7 +1123,7 @@ static void pl011_dma_startup(struct uar + return; + } + +- sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); ++ uap->dmatx.len = PL011_DMA_BUFFER_SIZE; + + /* The DMA buffer is now the FIFO the TTY subsystem can use */ + uap->port.fifosize = PL011_DMA_BUFFER_SIZE; +@@ -1138,7 +1133,7 @@ static void pl011_dma_startup(struct uar + goto skip_rx; + + /* Allocate and map DMA RX buffers */ +- ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, ++ ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_a, + DMA_FROM_DEVICE); + if (ret) { + dev_err(uap->port.dev, "failed to init DMA %s: %d\n", +@@ -1146,12 +1141,12 @@ static void pl011_dma_startup(struct uar + goto skip_rx; + } + +- ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, ++ ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_b, + DMA_FROM_DEVICE); + if (ret) { + dev_err(uap->port.dev, "failed to init DMA %s: %d\n", + "RX buffer B", ret); +- pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, ++ pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, + DMA_FROM_DEVICE); + goto skip_rx; + } +@@ -1205,8 +1200,9 @@ static void pl011_dma_shutdown(struct ua + /* In theory, this should already be done by pl011_dma_flush_buffer */ + dmaengine_terminate_all(uap->dmatx.chan); + if (uap->dmatx.queued) { +- dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, +- DMA_TO_DEVICE); ++ dma_unmap_single(uap->dmatx.chan->device->dev, ++ uap->dmatx.dma, uap->dmatx.len, ++ DMA_TO_DEVICE); + uap->dmatx.queued = false; + } + +@@ -1217,8 +1213,8 @@ static void pl011_dma_shutdown(struct ua + if (uap->using_rx_dma) { + dmaengine_terminate_all(uap->dmarx.chan); + /* Clean up the RX DMA */ +- pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); +- pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); ++ pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, DMA_FROM_DEVICE); ++ pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_b, DMA_FROM_DEVICE); + if (uap->dmarx.poll_rate) + del_timer_sync(&uap->dmarx.timer); + uap->using_rx_dma = false; diff --git a/queue-5.15/kvm-s390-mm-properly-reset-no-dat.patch b/queue-5.15/kvm-s390-mm-properly-reset-no-dat.patch new file mode 100644 index 00000000000..79b938456a3 --- /dev/null +++ b/queue-5.15/kvm-s390-mm-properly-reset-no-dat.patch @@ -0,0 +1,33 @@ +From 27072b8e18a73ffeffb1c140939023915a35134b Mon Sep 17 00:00:00 2001 +From: Claudio Imbrenda +Date: Thu, 9 Nov 2023 13:36:24 +0100 +Subject: KVM: s390/mm: Properly reset no-dat + +From: Claudio Imbrenda + +commit 27072b8e18a73ffeffb1c140939023915a35134b upstream. + +When the CMMA state needs to be reset, the no-dat bit also needs to be +reset. Failure to do so could cause issues in the guest, since the +guest expects the bit to be cleared after a reset. + +Cc: +Reviewed-by: Nico Boehr +Message-ID: <20231109123624.37314-1-imbrenda@linux.ibm.com> +Signed-off-by: Claudio Imbrenda +Signed-off-by: Greg Kroah-Hartman +--- + arch/s390/mm/pgtable.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/s390/mm/pgtable.c ++++ b/arch/s390/mm/pgtable.c +@@ -731,7 +731,7 @@ void ptep_zap_unused(struct mm_struct *m + pte_clear(mm, addr, ptep); + } + if (reset) +- pgste_val(pgste) &= ~_PGSTE_GPS_USAGE_MASK; ++ pgste_val(pgste) &= ~(_PGSTE_GPS_USAGE_MASK | _PGSTE_GPS_NODAT); + pgste_set_unlock(ptep, pgste); + preempt_enable(); + } diff --git a/queue-5.15/kvm-svm-update-efer-software-model-on-cr0-trap-for-sev-es.patch b/queue-5.15/kvm-svm-update-efer-software-model-on-cr0-trap-for-sev-es.patch new file mode 100644 index 00000000000..ddecf0e7965 --- /dev/null +++ b/queue-5.15/kvm-svm-update-efer-software-model-on-cr0-trap-for-sev-es.patch @@ -0,0 +1,74 @@ +From 4cdf351d3630a640ab6a05721ef055b9df62277f Mon Sep 17 00:00:00 2001 +From: Sean Christopherson +Date: Fri, 7 May 2021 09:59:46 -0700 +Subject: KVM: SVM: Update EFER software model on CR0 trap for SEV-ES + +From: Sean Christopherson + +commit 4cdf351d3630a640ab6a05721ef055b9df62277f upstream. + +In general, activating long mode involves setting the EFER_LME bit in +the EFER register and then enabling the X86_CR0_PG bit in the CR0 +register. At this point, the EFER_LMA bit will be set automatically by +hardware. + +In the case of SVM/SEV guests where writes to CR0 are intercepted, it's +necessary for the host to set EFER_LMA on behalf of the guest since +hardware does not see the actual CR0 write. + +In the case of SEV-ES guests where writes to CR0 are trapped instead of +intercepted, the hardware *does* see/record the write to CR0 before +exiting and passing the value on to the host, so as part of enabling +SEV-ES support commit f1c6366e3043 ("KVM: SVM: Add required changes to +support intercepts under SEV-ES") dropped special handling of the +EFER_LMA bit with the understanding that it would be set automatically. + +However, since the guest never explicitly sets the EFER_LMA bit, the +host never becomes aware that it has been set. This becomes problematic +when userspace tries to get/set the EFER values via +KVM_GET_SREGS/KVM_SET_SREGS, since the EFER contents tracked by the host +will be missing the EFER_LMA bit, and when userspace attempts to pass +the EFER value back via KVM_SET_SREGS it will fail a sanity check that +asserts that EFER_LMA should always be set when X86_CR0_PG and EFER_LME +are set. + +Fix this by always inferring the value of EFER_LMA based on X86_CR0_PG +and EFER_LME, regardless of whether or not SEV-ES is enabled. + +Fixes: f1c6366e3043 ("KVM: SVM: Add required changes to support intercepts under SEV-ES") +Reported-by: Peter Gonda +Cc: stable@vger.kernel.org +Signed-off-by: Sean Christopherson +Message-Id: <20210507165947.2502412-2-seanjc@google.com> +[A two year old patch that was revived after we noticed the failure in + KVM_SET_SREGS and a similar patch was posted by Michael Roth. This is + Sean's patch, but with Michael's more complete commit message. - Paolo] +Signed-off-by: Paolo Bonzini +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/kvm/svm/svm.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +--- a/arch/x86/kvm/svm/svm.c ++++ b/arch/x86/kvm/svm/svm.c +@@ -1750,15 +1750,17 @@ void svm_set_cr0(struct kvm_vcpu *vcpu, + bool old_paging = is_paging(vcpu); + + #ifdef CONFIG_X86_64 +- if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) { ++ if (vcpu->arch.efer & EFER_LME) { + if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { + vcpu->arch.efer |= EFER_LMA; +- svm->vmcb->save.efer |= EFER_LMA | EFER_LME; ++ if (!vcpu->arch.guest_state_protected) ++ svm->vmcb->save.efer |= EFER_LMA | EFER_LME; + } + + if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { + vcpu->arch.efer &= ~EFER_LMA; +- svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); ++ if (!vcpu->arch.guest_state_protected) ++ svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); + } + } + #endif diff --git a/queue-5.15/mips-loongson64-enable-dma-noncoherent-support.patch b/queue-5.15/mips-loongson64-enable-dma-noncoherent-support.patch new file mode 100644 index 00000000000..648406d10c5 --- /dev/null +++ b/queue-5.15/mips-loongson64-enable-dma-noncoherent-support.patch @@ -0,0 +1,87 @@ +From edc0378eee00200a5bedf1bb9f00ad390e0d1bd4 Mon Sep 17 00:00:00 2001 +From: Jiaxun Yang +Date: Tue, 7 Nov 2023 11:15:19 +0000 +Subject: MIPS: Loongson64: Enable DMA noncoherent support + +From: Jiaxun Yang + +commit edc0378eee00200a5bedf1bb9f00ad390e0d1bd4 upstream. + +There are some Loongson64 systems come with broken coherent DMA +support, firmware will set a bit in boot_param and pass nocoherentio +in cmdline. + +However nonconherent support was missed out when spin off Loongson-2EF +form Loongson64, and that boot_param change never made itself into +upstream. + +Support DMA noncoherent properly to get those systems working. + +Cc: stable@vger.kernel.org +Fixes: 71e2f4dd5a65 ("MIPS: Fork loongson2ef from loongson64") +Signed-off-by: Jiaxun Yang +Signed-off-by: Thomas Bogendoerfer +Signed-off-by: Greg Kroah-Hartman +--- + arch/mips/Kconfig | 2 ++ + arch/mips/include/asm/mach-loongson64/boot_param.h | 3 ++- + arch/mips/loongson64/env.c | 10 +++++++++- + 3 files changed, 13 insertions(+), 2 deletions(-) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -480,6 +480,7 @@ config MACH_LOONGSON2EF + + config MACH_LOONGSON64 + bool "Loongson 64-bit family of machines" ++ select ARCH_DMA_DEFAULT_COHERENT + select ARCH_SPARSEMEM_ENABLE + select ARCH_MIGHT_HAVE_PC_PARPORT + select ARCH_MIGHT_HAVE_PC_SERIO +@@ -1379,6 +1380,7 @@ config CPU_LOONGSON64 + select CPU_SUPPORTS_MSA + select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT + select CPU_MIPSR2_IRQ_VI ++ select DMA_NONCOHERENT + select WEAK_ORDERING + select WEAK_REORDERING_BEYOND_LLSC + select MIPS_ASID_BITS_VARIABLE +--- a/arch/mips/include/asm/mach-loongson64/boot_param.h ++++ b/arch/mips/include/asm/mach-loongson64/boot_param.h +@@ -117,7 +117,8 @@ struct irq_source_routing_table { + u64 pci_io_start_addr; + u64 pci_io_end_addr; + u64 pci_config_addr; +- u32 dma_mask_bits; ++ u16 dma_mask_bits; ++ u16 dma_noncoherent; + } __packed; + + struct interface_info { +--- a/arch/mips/loongson64/env.c ++++ b/arch/mips/loongson64/env.c +@@ -13,6 +13,8 @@ + * Copyright (C) 2009 Lemote Inc. + * Author: Wu Zhangjin, wuzhangjin@gmail.com + */ ++ ++#include + #include + #include + #include +@@ -147,8 +149,14 @@ void __init prom_lefi_init_env(void) + + loongson_sysconf.dma_mask_bits = eirq_source->dma_mask_bits; + if (loongson_sysconf.dma_mask_bits < 32 || +- loongson_sysconf.dma_mask_bits > 64) ++ loongson_sysconf.dma_mask_bits > 64) { + loongson_sysconf.dma_mask_bits = 32; ++ dma_default_coherent = true; ++ } else { ++ dma_default_coherent = !eirq_source->dma_noncoherent; ++ } ++ ++ pr_info("Firmware: Coherent DMA: %s\n", dma_default_coherent ? "on" : "off"); + + loongson_sysconf.restart_addr = boot_p->reset_system.ResetWarm; + loongson_sysconf.poweroff_addr = boot_p->reset_system.Shutdown; diff --git a/queue-5.15/mips-loongson64-reserve-vgabios-memory-on-boot.patch b/queue-5.15/mips-loongson64-reserve-vgabios-memory-on-boot.patch new file mode 100644 index 00000000000..09028d01003 --- /dev/null +++ b/queue-5.15/mips-loongson64-reserve-vgabios-memory-on-boot.patch @@ -0,0 +1,43 @@ +From 8f7aa77a463f47c9e00592d02747a9fcf2271543 Mon Sep 17 00:00:00 2001 +From: Jiaxun Yang +Date: Tue, 7 Nov 2023 11:15:18 +0000 +Subject: MIPS: Loongson64: Reserve vgabios memory on boot + +From: Jiaxun Yang + +commit 8f7aa77a463f47c9e00592d02747a9fcf2271543 upstream. + +vgabios is passed from firmware to kernel on Loongson64 systems. +Sane firmware will keep this pointer in reserved memory space +passed from the firmware but insane firmware keeps it in low +memory before kernel entry that is not reserved. + +Previously kernel won't try to allocate memory from low memory +before kernel entry on boot, but after converting to memblock +it will do that. + +Fix by resversing those memory on early boot. + +Cc: stable@vger.kernel.org +Fixes: a94e4f24ec83 ("MIPS: init: Drop boot_mem_map") +Signed-off-by: Jiaxun Yang +Signed-off-by: Thomas Bogendoerfer +Signed-off-by: Greg Kroah-Hartman +--- + arch/mips/loongson64/init.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/mips/loongson64/init.c ++++ b/arch/mips/loongson64/init.c +@@ -86,6 +86,11 @@ void __init szmem(unsigned int node) + break; + } + } ++ ++ /* Reserve vgabios if it comes from firmware */ ++ if (loongson_sysconf.vgabios_addr) ++ memblock_reserve(virt_to_phys((void *)loongson_sysconf.vgabios_addr), ++ SZ_256K); + } + + #ifndef CONFIG_NUMA diff --git a/queue-5.15/parport-add-support-for-brainboxes-ix-uc-px-parallel-cards.patch b/queue-5.15/parport-add-support-for-brainboxes-ix-uc-px-parallel-cards.patch new file mode 100644 index 00000000000..31e0d5666c5 --- /dev/null +++ b/queue-5.15/parport-add-support-for-brainboxes-ix-uc-px-parallel-cards.patch @@ -0,0 +1,65 @@ +From 1a031f6edc460e9562098bdedc3918da07c30a6e Mon Sep 17 00:00:00 2001 +From: Cameron Williams +Date: Thu, 2 Nov 2023 21:10:40 +0000 +Subject: parport: Add support for Brainboxes IX/UC/PX parallel cards + +From: Cameron Williams + +commit 1a031f6edc460e9562098bdedc3918da07c30a6e upstream. + +Adds support for Intashield IX-500/IX-550, UC-146/UC-157, PX-146/PX-157, +PX-203 and PX-475 (LPT port) + +Cc: stable@vger.kernel.org +Signed-off-by: Cameron Williams +Acked-by: Sudip Mukherjee +Link: https://lore.kernel.org/r/AS4PR02MB790389C130410BD864C8DCC9C4A6A@AS4PR02MB7903.eurprd02.prod.outlook.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/parport/parport_pc.c | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +--- a/drivers/parport/parport_pc.c ++++ b/drivers/parport/parport_pc.c +@@ -2613,6 +2613,8 @@ enum parport_pc_pci_cards { + netmos_9865, + quatech_sppxp100, + wch_ch382l, ++ brainboxes_uc146, ++ brainboxes_px203, + }; + + +@@ -2676,6 +2678,8 @@ static struct parport_pc_pci { + /* netmos_9865 */ { 1, { { 0, -1 }, } }, + /* quatech_sppxp100 */ { 1, { { 0, 1 }, } }, + /* wch_ch382l */ { 1, { { 2, -1 }, } }, ++ /* brainboxes_uc146 */ { 1, { { 3, -1 }, } }, ++ /* brainboxes_px203 */ { 1, { { 0, -1 }, } }, + }; + + static const struct pci_device_id parport_pc_pci_tbl[] = { +@@ -2767,6 +2771,23 @@ static const struct pci_device_id parpor + PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 }, + /* WCH CH382L PCI-E single parallel port card */ + { 0x1c00, 0x3050, 0x1c00, 0x3050, 0, 0, wch_ch382l }, ++ /* Brainboxes IX-500/550 */ ++ { PCI_VENDOR_ID_INTASHIELD, 0x402a, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, ++ /* Brainboxes UC-146/UC-157 */ ++ { PCI_VENDOR_ID_INTASHIELD, 0x0be1, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_uc146 }, ++ { PCI_VENDOR_ID_INTASHIELD, 0x0be2, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_uc146 }, ++ /* Brainboxes PX-146/PX-257 */ ++ { PCI_VENDOR_ID_INTASHIELD, 0x401c, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, ++ /* Brainboxes PX-203 */ ++ { PCI_VENDOR_ID_INTASHIELD, 0x4007, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_px203 }, ++ /* Brainboxes PX-475 */ ++ { PCI_VENDOR_ID_INTASHIELD, 0x401f, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, + { 0, } /* terminate list */ + }; + MODULE_DEVICE_TABLE(pci, parport_pc_pci_tbl); diff --git a/queue-5.15/revert-xhci-loosen-rpm-as-default-policy-to-cover-for-amd-xhc-1.1.patch b/queue-5.15/revert-xhci-loosen-rpm-as-default-policy-to-cover-for-amd-xhc-1.1.patch new file mode 100644 index 00000000000..5fcaae72cdc --- /dev/null +++ b/queue-5.15/revert-xhci-loosen-rpm-as-default-policy-to-cover-for-amd-xhc-1.1.patch @@ -0,0 +1,44 @@ +From 24be0b3c40594a14b65141ced486ae327398faf8 Mon Sep 17 00:00:00 2001 +From: Mathias Nyman +Date: Tue, 5 Dec 2023 11:05:48 +0200 +Subject: Revert "xhci: Loosen RPM as default policy to cover for AMD xHC 1.1" + +From: Mathias Nyman + +commit 24be0b3c40594a14b65141ced486ae327398faf8 upstream. + +This reverts commit 4baf1218150985ee3ab0a27220456a1f027ea0ac. + +Enabling runtime pm as default for all AMD xHC 1.1 controllers caused +regression. An initial attempt to fix those was done in commit a5d6264b638e +("xhci: Enable RPM on controllers that support low-power states") but new +issues are still seen. + +Revert this to get those AMD xHC 1.1 systems working + +This patch went to stable an needs to be reverted from there as well. + +Fixes: 4baf12181509 ("xhci: Loosen RPM as default policy to cover for AMD xHC 1.1") +Link: https://lore.kernel.org/linux-usb/55c50bf5-bffb-454e-906e-4408c591cb63@molgen.mpg.de +Cc: Mario Limonciello +Cc: Basavaraj Natikar +Cc: stable@vger.kernel.org +Signed-off-by: Mathias Nyman +Reviewed-by: Mario Limonciello +Link: https://lore.kernel.org/r/20231205090548.1377667-1-mathias.nyman@linux.intel.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/host/xhci-pci.c | 2 -- + 1 file changed, 2 deletions(-) + +--- a/drivers/usb/host/xhci-pci.c ++++ b/drivers/usb/host/xhci-pci.c +@@ -349,8 +349,6 @@ static void xhci_pci_quirks(struct devic + /* xHC spec requires PCI devices to support D3hot and D3cold */ + if (xhci->hci_version >= 0x120) + xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; +- else if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version >= 0x110) +- xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; + + if (xhci->quirks & XHCI_RESET_ON_RESUME) + xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, diff --git a/queue-5.15/serial-8250-8250_omap-clear-uart_has_rhr_it_dis-bit.patch b/queue-5.15/serial-8250-8250_omap-clear-uart_has_rhr_it_dis-bit.patch new file mode 100644 index 00000000000..54d36325dc5 --- /dev/null +++ b/queue-5.15/serial-8250-8250_omap-clear-uart_has_rhr_it_dis-bit.patch @@ -0,0 +1,44 @@ +From 8973ab7a2441b286218f4a5c4c33680e2f139996 Mon Sep 17 00:00:00 2001 +From: Ronald Wahl +Date: Tue, 31 Oct 2023 12:09:09 +0100 +Subject: serial: 8250: 8250_omap: Clear UART_HAS_RHR_IT_DIS bit + +From: Ronald Wahl + +commit 8973ab7a2441b286218f4a5c4c33680e2f139996 upstream. + +This fixes commit 439c7183e5b9 ("serial: 8250: 8250_omap: Disable RX +interrupt after DMA enable") which unfortunately set the +UART_HAS_RHR_IT_DIS bit in the UART_OMAP_IER2 register and never +cleared it. + +Cc: stable@vger.kernel.org +Fixes: 439c7183e5b9 ("serial: 8250: 8250_omap: Disable RX interrupt after DMA enable") +Signed-off-by: Ronald Wahl +Reviewed-by: Vignesh Raghavendra +Link: https://lore.kernel.org/r/20231031110909.11695-1-rwahl@gmx.de +Signed-off-by: Greg Kroah-Hartman +--- + drivers/tty/serial/8250/8250_omap.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/tty/serial/8250/8250_omap.c ++++ b/drivers/tty/serial/8250/8250_omap.c +@@ -839,7 +839,7 @@ static void __dma_rx_do_complete(struct + if (priv->habit & UART_HAS_RHR_IT_DIS) { + reg = serial_in(p, UART_OMAP_IER2); + reg &= ~UART_OMAP_IER2_RHR_IT_DIS; +- serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS); ++ serial_out(p, UART_OMAP_IER2, reg); + } + + dmaengine_tx_status(rxchan, cookie, &state); +@@ -981,7 +981,7 @@ static int omap_8250_rx_dma(struct uart_ + if (priv->habit & UART_HAS_RHR_IT_DIS) { + reg = serial_in(p, UART_OMAP_IER2); + reg |= UART_OMAP_IER2_RHR_IT_DIS; +- serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS); ++ serial_out(p, UART_OMAP_IER2, reg); + } + + dma_async_issue_pending(dma->rxchan); diff --git a/queue-5.15/serial-8250-8250_omap-do-not-start-rx-dma-on-thri-interrupt.patch b/queue-5.15/serial-8250-8250_omap-do-not-start-rx-dma-on-thri-interrupt.patch new file mode 100644 index 00000000000..26aa23d4393 --- /dev/null +++ b/queue-5.15/serial-8250-8250_omap-do-not-start-rx-dma-on-thri-interrupt.patch @@ -0,0 +1,45 @@ +From c6bb057418876cdfdd29a6f7b8cef54539ee8811 Mon Sep 17 00:00:00 2001 +From: Ronald Wahl +Date: Wed, 1 Nov 2023 18:14:31 +0100 +Subject: serial: 8250: 8250_omap: Do not start RX DMA on THRI interrupt + +From: Ronald Wahl + +commit c6bb057418876cdfdd29a6f7b8cef54539ee8811 upstream. + +Starting RX DMA on THRI interrupt is too early because TX may not have +finished yet. + +This change is inspired by commit 90b8596ac460 ("serial: 8250: Prevent +starting up DMA Rx on THRI interrupt") and fixes DMA issues I had with +an AM62 SoC that is using the 8250 OMAP variant. + +Cc: stable@vger.kernel.org +Fixes: c26389f998a8 ("serial: 8250: 8250_omap: Add DMA support for UARTs on K3 SoCs") +Signed-off-by: Ronald Wahl +Reviewed-by: Vignesh Raghavendra +Link: https://lore.kernel.org/r/20231101171431.16495-1-rwahl@gmx.de +Signed-off-by: Greg Kroah-Hartman +--- + drivers/tty/serial/8250/8250_omap.c | 10 ++++++---- + 1 file changed, 6 insertions(+), 4 deletions(-) + +--- a/drivers/tty/serial/8250/8250_omap.c ++++ b/drivers/tty/serial/8250/8250_omap.c +@@ -1203,10 +1203,12 @@ static int omap_8250_dma_handle_irq(stru + + status = serial_port_in(port, UART_LSR); + +- if (priv->habit & UART_HAS_EFR2) +- am654_8250_handle_rx_dma(up, iir, status); +- else +- status = omap_8250_handle_rx_dma(up, iir, status); ++ if ((iir & 0x3f) != UART_IIR_THRI) { ++ if (priv->habit & UART_HAS_EFR2) ++ am654_8250_handle_rx_dma(up, iir, status); ++ else ++ status = omap_8250_handle_rx_dma(up, iir, status); ++ } + + serial8250_modem_status(up); + if (status & UART_LSR_THRE && up->dma->tx_err) { diff --git a/queue-5.15/serial-8250_omap-add-earlycon-support-for-the-am654-uart-controller.patch b/queue-5.15/serial-8250_omap-add-earlycon-support-for-the-am654-uart-controller.patch new file mode 100644 index 00000000000..ead305b0510 --- /dev/null +++ b/queue-5.15/serial-8250_omap-add-earlycon-support-for-the-am654-uart-controller.patch @@ -0,0 +1,31 @@ +From 8e42c301ce64e0dcca547626eb486877d502d336 Mon Sep 17 00:00:00 2001 +From: Ronald Wahl +Date: Tue, 31 Oct 2023 14:12:42 +0100 +Subject: serial: 8250_omap: Add earlycon support for the AM654 UART controller + +From: Ronald Wahl + +commit 8e42c301ce64e0dcca547626eb486877d502d336 upstream. + +Currently there is no support for earlycon on the AM654 UART +controller. This commit adds it. + +Signed-off-by: Ronald Wahl +Reviewed-by: Vignesh Raghavendra +Link: https://lore.kernel.org/r/20231031131242.15516-1-rwahl@gmx.de +Cc: stable +Signed-off-by: Greg Kroah-Hartman +--- + drivers/tty/serial/8250/8250_early.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/tty/serial/8250/8250_early.c ++++ b/drivers/tty/serial/8250/8250_early.c +@@ -199,6 +199,7 @@ static int __init early_omap8250_setup(s + OF_EARLYCON_DECLARE(omap8250, "ti,omap2-uart", early_omap8250_setup); + OF_EARLYCON_DECLARE(omap8250, "ti,omap3-uart", early_omap8250_setup); + OF_EARLYCON_DECLARE(omap8250, "ti,omap4-uart", early_omap8250_setup); ++OF_EARLYCON_DECLARE(omap8250, "ti,am654-uart", early_omap8250_setup); + + #endif + diff --git a/queue-5.15/serial-sc16is7xx-address-rx-timeout-interrupt-errata.patch b/queue-5.15/serial-sc16is7xx-address-rx-timeout-interrupt-errata.patch new file mode 100644 index 00000000000..38919cba37f --- /dev/null +++ b/queue-5.15/serial-sc16is7xx-address-rx-timeout-interrupt-errata.patch @@ -0,0 +1,68 @@ +From 08ce9a1b72e38cf44c300a44ac5858533eb3c860 Mon Sep 17 00:00:00 2001 +From: Daniel Mack +Date: Thu, 23 Nov 2023 08:28:18 +0100 +Subject: serial: sc16is7xx: address RX timeout interrupt errata + +From: Daniel Mack + +commit 08ce9a1b72e38cf44c300a44ac5858533eb3c860 upstream. + +This device has a silicon bug that makes it report a timeout interrupt +but no data in the FIFO. + +The datasheet states the following in the errata section 18.1.4: + + "If the host reads the receive FIFO at the same time as a + time-out interrupt condition happens, the host might read 0xCC + (time-out) in the Interrupt Indication Register (IIR), but bit 0 + of the Line Status Register (LSR) is not set (means there is no + data in the receive FIFO)." + +The errata description seems to indicate it concerns only polled mode of +operation when reading bit 0 of the LSR register. However, tests have +shown and NXP has confirmed that the RXLVL register also yields 0 when +the bug is triggered, and hence the IRQ driven implementation in this +driver is equally affected. + +This bug has hit us on production units and when it does, sc16is7xx_irq() +would spin forever because sc16is7xx_port_irq() keeps seeing an +interrupt in the IIR register that is not cleared because the driver +does not call into sc16is7xx_handle_rx() unless the RXLVL register +reports at least one byte in the FIFO. + +Fix this by always reading one byte from the FIFO when this condition +is detected in order to clear the interrupt. This approach was +confirmed to be correct by NXP through their support channels. + +Tested by: Hugo Villeneuve + +Signed-off-by: Daniel Mack +Co-Developed-by: Maxim Popov +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20231123072818.1394539-1-daniel@zonque.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/tty/serial/sc16is7xx.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/drivers/tty/serial/sc16is7xx.c ++++ b/drivers/tty/serial/sc16is7xx.c +@@ -694,6 +694,18 @@ static bool sc16is7xx_port_irq(struct sc + case SC16IS7XX_IIR_RTOI_SRC: + case SC16IS7XX_IIR_XOFFI_SRC: + rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG); ++ ++ /* ++ * There is a silicon bug that makes the chip report a ++ * time-out interrupt but no data in the FIFO. This is ++ * described in errata section 18.1.4. ++ * ++ * When this happens, read one byte from the FIFO to ++ * clear the interrupt. ++ */ ++ if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen) ++ rxlen = 1; ++ + if (rxlen) + sc16is7xx_handle_rx(port, rxlen, iir); + break; diff --git a/queue-5.15/series b/queue-5.15/series index e3a4c9fa19e..480c8e829f8 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -116,3 +116,17 @@ drm-amd-amdgpu-fix-warnings-in-amdgpu-amdgpu_display.patch drm-amdgpu-correct-the-amdgpu-runtime-dereference-us.patch kbuild-use-wdeclaration-after-statement.patch kbuild-move-to-std-gnu11.patch +usb-gadget-f_hid-fix-report-descriptor-allocation.patch +parport-add-support-for-brainboxes-ix-uc-px-parallel-cards.patch +revert-xhci-loosen-rpm-as-default-policy-to-cover-for-amd-xhc-1.1.patch +usb-typec-class-fix-typec_altmode_put_partner-to-put-plugs.patch +arm-pl011-fix-dma-support.patch +serial-sc16is7xx-address-rx-timeout-interrupt-errata.patch +serial-8250-8250_omap-clear-uart_has_rhr_it_dis-bit.patch +serial-8250-8250_omap-do-not-start-rx-dma-on-thri-interrupt.patch +serial-8250_omap-add-earlycon-support-for-the-am654-uart-controller.patch +x86-cpu-amd-check-vendor-in-the-amd-microcode-callback.patch +kvm-s390-mm-properly-reset-no-dat.patch +kvm-svm-update-efer-software-model-on-cr0-trap-for-sev-es.patch +mips-loongson64-reserve-vgabios-memory-on-boot.patch +mips-loongson64-enable-dma-noncoherent-support.patch diff --git a/queue-5.15/usb-gadget-f_hid-fix-report-descriptor-allocation.patch b/queue-5.15/usb-gadget-f_hid-fix-report-descriptor-allocation.patch new file mode 100644 index 00000000000..eb38f7efc9b --- /dev/null +++ b/queue-5.15/usb-gadget-f_hid-fix-report-descriptor-allocation.patch @@ -0,0 +1,54 @@ +From 61890dc28f7d9e9aac8a9471302613824c22fae4 Mon Sep 17 00:00:00 2001 +From: Konstantin Aladyshev +Date: Wed, 6 Dec 2023 11:07:44 +0300 +Subject: usb: gadget: f_hid: fix report descriptor allocation + +From: Konstantin Aladyshev + +commit 61890dc28f7d9e9aac8a9471302613824c22fae4 upstream. + +The commit 89ff3dfac604 ("usb: gadget: f_hid: fix f_hidg lifetime vs +cdev") has introduced a bug that leads to hid device corruption after +the replug operation. +Reverse device managed memory allocation for the report descriptor +to fix the issue. + +Tested: +This change was tested on the AMD EthanolX CRB server with the BMC +based on the OpenBMC distribution. The BMC provides KVM functionality +via the USB gadget device: +- before: KVM page refresh results in a broken USB device, +- after: KVM page refresh works without any issues. + +Fixes: 89ff3dfac604 ("usb: gadget: f_hid: fix f_hidg lifetime vs cdev") +Cc: stable@vger.kernel.org +Signed-off-by: Konstantin Aladyshev +Link: https://lore.kernel.org/r/20231206080744.253-2-aladyshev22@gmail.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/gadget/function/f_hid.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +--- a/drivers/usb/gadget/function/f_hid.c ++++ b/drivers/usb/gadget/function/f_hid.c +@@ -88,6 +88,7 @@ static void hidg_release(struct device * + { + struct f_hidg *hidg = container_of(dev, struct f_hidg, dev); + ++ kfree(hidg->report_desc); + kfree(hidg->set_report_buf); + kfree(hidg); + } +@@ -1287,9 +1288,9 @@ static struct usb_function *hidg_alloc(s + hidg->report_length = opts->report_length; + hidg->report_desc_length = opts->report_desc_length; + if (opts->report_desc) { +- hidg->report_desc = devm_kmemdup(&hidg->dev, opts->report_desc, +- opts->report_desc_length, +- GFP_KERNEL); ++ hidg->report_desc = kmemdup(opts->report_desc, ++ opts->report_desc_length, ++ GFP_KERNEL); + if (!hidg->report_desc) { + put_device(&hidg->dev); + --opts->refcnt; diff --git a/queue-5.15/usb-typec-class-fix-typec_altmode_put_partner-to-put-plugs.patch b/queue-5.15/usb-typec-class-fix-typec_altmode_put_partner-to-put-plugs.patch new file mode 100644 index 00000000000..420850aa7dd --- /dev/null +++ b/queue-5.15/usb-typec-class-fix-typec_altmode_put_partner-to-put-plugs.patch @@ -0,0 +1,51 @@ +From b17b7fe6dd5c6ff74b38b0758ca799cdbb79e26e Mon Sep 17 00:00:00 2001 +From: RD Babiera +Date: Wed, 29 Nov 2023 19:23:50 +0000 +Subject: usb: typec: class: fix typec_altmode_put_partner to put plugs + +From: RD Babiera + +commit b17b7fe6dd5c6ff74b38b0758ca799cdbb79e26e upstream. + +When typec_altmode_put_partner is called by a plug altmode upon release, +the port altmode the plug belongs to will not remove its reference to the +plug. The check to see if the altmode being released evaluates against the +released altmode's partner instead of the calling altmode itself, so change +adev in typec_altmode_put_partner to properly refer to the altmode being +released. + +typec_altmode_set_partner is not run for port altmodes, so also add a check +in typec_altmode_release to prevent typec_altmode_put_partner() calls on +port altmode release. + +Fixes: 8a37d87d72f0 ("usb: typec: Bus type for alternate modes") +Cc: stable@vger.kernel.org +Signed-off-by: RD Babiera +Reviewed-by: Heikki Krogerus +Link: https://lore.kernel.org/r/20231129192349.1773623-2-rdbabiera@google.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/typec/class.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/usb/typec/class.c ++++ b/drivers/usb/typec/class.c +@@ -265,7 +265,7 @@ static void typec_altmode_put_partner(st + if (!partner) + return; + +- adev = &partner->adev; ++ adev = &altmode->adev; + + if (is_typec_plug(adev->dev.parent)) { + struct typec_plug *plug = to_typec_plug(adev->dev.parent); +@@ -495,7 +495,8 @@ static void typec_altmode_release(struct + { + struct altmode *alt = to_altmode(to_typec_altmode(dev)); + +- typec_altmode_put_partner(alt); ++ if (!is_typec_port(dev->parent)) ++ typec_altmode_put_partner(alt); + + altmode_id_remove(alt->adev.dev.parent, alt->id); + kfree(alt); diff --git a/queue-5.15/x86-cpu-amd-check-vendor-in-the-amd-microcode-callback.patch b/queue-5.15/x86-cpu-amd-check-vendor-in-the-amd-microcode-callback.patch new file mode 100644 index 00000000000..00945ce95f5 --- /dev/null +++ b/queue-5.15/x86-cpu-amd-check-vendor-in-the-amd-microcode-callback.patch @@ -0,0 +1,52 @@ +From 9b8493dc43044376716d789d07699f17d538a7c4 Mon Sep 17 00:00:00 2001 +From: "Borislav Petkov (AMD)" +Date: Fri, 1 Dec 2023 19:37:27 +0100 +Subject: x86/CPU/AMD: Check vendor in the AMD microcode callback + +From: Borislav Petkov (AMD) + +commit 9b8493dc43044376716d789d07699f17d538a7c4 upstream. + +Commit in Fixes added an AMD-specific microcode callback. However, it +didn't check the CPU vendor the kernel runs on explicitly. + +The only reason the Zenbleed check in it didn't run on other x86 vendors +hardware was pure coincidental luck: + + if (!cpu_has_amd_erratum(c, amd_zenbleed)) + return; + +gives true on other vendors because they don't have those families and +models. + +However, with the removal of the cpu_has_amd_erratum() in + + 05f5f73936fa ("x86/CPU/AMD: Drop now unused CPU erratum checking function") + +that coincidental condition is gone, leading to the zenbleed check +getting executed on other vendors too. + +Add the explicit vendor check for the whole callback as it should've +been done in the first place. + +Fixes: 522b1d69219d ("x86/cpu/amd: Add a Zenbleed fix") +Cc: +Signed-off-by: Borislav Petkov (AMD) +Link: https://lore.kernel.org/r/20231201184226.16749-1-bp@alien8.de +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/kernel/cpu/amd.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/arch/x86/kernel/cpu/amd.c ++++ b/arch/x86/kernel/cpu/amd.c +@@ -1316,6 +1316,9 @@ static void zenbleed_check_cpu(void *unu + + void amd_check_microcode(void) + { ++ if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) ++ return; ++ + on_each_cpu(zenbleed_check_cpu, NULL, 1); + } +