From: Jim Lin <jim@andestech.com>
Date: Mon, 6 Jul 2026 15:37:25 +0000 (-0600)
Subject: [PATCH] RISC-V: Skip shift-shift-7.c under -Og
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=413d90e7515b571bbbf33475695ba042cf5890a6;p=thirdparty%2Fgcc.git

[PATCH] RISC-V: Skip shift-shift-7.c under -Og

At -Og the a << 1 is kept as a separate slliw instead of being folded
into the zero_extendsidi2_shifted sequence, so the "slli" regex matches
both slliw and slli and the scan-assembler-times "slli" 1 check fails.
Skip the test under -Og.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/shift-shift-7.c: Skip under -Og.
---

diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-7.c b/gcc/testsuite/gcc.target/riscv/shift-shift-7.c
index 3ecd9ebdc39..8fe9143960e 100644
--- a/gcc/testsuite/gcc.target/riscv/shift-shift-7.c
+++ b/gcc/testsuite/gcc.target/riscv/shift-shift-7.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gc -mabi=lp64" } */
-/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
 
 /* Test for zero_extendsidi2_shifted handling arbitrary mask widths
    (not just 32 bits). */