From: Peter Maydell Date: Wed, 18 Feb 2026 18:40:13 +0000 (+0000) Subject: target/arm: Account for SME in aarch64_sve_narrow_vq() assertion X-Git-Tag: v11.0.0-rc0~60^2~31 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=42eab40a12f12f044a5ca7b7d889d9a1f0d172ee;p=thirdparty%2Fqemu.git target/arm: Account for SME in aarch64_sve_narrow_vq() assertion In aarch64_sve_narrow_vq() we assert that the new VQ is within the maximum supported range for the CPU. We forgot to update this to account for SME, which might have a different maximum. Update the assert to permit any VQ which is valid for either SVE or SME. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20260202133353.2231685-2-peter.maydell@linaro.org --- diff --git a/target/arm/helper.c b/target/arm/helper.c index 8c5769477cf..373f0ebcb34 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10088,7 +10088,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) uint64_t pmask; assert(vq >= 1 && vq <= ARM_MAX_VQ); - assert(vq <= env_archcpu(env)->sve_max_vq); + assert(vq <= arm_max_vq(env_archcpu(env))); /* Zap the high bits of the zregs. */ for (i = 0; i < 32; i++) { diff --git a/target/arm/internals.h b/target/arm/internals.h index f7b641342a4..8ec27508473 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1808,6 +1808,15 @@ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env) ((1 << (1 - 1)) | (1 << (2 - 1)) | \ (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1))) +/* + * Return the maximum SVE/SME VQ for this CPU. This defines + * the maximum possible size of the Zn vector registers. + */ +static inline int arm_max_vq(ARMCPU *cpu) +{ + return MAX(cpu->sve_max_vq, cpu->sme_max_vq); +} + /* * Return true if it is possible to take a fine-grained-trap to EL2. */