From: Julian Seward <jseward@acm.org>
Date: Fri, 10 Sep 2004 20:25:11 +0000 (+0000)
Subject: x86 -> IR changes:
X-Git-Tag: svn/VALGRIND_3_0_1^2~1081
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=43fb538659d4df9d355391c5e29599bc8e4bb55a;p=thirdparty%2Fvalgrind.git

x86 -> IR changes:
* fix bug in movsbl/swl/sbw causing zero extension
* more ADC cases
* FIDIVR m32


git-svn-id: svn://svn.valgrind.org/vex/trunk@253
---

diff --git a/VEX/priv/guest-x86/toIR.c b/VEX/priv/guest-x86/toIR.c
index c640e70c8e..fda5c61fce 100644
--- a/VEX/priv/guest-x86/toIR.c
+++ b/VEX/priv/guest-x86/toIR.c
@@ -1703,7 +1703,6 @@ UInt dis_op2_E_G ( UChar       sorb,
       assign( src,  loadLE(szToITy(size), mkexpr(addr)) );
 
       if (addSubCarry && op8 == Iop_Add8) {
-         vassert(0);
          helper_ADC( size, dst1, dst0, src );
          putIReg(size, gregOfRM(rm), mkexpr(dst1));
       } else
@@ -1968,7 +1967,7 @@ UInt dis_movx_E_G ( UChar       sorb,
    UChar rm = getIByte(delta);
    if (epartIsReg(rm)) {
       putIReg(szd, gregOfRM(rm),
-	           unop(mkWidenOp(szs,szd,False), 
+	           unop(mkWidenOp(szs,szd,sign_extend), 
 		        getIReg(szs,eregOfRM(rm))));
       DIP("mov%c%c%c %s,%s\n", sign_extend ? 's' : 'z',
                                nameISize(szs), nameISize(szd),
@@ -1984,7 +1983,7 @@ UInt dis_movx_E_G ( UChar       sorb,
       IRTemp addr = disAMode ( &len, sorb, delta, dis_buf );
 
       putIReg(szd, gregOfRM(rm),
-	           unop(mkWidenOp(szs,szd,False), 
+	           unop(mkWidenOp(szs,szd,sign_extend), 
                         loadLE(szToITy(szs),mkexpr(addr))));
       DIP("mov%c%c%c %s,%s\n", sign_extend ? 's' : 'z',
                                nameISize(szs), nameISize(szd),
@@ -3632,6 +3631,11 @@ UInt dis_FPU ( Bool* decode_ok, UChar sorb, UInt delta )
 	       fop = Iop_DivF64;
 	       goto do_fop_m32;
 
+            case 7: /* FIDIVR m32int */ /* ST(0) = m32int / ST(0) */
+               DIP("fisubrl %s", dis_buf);
+	       fop = Iop_DivF64;
+	       goto do_foprev_m32;
+
             do_fop_m32:
                put_ST_UNCHECKED(0, 
                   binop(fop, 
@@ -3640,6 +3644,14 @@ UInt dis_FPU ( Bool* decode_ok, UChar sorb, UInt delta )
                              loadLE(Ity_I32, mkexpr(addr)))));
                break;
 
+            do_foprev_m32:
+               put_ST_UNCHECKED(0, 
+                  binop(fop, 
+                        unop(Iop_I32toF64,
+                             loadLE(Ity_I32, mkexpr(addr))),
+                        get_ST(0)));
+               break;
+
             default:
                vex_printf("unhandled opc_aux = 0x%2x\n", gregOfRM(modrm));
                vex_printf("first_opcode == 0xDA\n");
@@ -7562,10 +7574,10 @@ static UInt disInstr ( UInt delta, Bool* isEnd )
 //--    case 0x12: /* ADC Eb,Gb */
 //--       delta = dis_op2_E_G ( sorb, True, ADC, True, 1, delta, "adc" );
 //--       break;
-//--    case 0x13: /* ADC Ev,Gv */
-//--       delta = dis_op2_E_G ( sorb, True, ADC, True, sz, delta, "adc" );
-//--       break;
-//-- 
+   case 0x13: /* ADC Ev,Gv */
+      delta = dis_op2_E_G ( sorb, True, Iop_Add8, True, sz, delta, "adc" );
+      break;
+
 //--    case 0x1A: /* SBB Eb,Gb */
 //--       delta = dis_op2_E_G ( sorb, True, SBB, True, 1, delta, "sbb" );
 //--       break;