From: sayle Date: Sat, 12 Mar 2005 04:56:29 +0000 (+0000) Subject: PR middle-end/20419 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=44b0f1d0af17ec80ac6369cd7e7f5c7343e51b69;p=thirdparty%2Fgcc.git PR middle-end/20419 * builtins.c (expand_builtin_signbit): Force the signbit's word into an integer register to avoid SUBREGs of floating point modes. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@96328 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0bbe5866c84f..3e9f384253d2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2005-03-11 Roger Sayle + + PR middle-end/20419 + * builtins.c (expand_builtin_signbit): Force the signbit's word + into an integer register to avoid SUBREGs of floating point modes. + 2005-03-12 Kazu Hirata * cfglayout.c, loop-doloop.c, profile.c, target-def.h, diff --git a/gcc/builtins.c b/gcc/builtins.c index 4f464746b9a8..e6e07171f742 100644 --- a/gcc/builtins.c +++ b/gcc/builtins.c @@ -5003,6 +5003,11 @@ expand_builtin_signbit (tree exp, rtx target) bitpos = bitpos % BITS_PER_WORD; } + /* Force the intermediate word_mode (or narrower) result into a + register. This avoids attempting to create paradoxical SUBREGs + of floating point modes below. */ + temp = force_reg (imode, temp); + /* If the bitpos is within the "result mode" lowpart, the operation can be implement with a single bitwise AND. Otherwise, we need a right shift and an AND. */