From: Dave Jiang <dave.jiang@intel.com>
Date: Thu, 18 Sep 2025 21:34:51 +0000 (-0700)
Subject: Merge branch 'for-6.18/cxl-delay-dport' into cxl-for-next
X-Git-Tag: v6.18-rc1~85^2
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=46037455cbb748c5e85071c95f2244e81986eb58;p=thirdparty%2Fkernel%2Flinux.git

Merge branch 'for-6.18/cxl-delay-dport' into cxl-for-next

Add changes to delay the allocation and setup of dports until when the
endpoint device is being probed. At this point, the CXL link is
established from endpoint to host bridge. Addresses issues seen on
some platforms when dports are probed earlier.

Link: https://lore.kernel.org/linux-cxl/20250829180928.842707-1-dave.jiang@intel.com/
---

46037455cbb748c5e85071c95f2244e81986eb58
diff --cc drivers/cxl/acpi.c
index ff15dac3f2944,bb0871d926206..d7a5539d07d4f
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@@ -475,16 -471,10 +474,16 @@@ static int __cxl_parse_cfmws(struct acp
  
  	cxlrd->qos_class = cfmws->qtg_id;
  
 -	if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR)
 -		cxlrd->hpa_to_spa = cxl_xor_hpa_to_spa;
 +	if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
 +		cxlrd->ops = kzalloc(sizeof(*cxlrd->ops), GFP_KERNEL);
 +		if (!cxlrd->ops)
 +			return -ENOMEM;
 +
 +		cxlrd->ops->hpa_to_spa = cxl_apply_xor_maps;
 +		cxlrd->ops->spa_to_hpa = cxl_apply_xor_maps;
 +	}
  
- 	rc = cxl_decoder_add(cxld, target_map);
+ 	rc = cxl_decoder_add(cxld);
  	if (rc)
  		return rc;