From: Julian Seward <jseward@acm.org>
Date: Mon, 26 May 2003 09:17:41 +0000 (+0000)
Subject: Teach memcheck about the SSE UInstrs generated thus far.  So now the
X-Git-Tag: svn/VALGRIND_2_0_0~131
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=474d73ecf5ea980f206764fe4abfabf0ddf82aad;p=thirdparty%2Fvalgrind.git

Teach memcheck about the SSE UInstrs generated thus far.  So now the
Qt GL demos run on memcheck.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@1653
---

diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c
index 9bbe74936b..1a9f4d65fc 100644
--- a/memcheck/mc_main.c
+++ b/memcheck/mc_main.c
@@ -1156,7 +1156,8 @@ void MC_(fpu_read_check) ( Addr addr, Int size )
       return;
    }
 
-   if (size == 10 || size == 28 || size == 108) {
+   if (size == 16 /*SSE*/ 
+       || size == 10 || size == 28 || size == 108) {
       PROF_EVENT(84);
       mc_fpu_read_check_SLOWLY ( addr, size );
       return;
@@ -1238,7 +1239,8 @@ void MC_(fpu_write_check) ( Addr addr, Int size )
       return;
    }
 
-   if (size == 10 || size == 28 || size == 108) {
+   if (size == 16 /*SSE*/ 
+       || size == 10 || size == 28 || size == 108) {
       PROF_EVENT(89);
       mc_fpu_write_check_SLOWLY ( addr, size );
       return;
diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c
index 8994e0ff9d..da4969e31c 100644
--- a/memcheck/mc_translate.c
+++ b/memcheck/mc_translate.c
@@ -1080,7 +1080,37 @@ static UCodeBlock* memcheck_instrument ( UCodeBlock* cb_in )
             break;
          }
 
-         /* For FPU insns not referencing memory, just copy thru. */
+         /* ... and the same deal for SSE insns referencing memory. */
+         case SSE3a_MemRd:
+         case SSE3a_MemWr:
+         case SSE2a_MemWr:
+         case SSE2a_MemRd: { 
+            Bool is_load;
+            Int t_size;
+
+            sk_assert(u_in->size == 4 || u_in->size == 16);
+
+            t_size = INVALID_TEMPREG;
+            is_load = u_in->opcode==SSE2a_MemRd
+                      || u_in->opcode==SSE3a_MemRd;
+            sk_assert(u_in->tag3 == TempReg);
+            uInstr1(cb, TESTV, 4, TempReg, SHADOW(u_in->val3));
+            uInstr1(cb, SETV,  4, TempReg, SHADOW(u_in->val3));
+
+            t_size = newTemp(cb);
+            uInstr2(cb, MOV,   4, Literal, 0, TempReg, t_size);
+            uLiteral(cb, u_in->size);
+            uInstr2(cb, CCALL, 0, TempReg, u_in->val3, TempReg, t_size);
+            uCCall(cb, is_load ? (Addr) & MC_(fpu_read_check) 
+                               : (Addr) & MC_(fpu_write_check),
+                   2, 2, False);
+            VG_(copy_UInstr)(cb, u_in);
+            break;
+         }
+
+         /* For FPU, MMX and SSE insns not referencing memory, just
+	    copy thru. */
+         case SSE4: case SSE3:
          case MMX1: case MMX2: case MMX3:
          case FPU: 
             VG_(copy_UInstr)(cb, u_in);