From: Michal Simek Date: Wed, 5 Aug 2015 13:41:18 +0000 (+0200) Subject: Merge tag 'v2015.07' into xilinx/master X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=4954f5b8310fb00b167a425f92d3c58b0592aa80;p=thirdparty%2Fu-boot.git Merge tag 'v2015.07' into xilinx/master Prepare v2015.07 - Use CONFIG_ARCH_ZYNQ instead of CONFIG_ZYNQ - Enable DM for SPI and OF_CONTROL for Zynq - Enable OF_EMBED by default for all Zynq boards and change SPL target for loading in MMC mode - Add missing DTS files for Xilinx internal platforms - Fix ahci_init parameter recasting for ZynqMP - Fix board parameter setup for ZynqMP - Remove config_cmd_default.h from ancient platforms - Use microblaze-generic mainline configuration Signed-off-by: Michal Simek --- 4954f5b8310fb00b167a425f92d3c58b0592aa80 diff --cc Kconfig index 708d584694b,15e15af5b3c..fc69189217a --- a/Kconfig +++ b/Kconfig @@@ -178,7 -178,7 +178,7 @@@ config SYS_EXTRA_OPTION new boards should not use this option. config SYS_TEXT_BASE - depends on SPARC || ARC || ARCH_ZYNQMP - depends on SPARC || ARC || X86 || ARCH_UNIPHIER ++ depends on SPARC || ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP hex "Text Base" help TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture diff --cc Makefile index e7606b61ac6,a7dce064081..843e81a082f mode 100755,100644..100755 --- a/Makefile +++ b/Makefile @@@ -762,12 -768,6 +768,12 @@@ endi endif endif - ifneq ($(CONFIG_ZYNQ),) ++ifneq ($(CONFIG_ARCH_ZYNQ),) +ifeq ($(CONFIG_SPL),y) +ALL-y += boot.bin +endif +endif + # Add optional build target if defined in board/cpu/soc headers ifneq ($(CONFIG_BUILD_TARGET),) ALL-y += $(CONFIG_BUILD_TARGET:"%"=%) diff --cc arch/arm/Kconfig index 9f99737d7f1,9908b430d62..7c026441539 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@@ -621,8 -666,13 +666,13 @@@ config ARCH_ZYN bool "Xilinx Zynq Platform" select CPU_V7 select SUPPORT_SPL + select OF_CONTROL + select SPL_DISABLE_OF_CONTROL + select DM + select DM_SPI + select DM_SPI_FLASH -config TARGET_XILINX_ZYNQMP +config ARCH_ZYNQMP bool "Support Xilinx ZynqMP Platform" select ARM64 diff --cc arch/arm/dts/Makefile index e08546b860d,19e1de67a0b..935afe16a30 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@@ -44,9 -43,8 +43,16 @@@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.d zynq-zed.dtb \ zynq-zybo.dtb \ zynq-microzed.dtb \ + zynq-cc108.dtb \ ++ zynq-afx-nand.dtb \ ++ zynq-afx-nor.dtb \ ++ zynq-afx-qspi.dtb \ ++ zynq-cse-nand.dtb \ ++ zynq-cse-nor.dtb \ ++ zynq-cse-qspi.dtb \ + zynq-picozed.dtb \ zynq-zc770-xm010.dtb \ + zynq-zc770-xm011.dtb \ zynq-zc770-xm012.dtb \ zynq-zc770-xm013.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb diff --cc arch/arm/dts/zynq-afx-nand.dts index 00000000000,00000000000..cbb56a69793 new file mode 100644 --- /dev/null +++ b/arch/arm/dts/zynq-afx-nand.dts @@@ -1,0 -1,0 +1,79 @@@ ++/* ++ * Device Tree Generator version: 1.1 ++ * ++ * (C) Copyright 2007-2013 Xilinx, Inc. ++ * (C) Copyright 2007-2013 Michal Simek ++ * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd ++ * ++ * Michal SIMEK ++ * ++ * CAUTION: This file is automatically generated by libgen. ++ * Version: Xilinx EDK 14.5 EDK_P.58f ++ * ++ */ ++/dts-v1/; ++/include/ "zynq-7000.dtsi" ++ ++/ { ++ compatible = "xlnx,zynq-afx-nand", "xlnx,zynq-7000"; ++ model = "Xilinx Zynq"; ++ ++ aliases { ++ serial0 = &uart1; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; ++ linux,stdout-path = &uart1; ++ stdout-path = &uart1; ++ }; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x8000000>; ++ }; ++}; ++ ++&smcc { ++ status = "okay"; ++ arm,addr25 = <0x0>; ++ arm,nor-chip-sel0 = <0x0>; ++ arm,nor-chip-sel1 = <0x0>; ++ arm,sram-chip-sel0 = <0x0>; ++ arm,sram-chip-sel1 = <0x0>; ++}; ++ ++&nand0 { ++ status = "okay"; ++ arm,nand-cycle-t0 = <0x4>; ++ arm,nand-cycle-t1 = <0x4>; ++ arm,nand-cycle-t2 = <0x1>; ++ arm,nand-cycle-t3 = <0x2>; ++ arm,nand-cycle-t4 = <0x2>; ++ arm,nand-cycle-t5 = <0x2>; ++ arm,nand-cycle-t6 = <0x4>; ++ partition@nand-fsbl-uboot { ++ label = "nand-fsbl-uboot"; ++ reg = <0x0 0x100000>; ++ }; ++ partition@nand-linux { ++ label = "nand-linux"; ++ reg = <0x100000 0x500000>; ++ }; ++ partition@nand-device-tree { ++ label = "nand-device-tree"; ++ reg = <0x600000 0x20000>; ++ }; ++ partition@nand-rootfs { ++ label = "nand-rootfs"; ++ reg = <0x620000 0x5E0000>; ++ }; ++ partition@nand-bitstream { ++ label = "nand-bitstream"; ++ reg = <0xC00000 0x400000>; ++ }; ++}; ++ ++&uart1 { ++ status = "okay"; ++}; diff --cc arch/arm/dts/zynq-afx-nor.dts index 00000000000,00000000000..3c79ae384ca new file mode 100644 --- /dev/null +++ b/arch/arm/dts/zynq-afx-nor.dts @@@ -1,0 -1,0 +1,80 @@@ ++/* ++ * Device Tree Generator version: 1.1 ++ * ++ * (C) Copyright 2007-2013 Xilinx, Inc. ++ * (C) Copyright 2007-2013 Michal Simek ++ * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd ++ * ++ * Michal SIMEK ++ * ++ * CAUTION: This file is automatically generated by libgen. ++ * Version: Xilinx EDK 14.5 EDK_P.58f ++ * ++ */ ++/dts-v1/; ++/include/ "zynq-7000.dtsi" ++ ++/ { ++ compatible = "xlnx,zynq-afx-nor", "xlnx,zynq-7000"; ++ model = "Xilinx Zynq"; ++ ++ aliases { ++ serial0 = &uart1; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; ++ linux,stdout-path = &uart1; ++ stdout-path = &uart1; ++ }; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x8000000>; ++ }; ++}; ++ ++&smcc { ++ status = "okay"; ++ arm,addr25 = <0x1>; ++ arm,nor-chip-sel0 = <0x1>; ++ arm,nor-chip-sel1 = <0x0>; ++ arm,sram-chip-sel0 = <0x0>; ++ arm,sram-chip-sel1 = <0x0>; ++}; ++ ++&nor0 { ++ status = "okay"; ++ bank-width = <1>; ++ xlnx,sram-cycle-t0 = <0xb>; ++ xlnx,sram-cycle-t1 = <0xb>; ++ xlnx,sram-cycle-t2 = <0x5>; ++ xlnx,sram-cycle-t3 = <0x4>; ++ xlnx,sram-cycle-t4 = <0x3>; ++ xlnx,sram-cycle-t5 = <0x3>; ++ xlnx,sram-cycle-t6 = <0x2>; ++ partition@nor-fsbl-uboot { ++ label = "nor-fsbl-uboot"; ++ reg = <0x0 0x100000>; ++ }; ++ partition@nor-linux { ++ label = "nor-linux"; ++ reg = <0x100000 0x500000>; ++ }; ++ partition@nor-device-tree { ++ label = "nor-device-tree"; ++ reg = <0x600000 0x20000>; ++ }; ++ partition@nor-rootfs { ++ label = "nor-rootfs"; ++ reg = <0x620000 0x5E0000>; ++ }; ++ partition@nor-bitstream { ++ label = "nor-bitstream"; ++ reg = <0xC00000 0x400000>; ++ }; ++}; ++ ++&uart1 { ++ status = "okay"; ++}; diff --cc arch/arm/dts/zynq-afx-qspi.dts index 00000000000,00000000000..9c2f9d7e899 new file mode 100644 --- /dev/null +++ b/arch/arm/dts/zynq-afx-qspi.dts @@@ -1,0 -1,0 +1,84 @@@ ++/* ++ * Device Tree Generator version: 1.1 ++ * ++ * (C) Copyright 2007-2013 Xilinx, Inc. ++ * (C) Copyright 2007-2013 Michal Simek ++ * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd ++ * ++ * Michal SIMEK ++ * ++ * CAUTION: This file is automatically generated by libgen. ++ * Version: Xilinx EDK 14.5 EDK_P.58f ++ * ++ */ ++/dts-v1/; ++/include/ "zynq-7000.dtsi" ++ ++/ { ++ compatible = "xlnx,zynq-afx-qspi", "xlnx,zynq-7000"; ++ model = "Xilinx Zynq"; ++ ++ aliases { ++ serial0 = &uart1; ++ spi0 = &qspi; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; ++ linux,stdout-path = &uart1; ++ stdout-path = &uart1; ++ }; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x8000000>; ++ }; ++}; ++ ++&smcc { ++ status = "okay"; ++ arm,addr25 = <0x1>; ++ arm,nor-chip-sel0 = <0x1>; ++ arm,nor-chip-sel1 = <0x0>; ++ arm,sram-chip-sel0 = <0x0>; ++ arm,sram-chip-sel1 = <0x0>; ++}; ++ ++&qspi { ++ status = "okay"; ++ is-dual = <0>; ++ num-cs = <1>; ++ flash@0 { ++ compatible = "is25lp128"; ++ reg = <0x0>; ++ spi-tx-bus-width = <1>; ++ spi-rx-bus-width = <4>; ++ spi-max-frequency = <50000000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ partition@qspi-fsbl-uboot { ++ label = "qspi-fsbl-uboot"; ++ reg = <0x0 0x100000>; ++ }; ++ partition@qspi-linux { ++ label = "qspi-linux"; ++ reg = <0x100000 0x500000>; ++ }; ++ partition@qspi-device-tree { ++ label = "qspi-device-tree"; ++ reg = <0x600000 0x20000>; ++ }; ++ partition@qspi-rootfs { ++ label = "qspi-rootfs"; ++ reg = <0x620000 0x5E0000>; ++ }; ++ partition@qspi-bitstream { ++ label = "qspi-bitstream"; ++ reg = <0xC00000 0x400000>; ++ }; ++ }; ++}; ++ ++&uart1 { ++ status = "okay"; ++}; diff --cc arch/arm/dts/zynq-cse-nand.dts index 00000000000,00000000000..e0411f6a345 new file mode 100644 --- /dev/null +++ b/arch/arm/dts/zynq-cse-nand.dts @@@ -1,0 -1,0 +1,14 @@@ ++/* ++ * Xilinx CSE NAND board DTS ++ * ++ * Copyright (C) 2015 Xilinx, Inc. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++/dts-v1/; ++#include "zynq-7000.dtsi" ++ ++/ { ++ model = "Zynq CSE NAND Board"; ++ compatible = "xlnx,zynq-cse-nand", "xlnx,zynq-7000"; ++}; diff --cc arch/arm/dts/zynq-cse-nor.dts index 00000000000,00000000000..80f14464add new file mode 100644 --- /dev/null +++ b/arch/arm/dts/zynq-cse-nor.dts @@@ -1,0 -1,0 +1,14 @@@ ++/* ++ * Xilinx CSE NOR board DTS ++ * ++ * Copyright (C) 2015 Xilinx, Inc. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++/dts-v1/; ++#include "zynq-7000.dtsi" ++ ++/ { ++ model = "Zynq CSE NOR Board"; ++ compatible = "xlnx,zynq-cse-nor", "xlnx,zynq-7000"; ++}; diff --cc arch/arm/dts/zynq-cse-qspi.dts index 00000000000,00000000000..ef71da95c63 new file mode 100644 --- /dev/null +++ b/arch/arm/dts/zynq-cse-qspi.dts @@@ -1,0 -1,0 +1,14 @@@ ++/* ++ * Xilinx CSE QSPI board DTS ++ * ++ * Copyright (C) 2015 Xilinx, Inc. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++/dts-v1/; ++#include "zynq-7000.dtsi" ++ ++/ { ++ model = "Zynq CSE QSPI Board"; ++ compatible = "xlnx,zynq-cse-qspi", "xlnx,zynq-7000"; ++}; diff --cc arch/arm/include/asm/arch-zynqmp/hardware.h index a809e0cb529,c9dc49d7831..5df45875a3c --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@@ -19,7 -14,6 +19,8 @@@ #define ZYNQ_SPI_BASEADDR0 0xFF040000 #define ZYNQ_SPI_BASEADDR1 0xFF050000 +#define ZYNQMP_QSPI_BASEADDR 0xFF0F0000 ++ #define ZYNQ_I2C_BASEADDR0 0xFF020000 #define ZYNQ_I2C_BASEADDR1 0xFF030000 diff --cc arch/arm/include/asm/system.h index b0cf6d9fb7e,760e8ab1c8c..0f973c98b64 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@@ -216,6 -250,30 +256,20 @@@ enum MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT, }; + #ifdef CONFIG_ARMV7 + /* TTBR0 bits */ + #define TTBR0_BASE_ADDR_MASK 0xFFFFC000 + #define TTBR0_RGN_NC (0 << 3) + #define TTBR0_RGN_WBWA (1 << 3) + #define TTBR0_RGN_WT (2 << 3) + #define TTBR0_RGN_WB (3 << 3) + /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */ + #define TTBR0_IRGN_NC (0 << 0 | 0 << 6) + #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6) + #define TTBR0_IRGN_WT (1 << 0 | 0 << 6) + #define TTBR0_IRGN_WB (1 << 0 | 1 << 6) + #endif + -/** - * Change the cache settings for a region. - * - * \param start start address of memory region to change - * \param size size of memory region to change - * \param option dcache option to select - */ -void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, - enum dcache_option option); - /** * Register an update to the page tables, and flush the TLB * diff --cc arch/arm/mach-zynq/Kconfig index 00000000000,1de5b0710a6..fc8989b4ec4 mode 000000,100644..100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@@ -1,0 -1,65 +1,80 @@@ + if ARCH_ZYNQ + + config ZYNQ_CUSTOM_INIT + bool "Use custom ps7_init provided by Xilinx tool" + help + U-Boot includes ps7_init_gpl.[ch] for some Zynq board variants. + If you want to override them with customized ones + or ps7_init code for your board is missing, please say Y here + and add ones into board/xilinx/zynq/custom_hw_platform/ directory. + + choice + prompt "Xilinx Zynq board select" + optional + + config TARGET_ZYNQ_ZED + bool "Zynq ZedBoard" + + config TARGET_ZYNQ_MICROZED + bool "Zynq MicroZed" + + config TARGET_ZYNQ_PICOZED + bool "Zynq PicoZed" + + config TARGET_ZYNQ_ZC70X + bool "Zynq ZC702/ZC706 Board (deprecated)" + select ZYNQ_CUSTOM_INIT + help + This option is deprecated. Use TARGET_ZYNQ_ZC702 + or TARGET_ZYNQ_706. + + config TARGET_ZYNQ_ZC702 + bool "Zynq ZC702 Board" + + config TARGET_ZYNQ_ZC706 + bool "Zynq ZC706 Board" + + config TARGET_ZYNQ_ZC770 + bool "Zynq ZC770 Board" + select ZYNQ_CUSTOM_INIT + + config TARGET_ZYNQ_ZYBO + bool "Zynq Zybo Board" + select ZYNQ_CUSTOM_INIT + ++config TARGET_ZYNQ_AFX ++ bool "Zynq AFX Board" ++ select ZYNQ_CUSTOM_INIT ++ ++config TARGET_ZYNQ_CSE ++ bool "Zynq CSE Board" ++ select ZYNQ_CUSTOM_INIT ++ ++config TARGET_ZYNQ_CC108 ++ bool "Zynq CC108 Board" ++ select ZYNQ_CUSTOM_INIT ++ + endchoice + + config SYS_BOARD + default "zynq" + + config SYS_VENDOR + default "xilinx" + + config SYS_SOC + default "zynq" + + config SYS_CONFIG_NAME + default "zynq_zed" if TARGET_ZYNQ_ZED + default "zynq_microzed" if TARGET_ZYNQ_MICROZED + default "zynq_picozed" if TARGET_ZYNQ_PICOZED + default "zynq_zc70x" if TARGET_ZYNQ_ZC702 || TARGET_ZYNQ_ZC706 \ + || TARGET_ZYNQ_ZC70X + default "zynq_zc770" if TARGET_ZYNQ_ZC770 + default "zynq_zybo" if TARGET_ZYNQ_ZYBO ++ default "zynq_cse" if TARGET_ZYNQ_CSE ++ default "zynq_afx" if TARGET_ZYNQ_AFX ++ default "zynq_cc108" if TARGET_ZYNQ_CC108 + + endif diff --cc arch/arm/mach-zynq/config.mk index d4f3332949c,00000000000..d4f3332949c mode 100644,000000..100644 --- a/arch/arm/mach-zynq/config.mk +++ b/arch/arm/mach-zynq/config.mk diff --cc board/xilinx/zynqmp/zynqmp.c index 3fc65eb44c9,f5ff64d988e..a8152109b81 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@@ -55,39 -51,6 +55,39 @@@ void reset_cpu(ulong addr { } +#ifdef CONFIG_SCSI_AHCI_PLAT +void scsi_init(void) +{ - ahci_init(ZYNQMP_SATA_BASEADDR); ++ ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR); + scsi_scan(1); +} +#endif + +int board_eth_init(bd_t *bis) +{ + u32 ret = 0; + +#if defined(CONFIG_ZYNQ_GEM) +# if defined(CONFIG_ZYNQ_GEM0) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, + CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); +# endif +# if defined(CONFIG_ZYNQ_GEM1) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, + CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); +# endif +# if defined(CONFIG_ZYNQ_GEM2) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR2, + CONFIG_ZYNQ_GEM_PHY_ADDR2, 0); +# endif +# if defined(CONFIG_ZYNQ_GEM3) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR3, + CONFIG_ZYNQ_GEM_PHY_ADDR3, 0); +# endif +#endif + return ret; +} + #ifdef CONFIG_CMD_MMC int board_mmc_init(bd_t *bd) { @@@ -113,23 -77,6 +113,18 @@@ int board_late_init(void { u32 reg = 0; u8 bootmode; + u32 ver = zynqmp_get_silicon_version(); + + switch (ver) { + case ZYNQMP_CSU_VERSION_VELOCE: - setenv("baudrate", "4800"); - setenv("bootcmd", "run veloce"); ++ setenv("setup", "setenv baudrate 4800 && setenv bootcmd run veloce"); + case ZYNQMP_CSU_VERSION_EP108: - setenv("serverip", "10.10.70.101"); - setenv("ipaddr", "10.10.71.100"); - setenv("partid", "auto"); ++ setenv("setup", "setenv serverip 10.10.70.101 && setenv ipaddr 10.10.71.100 && setenv partid auto"); + break; + case ZYNQMP_CSU_VERSION_QEMU: + default: - setenv("serverip", "10.0.2.2"); - setenv("ipaddr", "10.0.2.15"); - setenv("partid", "0"); ++ setenv("setup", "setenv serverip 10.0.2.2 && setenv ipaddr 10.0.2.15 && setenv partid 0"); + } reg = readl(&crlapb_base->boot_mode); bootmode = reg & BOOT_MODES_MASK; diff --cc common/Kconfig index 6b42d4acde5,40cd69ed708..7299f5f0e57 --- a/common/Kconfig +++ b/common/Kconfig @@@ -339,11 -464,158 +464,163 @@@ config CMD_SETGETDC getidcr - Get a register value via indirect DCR addressing setidcr - Set a register value via indirect DCR addressing +config CMD_ZYNQ_RSA + bool "Zynq RSA" + help + Verifies the authenticated and encrypted zynq images. + + config CMD_SOUND + bool "sound" + depends on SOUND + help + This provides basic access to the U-Boot's sound support. The main + feature is to play a beep. + + sound init - set up sound system + sound play - play a sound + + endmenu + + menu "Boot timing" + + config BOOTSTAGE + bool "Boot timing and reporting" + help + Enable recording of boot time while booting. To use it, insert + calls to bootstage_mark() with a suitable BOOTSTAGE_ID from + bootstage.h. Only a single entry is recorded for each ID. You can + give the entry a name with bootstage_mark_name(). You can also + record elapsed time in a particular stage using bootstage_start() + before starting and bootstage_accum() when finished. Bootstage will + add up all the accumated time and report it. + + Normally, IDs are defined in bootstage.h but a small number of + additional 'user' IDs can be used but passing BOOTSTAGE_ID_ALLOC + as the ID. + + Calls to show_boot_progress() wil also result in log entries but + these will not have names. + + config BOOTSTAGE_REPORT + bool "Display a detailed boot timing report before booting the OS" + depends on BOOTSTAGE + help + Enable output of a boot time report just before the OS is booted. + This shows how long it took U-Boot to go through each stage of the + boot process. The report looks something like this: + + Timer summary in microseconds: + Mark Elapsed Stage + 0 0 reset + 3,575,678 3,575,678 board_init_f start + 3,575,695 17 arch_cpu_init A9 + 3,575,777 82 arch_cpu_init done + 3,659,598 83,821 board_init_r start + 3,910,375 250,777 main_loop + 29,916,167 26,005,792 bootm_start + 30,361,327 445,160 start_kernel + + config BOOTSTAGE_USER_COUNT + hex "Number of boot ID numbers available for user use" + default 20 + help + This is the number of available user bootstage records. + Each time you call bootstage_mark(BOOTSTAGE_ID_ALLOC, ...) + a new ID will be allocated from this stash. If you exceed + the limit, recording will stop. + + config CMD_BOOTSTAGE + bool "Enable the 'bootstage' command" + depends on BOOTSTAGE + help + Add a 'bootstage' command which supports printing a report + and un/stashing of bootstage data. + + config BOOTSTAGE_FDT + bool "Store boot timing information in the OS device tree" + depends on BOOTSTAGE + help + Stash the bootstage information in the FDT. A root 'bootstage' + node is created with each bootstage id as a child. Each child + has a 'name' property and either 'mark' containing the + mark time in microsecond, or 'accum' containing the + accumulated time for that bootstage id in microseconds. + For example: + + bootstage { + 154 { + name = "board_init_f"; + mark = <3575678>; + }; + 170 { + name = "lcd"; + accum = <33482>; + }; + }; + + Code in the Linux kernel can find this in /proc/devicetree. + + config BOOTSTAGE_STASH + bool "Stash the boot timing information in memory before booting OS" + depends on BOOTSTAGE + help + Some OSes do not support device tree. Bootstage can instead write + the boot timing information in a binary format at a given address. + This happens through a call to bootstage_stash(), typically in + the CPU's cleanup_before_linux() function. You can use the + 'bootstage stash' and 'bootstage unstash' commands to do this on + the command line. + + config BOOTSTAGE_STASH_ADDR + hex "Address to stash boot timing information" + default 0 + help + Provide an address which will not be overwritten by the OS when it + starts, so that it can read this information when ready. + + config BOOTSTAGE_STASH_SIZE + hex "Size of boot timing stash region" + default 4096 + help + This should be large enough to hold the bootstage stash. A value of + 4096 (4KiB) is normally plenty. + + endmenu + + menu "Power commands" + config CMD_PMIC + bool "Enable Driver Model PMIC command" + depends on DM_PMIC + help + This is the pmic command, based on a driver model pmic's API. + Command features are unchanged: + - list - list pmic devices + - pmic dev - show or [set] operating pmic device (NEW) + - pmic dump - dump registers + - pmic read address - read byte of register at address + - pmic write address - write byte to register at address + The only one change for this command is 'dev' subcommand. + + config CMD_REGULATOR + bool "Enable Driver Model REGULATOR command" + depends on DM_REGULATOR + help + This command is based on driver model regulator's API. + User interface features: + - list - list regulator devices + - regulator dev - show or [set] operating regulator device + - regulator info - print constraints info + - regulator status - print operating status + - regulator value - print/[set] voltage value [uV] + - regulator current - print/[set] current value [uA] + - regulator mode - print/[set] operating mode id + - regulator enable - enable the regulator output + - regulator disable - disable the regulator output + + The '-f' (force) option can be used for set the value which exceeds + the limits, which are found in device-tree and are kept in regulator's + uclass platdata structure. + endmenu endmenu diff --cc common/spl/spl_mmc.c index 6fdc7a7f332,552f80d1e3d..259de7ba275 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@@ -141,51 -119,69 +151,74 @@@ void spl_mmc_load_image(void } boot_mode = spl_boot_mode(); - if (boot_mode == MMCSD_MODE_RAW) { - debug("boot mode - RAW\n"); + switch (boot_mode) { + case MMCSD_MODE_RAW: + debug("spl: mmc boot mode: raw\n"); + #ifdef CONFIG_SPL_OS_BOOT - if (spl_start_uboot() || mmc_load_image_raw_os(mmc)) + if (!spl_start_uboot()) { + err = mmc_load_image_raw_os(mmc); + if (!err) + return; + } #endif - #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION + #if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION) err = mmc_load_image_raw_partition(mmc, CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION); - #else + if (!err) + return; + #elif defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR) err = mmc_load_image_raw_sector(mmc, CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR); + if (!err) + return; #endif - #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) - } - if (err || boot_mode == MMCSD_MODE_FS) { - debug("boot mode - FS\n"); + case MMCSD_MODE_FS: + debug("spl: mmc boot mode: fs\n"); + + #ifdef CONFIG_SYS_MMCSD_FS_BOOT_PARTITION #ifdef CONFIG_SPL_FAT_SUPPORT + +#ifdef CONFIG_SPL_FPGA_SUPPORT + mmc_load_fpga_image_fat(mmc); +#endif + #ifdef CONFIG_SPL_OS_BOOT - if (spl_start_uboot() || spl_load_image_fat_os(&mmc->block_dev, - CONFIG_SYS_MMCSD_FS_BOOT_PARTITION)) + if (!spl_start_uboot()) { + err = spl_load_image_fat_os(&mmc->block_dev, + CONFIG_SYS_MMCSD_FS_BOOT_PARTITION); + if (!err) + return; + } #endif + #ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME err = spl_load_image_fat(&mmc->block_dev, - CONFIG_SYS_MMCSD_FS_BOOT_PARTITION, - CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); - if(err) - #endif /* CONFIG_SPL_FAT_SUPPORT */ - { + CONFIG_SYS_MMCSD_FS_BOOT_PARTITION, + CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); + if (!err) + return; + #endif + #endif #ifdef CONFIG_SPL_EXT_SUPPORT #ifdef CONFIG_SPL_OS_BOOT - if (spl_start_uboot() || spl_load_image_ext_os(&mmc->block_dev, - CONFIG_SYS_MMCSD_FS_BOOT_PARTITION)) + if (!spl_start_uboot()) { + err = spl_load_image_ext_os(&mmc->block_dev, + CONFIG_SYS_MMCSD_FS_BOOT_PARTITION); + if (!err) + return; + } #endif + #ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME err = spl_load_image_ext(&mmc->block_dev, - CONFIG_SYS_MMCSD_FS_BOOT_PARTITION, - CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); - #endif /* CONFIG_SPL_EXT_SUPPORT */ - } - #endif /* defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) */ + CONFIG_SYS_MMCSD_FS_BOOT_PARTITION, + CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); + if (!err) + return; + #endif + #endif + #endif #ifdef CONFIG_SUPPORT_EMMC_BOOT - } else if (boot_mode == MMCSD_MODE_EMMCBOOT) { + case MMCSD_MODE_EMMCBOOT: /* * We need to check what the partition is configured to. * 1 and 2 match up to boot0 / boot1 and 7 is user data diff --cc configs/xilinx_zynqmp_ep_defconfig index b3bb9f6281e,00000000000..12b567d13b7 mode 100644,000000..100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@@ -1,21 -1,0 +1,13 @@@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_ZYNQMP_QSPI=y +CONFIG_NAND_ARASAN=y - CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep" +CONFIG_SYS_TEXT_BASE=0x8000000 - CONFIG_CMD_BDI=y - CONFIG_CMD_BOOTD=y - CONFIG_CMD_RUN=y - CONFIG_CMD_IMI=y - CONFIG_CMD_SAVEENV=y - CONFIG_CMD_FLASH=y - CONFIG_CMD_ECHO=y - CONFIG_CMD_SOURCE=y - CONFIG_CMD_NET=y ++CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep" ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y - CONFIG_CMD_MISC=y +CONFIG_CMD_TIMER=y diff --cc configs/xilinx_zynqmp_mini_qspi_defconfig index f62f5c2f364,00000000000..fa3cd8091a3 mode 100644,000000..100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@@ -1,9 -1,0 +1,9 @@@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_TARGET_ZYNQMP_MINI=y +CONFIG_SECURE_IOU=y +CONFIG_ZYNQMP_QSPI=y ++CONFIG_SYS_TEXT_BASE=0xFFFC0000 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-flash" +CONFIG_SYS_EXTRA_OPTIONS="MINI_QSPI" - CONFIG_SYS_TEXT_BASE=0xFFFC0000 - CONFIG_CMD_RUN=y ++# CONFIG_CMD_IMLS is not set diff --cc configs/zynq_afx_nand_RSA_defconfig index ca45657923d,00000000000..2c1ece6fba2 mode 100644,000000..100644 --- a/configs/zynq_afx_nand_RSA_defconfig +++ b/configs/zynq_afx_nand_RSA_defconfig @@@ -1,11 -1,0 +1,11 @@@ - CONFIG_SPL=n - CONFIG_SYS_EXTRA_OPTIONS="AFX_NAND" +CONFIG_ARM=y - CONFIG_ZYNQ=y ++CONFIG_ARCH_ZYNQ=y +CONFIG_TARGET_ZYNQ_AFX=y - CONFIG_OF_CONTROL=n - CONFIG_CMD_ZYNQ_RSA=y ++CONFIG_DEFAULT_DEVICE_TREE="zynq-afx-nand" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y - CONFIG_DM=y ++CONFIG_SYS_EXTRA_OPTIONS="AFX_NAND" ++# CONFIG_CMD_IMLS is not set ++CONFIG_CMD_ZYNQ_RSA=y ++CONFIG_OF_EMBED=y diff --cc configs/zynq_afx_nand_defconfig index bfd1b1e9eef,00000000000..45e3759c4ff mode 100644,000000..100644 --- a/configs/zynq_afx_nand_defconfig +++ b/configs/zynq_afx_nand_defconfig @@@ -1,6 -1,0 +1,7 @@@ - CONFIG_SPL=n - CONFIG_SYS_EXTRA_OPTIONS="AFX_NAND" +CONFIG_ARM=y - CONFIG_ZYNQ=y ++CONFIG_ARCH_ZYNQ=y +CONFIG_TARGET_ZYNQ_AFX=y - CONFIG_OF_CONTROL=n ++CONFIG_DEFAULT_DEVICE_TREE="zynq-afx-nand" ++CONFIG_SYS_EXTRA_OPTIONS="AFX_NAND" ++# CONFIG_CMD_IMLS is not set ++CONFIG_OF_EMBED=y diff --cc configs/zynq_afx_nor_RSA_defconfig index 1e17adafe1a,00000000000..3000535eba4 mode 100644,000000..100644 --- a/configs/zynq_afx_nor_RSA_defconfig +++ b/configs/zynq_afx_nor_RSA_defconfig @@@ -1,11 -1,0 +1,10 @@@ - CONFIG_SPL=n - CONFIG_SYS_EXTRA_OPTIONS="AFX_NOR" +CONFIG_ARM=y - CONFIG_ZYNQ=y ++CONFIG_ARCH_ZYNQ=y +CONFIG_TARGET_ZYNQ_AFX=y - CONFIG_OF_CONTROL=n - CONFIG_CMD_ZYNQ_RSA=y ++CONFIG_DEFAULT_DEVICE_TREE="zynq-afx-nor" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y - CONFIG_DM=y ++CONFIG_SYS_EXTRA_OPTIONS="AFX_NOR" ++CONFIG_CMD_ZYNQ_RSA=y ++CONFIG_OF_EMBED=y diff --cc configs/zynq_afx_nor_defconfig index c61d614c015,00000000000..872f985b9b1 mode 100644,000000..100644 --- a/configs/zynq_afx_nor_defconfig +++ b/configs/zynq_afx_nor_defconfig @@@ -1,6 -1,0 +1,6 @@@ - CONFIG_SPL=n - CONFIG_SYS_EXTRA_OPTIONS="AFX_NOR" +CONFIG_ARM=y - CONFIG_ZYNQ=y ++CONFIG_ARCH_ZYNQ=y +CONFIG_TARGET_ZYNQ_AFX=y - CONFIG_OF_CONTROL=n ++CONFIG_DEFAULT_DEVICE_TREE="zynq-afx-nor" ++CONFIG_SYS_EXTRA_OPTIONS="AFX_NOR" ++CONFIG_OF_EMBED=y diff --cc configs/zynq_afx_qspi_RSA_defconfig index 9469fde658d,00000000000..1aee4769161 mode 100644,000000..100644 --- a/configs/zynq_afx_qspi_RSA_defconfig +++ b/configs/zynq_afx_qspi_RSA_defconfig @@@ -1,11 -1,0 +1,11 @@@ - CONFIG_SPL=n - CONFIG_SYS_EXTRA_OPTIONS="AFX_QSPI" +CONFIG_ARM=y - CONFIG_ZYNQ=y ++CONFIG_ARCH_ZYNQ=y +CONFIG_TARGET_ZYNQ_AFX=y - CONFIG_OF_CONTROL=n - CONFIG_CMD_ZYNQ_RSA=y ++CONFIG_DEFAULT_DEVICE_TREE="zynq-afx-qspi" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y - CONFIG_DM=y ++CONFIG_SYS_EXTRA_OPTIONS="AFX_QSPI" ++# CONFIG_CMD_IMLS is not set ++CONFIG_CMD_ZYNQ_RSA=y ++CONFIG_OF_EMBED=y diff --cc configs/zynq_afx_qspi_defconfig index 8c4c7e5290d,00000000000..7d9d4cfcbd9 mode 100644,000000..100644 --- a/configs/zynq_afx_qspi_defconfig +++ b/configs/zynq_afx_qspi_defconfig @@@ -1,6 -1,0 +1,7 @@@ - CONFIG_SPL=n - CONFIG_SYS_EXTRA_OPTIONS="AFX_QSPI" +CONFIG_ARM=y - CONFIG_ZYNQ=y ++CONFIG_ARCH_ZYNQ=y +CONFIG_TARGET_ZYNQ_AFX=y - CONFIG_OF_CONTROL=n ++CONFIG_DEFAULT_DEVICE_TREE="zynq-afx-qspi" ++CONFIG_SYS_EXTRA_OPTIONS="AFX_QSPI" ++# CONFIG_CMD_IMLS is not set ++CONFIG_OF_EMBED=y diff --cc configs/zynq_cc108_defconfig index 10abfdadffc,00000000000..badc792058e mode 100644,000000..100644 --- a/configs/zynq_cc108_defconfig +++ b/configs/zynq_cc108_defconfig @@@ -1,6 -1,0 +1,7 @@@ - CONFIG_SPL=y +CONFIG_ARM=y - CONFIG_ZYNQ=y ++CONFIG_ARCH_ZYNQ=y +CONFIG_TARGET_ZYNQ_CC108=y - CONFIG_OF_CONTROL=n +CONFIG_DEFAULT_DEVICE_TREE="zynq-cc108" ++CONFIG_SPL=y ++# CONFIG_CMD_IMLS is not set ++CONFIG_OF_EMBED=y diff --cc configs/zynq_cse_nand_defconfig index 9bcf5b80ac2,00000000000..5c32880bd34 mode 100644,000000..100644 --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@@ -1,7 -1,0 +1,9 @@@ - CONFIG_SPL=n - CONFIG_SYS_EXTRA_OPTIONS="CSE_NAND" +CONFIG_ARM=y - CONFIG_ZYNQ=y ++CONFIG_ARCH_ZYNQ=y +CONFIG_TARGET_ZYNQ_CSE=y - CONFIG_CMD_BOOTM=n - CONFIG_CMD_GO=n ++CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nand" ++CONFIG_SYS_EXTRA_OPTIONS="CSE_NAND" ++# CONFIG_CMD_BOOTD is not set ++# CONFIG_CMD_BOOTM is not set ++# CONFIG_CMD_GO is not set ++CONFIG_OF_EMBED=y diff --cc configs/zynq_cse_nor_defconfig index 4abb34f3e22,00000000000..24cfead80b0 mode 100644,000000..100644 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@@ -1,7 -1,0 +1,9 @@@ - CONFIG_SPL=n - CONFIG_SYS_EXTRA_OPTIONS="CSE_NOR" +CONFIG_ARM=y - CONFIG_ZYNQ=y ++CONFIG_ARCH_ZYNQ=y +CONFIG_TARGET_ZYNQ_CSE=y - CONFIG_CMD_BOOTM=n - CONFIG_CMD_GO=n ++CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nor" ++CONFIG_SYS_EXTRA_OPTIONS="CSE_NOR" ++# CONFIG_CMD_BOOTD is not set ++# CONFIG_CMD_BOOTM is not set ++# CONFIG_CMD_GO is not set ++CONFIG_OF_EMBED=y diff --cc configs/zynq_cse_qspi_defconfig index 41404341123,00000000000..3957a671c7d mode 100644,000000..100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@@ -1,7 -1,0 +1,9 @@@ - CONFIG_SPL=n - CONFIG_SYS_EXTRA_OPTIONS="CSE_QSPI" +CONFIG_ARM=y - CONFIG_ZYNQ=y ++CONFIG_ARCH_ZYNQ=y +CONFIG_TARGET_ZYNQ_CSE=y - CONFIG_CMD_BOOTM=n - CONFIG_CMD_GO=n ++CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi" ++CONFIG_SYS_EXTRA_OPTIONS="CSE_QSPI" ++# CONFIG_CMD_BOOTD is not set ++# CONFIG_CMD_BOOTM is not set ++# CONFIG_CMD_GO is not set ++CONFIG_OF_EMBED=y diff --cc configs/zynq_microzed_defconfig index 04d83bdf901,c878924c70d..129faf4f2cd --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@@ -7,5 -7,6 +7,7 @@@ CONFIG_SPL= CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y - CONFIG_DM=y - CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed" + # CONFIG_CMD_IMLS is not set + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_SETEXPR is not set ++CONFIG_OF_EMBED=y diff --cc configs/zynq_picozed_defconfig index 00000000000,af77a9d9d34..62be59be22c mode 000000,100644..100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@@ -1,0 -1,8 +1,9 @@@ + CONFIG_ARM=y + CONFIG_ARCH_ZYNQ=y + CONFIG_TARGET_ZYNQ_PICOZED=y + CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed" + CONFIG_SPL=y + # CONFIG_CMD_IMLS is not set + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_SETEXPR is not set ++CONFIG_OF_EMBED=y diff --cc configs/zynq_zc702_defconfig index 00000000000,5dde452cc39..936eec27f55 mode 000000,100644..100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@@ -1,0 -1,12 +1,13 @@@ + CONFIG_ARM=y + CONFIG_ARCH_ZYNQ=y + CONFIG_TARGET_ZYNQ_ZC702=y + CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702" + # CONFIG_SYS_MALLOC_F is not set + CONFIG_SPL=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_FIT_SIGNATURE=y + # CONFIG_CMD_IMLS is not set + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_SETEXPR is not set ++CONFIG_OF_EMBED=y diff --cc configs/zynq_zc706_defconfig index 00000000000,0f96d16c080..db11e6fe5b2 mode 000000,100644..100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@@ -1,0 -1,12 +1,13 @@@ + CONFIG_ARM=y + CONFIG_ARCH_ZYNQ=y + CONFIG_TARGET_ZYNQ_ZC706=y + CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706" + # CONFIG_SYS_MALLOC_F is not set + CONFIG_SPL=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_FIT_SIGNATURE=y + # CONFIG_CMD_IMLS is not set + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_SETEXPR is not set ++CONFIG_OF_EMBED=y diff --cc configs/zynq_zc70x_RSA_defconfig index f664919531d,00000000000..25813d2a1e0 mode 100644,000000..100644 --- a/configs/zynq_zc70x_RSA_defconfig +++ b/configs/zynq_zc70x_RSA_defconfig @@@ -1,11 -1,0 +1,14 @@@ - CONFIG_SPL=y +CONFIG_ARM=y - CONFIG_ZYNQ=y ++CONFIG_ARCH_ZYNQ=y +CONFIG_TARGET_ZYNQ_ZC70X=y - CONFIG_OF_CONTROL=n +CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702" - CONFIG_CMD_ZYNQ_RSA=y ++# CONFIG_SYS_MALLOC_F is not set ++CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y - CONFIG_DM=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_ZYNQ_RSA=y ++CONFIG_OF_EMBED=y diff --cc configs/zynq_zc70x_defconfig index a3bf56537ac,525c538b983..abb02b1349f --- a/configs/zynq_zc70x_defconfig +++ b/configs/zynq_zc70x_defconfig @@@ -8,4 -7,6 +7,7 @@@ CONFIG_SPL= CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y - CONFIG_DM=y + # CONFIG_CMD_IMLS is not set + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_SETEXPR is not set ++CONFIG_OF_EMBED=y diff --cc configs/zynq_zc770_xm010_RSA_defconfig index a03578b332e,00000000000..db64432ddbb mode 100644,000000..100644 --- a/configs/zynq_zc770_xm010_RSA_defconfig +++ b/configs/zynq_zc770_xm010_RSA_defconfig @@@ -1,12 -1,0 +1,15 @@@ - CONFIG_SPL=n - CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010" +CONFIG_ARM=y - CONFIG_ZYNQ=y ++CONFIG_ARCH_ZYNQ=y +CONFIG_TARGET_ZYNQ_ZC770=y - CONFIG_OF_CONTROL=n +CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010" - CONFIG_CMD_ZYNQ_RSA=y ++# CONFIG_SYS_MALLOC_F is not set ++CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y - CONFIG_DM=y ++CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010" ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_ZYNQ_RSA=y ++CONFIG_OF_EMBED=y diff --cc configs/zynq_zc770_xm010_defconfig index d9c9053214d,f1fc2830360..52511a759ae --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@@ -9,4 -7,8 +7,9 @@@ CONFIG_SPL= CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y - CONFIG_DM=y + CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010" + # CONFIG_CMD_IMLS is not set + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_SETEXPR is not set ++CONFIG_OF_EMBED=y + CONFIG_SPI_FLASH=y diff --cc configs/zynq_zc770_xm011_RSA_defconfig index 587cec8e567,00000000000..c82f0f30ce1 mode 100644,000000..100644 --- a/configs/zynq_zc770_xm011_RSA_defconfig +++ b/configs/zynq_zc770_xm011_RSA_defconfig @@@ -1,12 -1,0 +1,11 @@@ - CONFIG_SPL=n - CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011" +CONFIG_ARM=y - CONFIG_ZYNQ=y ++CONFIG_ARCH_ZYNQ=y +CONFIG_TARGET_ZYNQ_ZC770=y - CONFIG_OF_CONTROL=n +CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011" - CONFIG_CMD_ZYNQ_RSA=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y - CONFIG_DM=y ++CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011" ++# CONFIG_CMD_IMLS is not set ++CONFIG_CMD_ZYNQ_RSA=y ++CONFIG_OF_EMBED=y diff --cc configs/zynq_zc770_xm011_defconfig index dea6e50e4f2,00000000000..ab7d6c50cd2 mode 100644,000000..100644 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@@ -1,7 -1,0 +1,5 @@@ - CONFIG_SPL=n - CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011" +CONFIG_ARM=y - CONFIG_ZYNQ=y - CONFIG_TARGET_ZYNQ_ZC770=y - CONFIG_OF_CONTROL=n +CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011" ++CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011" ++CONFIG_OF_CONTROL=y ++CONFIG_OF_EMBED=y diff --cc configs/zynq_zc770_xm012_RSA_defconfig index 4e45ae37107,00000000000..b5fb79c4267 mode 100644,000000..100644 --- a/configs/zynq_zc770_xm012_RSA_defconfig +++ b/configs/zynq_zc770_xm012_RSA_defconfig @@@ -1,12 -1,0 +1,14 @@@ - CONFIG_SPL=n - CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012" +CONFIG_ARM=y - CONFIG_ZYNQ=y ++CONFIG_ARCH_ZYNQ=y +CONFIG_TARGET_ZYNQ_ZC770=y - CONFIG_OF_CONTROL=n +CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012" - CONFIG_CMD_ZYNQ_RSA=y ++# CONFIG_SYS_MALLOC_F is not set ++CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y - CONFIG_DM=y ++CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012" ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_ZYNQ_RSA=y ++CONFIG_OF_EMBED=y diff --cc configs/zynq_zc770_xm012_defconfig index 3c0022b3cec,73ed13d9be8..4361bf78758 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@@ -9,4 -7,5 +7,6 @@@ CONFIG_SPL= CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y - CONFIG_DM=y + CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012" + # CONFIG_CMD_SETEXPR is not set ++CONFIG_OF_EMBED=y diff --cc configs/zynq_zc770_xm013_RSA_defconfig index 3df4254f310,00000000000..6dbe02a894c mode 100644,000000..100644 --- a/configs/zynq_zc770_xm013_RSA_defconfig +++ b/configs/zynq_zc770_xm013_RSA_defconfig @@@ -1,12 -1,0 +1,15 @@@ - CONFIG_SPL=n - CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013" +CONFIG_ARM=y - CONFIG_ZYNQ=y ++CONFIG_ARCH_ZYNQ=y +CONFIG_TARGET_ZYNQ_ZC770=y - CONFIG_OF_CONTROL=n +CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013" - CONFIG_CMD_ZYNQ_RSA=y ++# CONFIG_SYS_MALLOC_F is not set ++CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y - CONFIG_DM=y ++CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013" ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_ZYNQ_RSA=y ++CONFIG_OF_EMBED=y diff --cc configs/zynq_zc770_xm013_defconfig index c89010d41b7,211a41d91a5..8f10d325a50 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@@ -9,4 -7,7 +7,8 @@@ CONFIG_SPL= CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y - CONFIG_DM=y + CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013" + # CONFIG_CMD_IMLS is not set + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_SETEXPR is not set ++CONFIG_OF_EMBED=y diff --cc configs/zynq_zed_RSA_defconfig index 3261baa0f84,00000000000..4fe5df94ca9 mode 100644,000000..100644 --- a/configs/zynq_zed_RSA_defconfig +++ b/configs/zynq_zed_RSA_defconfig @@@ -1,11 -1,0 +1,14 @@@ - CONFIG_SPL=y +CONFIG_ARM=y - CONFIG_ZYNQ=y ++CONFIG_ARCH_ZYNQ=y +CONFIG_TARGET_ZYNQ_ZED=y - CONFIG_OF_CONTROL=n +CONFIG_DEFAULT_DEVICE_TREE="zynq-zed" - CONFIG_CMD_ZYNQ_RSA=y ++# CONFIG_SYS_MALLOC_F is not set ++CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y - CONFIG_DM=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_ZYNQ_RSA=y ++CONFIG_OF_EMBED=y diff --cc configs/zynq_zed_defconfig index 138d5ec06c1,f3c63f9560b..44885a17fe3 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@@ -8,4 -7,6 +7,7 @@@ CONFIG_SPL= CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y - CONFIG_DM=y + # CONFIG_CMD_IMLS is not set + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_SETEXPR is not set ++CONFIG_OF_EMBED=y diff --cc configs/zynq_zybo_defconfig index 6aac41e9425,0c6117d68e7..7779836e541 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@@ -8,4 -7,6 +7,7 @@@ CONFIG_SPL= CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y - CONFIG_DM=y + # CONFIG_CMD_IMLS is not set + # CONFIG_CMD_FLASH is not set + # CONFIG_CMD_SETEXPR is not set ++CONFIG_OF_EMBED=y diff --cc drivers/mtd/spi/sf_probe.c index cab985c9895,e0283dc82cd..5377c2f623d --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@@ -439,11 -303,7 +418,11 @@@ int spi_flash_decode_fdt(const void *bl */ int spi_flash_probe_slave(struct spi_slave *spi, struct spi_flash *flash) { - u8 idcode[5]; + u8 idcode[6]; +#ifdef CONFIG_SPI_GENERIC - u8 idcode_up[5]; ++ u8 idcode_up[6]; + u8 i; +#endif int ret; /* Setup spi_slave */ diff --cc drivers/net/Makefile index 9e022388d25,150470c24b0..01dada68150 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@@ -63,7 -65,10 +65,9 @@@ obj-$(CONFIG_ULI526X) += uli526x. obj-$(CONFIG_VSC7385_ENET) += vsc7385.o obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o -obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \ - xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o +obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/ + obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/ + obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o obj-$(CONFIG_VSC9953) += vsc9953.o diff --cc drivers/net/xilinx_emaclite.c index dbda9e6f245,c9afa996908..ae614305ad2 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@@ -499,12 -317,12 +499,12 @@@ static int emaclite_recv(struct eth_dev etherrxbuff, length); /* Acknowledge the frame */ - reg = in_be32 (baseaddress + XEL_RSR_OFFSET); + reg = in_be32 ((u32 *)(baseaddress + XEL_RSR_OFFSET)); reg &= ~XEL_RSR_RECV_DONE_MASK; - out_be32 (baseaddress + XEL_RSR_OFFSET, reg); + out_be32 ((u32 *)(baseaddress + XEL_RSR_OFFSET), reg); debug("Packet receive from 0x%x, length %dB\n", baseaddress, length); - NetReceive((uchar *) etherrxbuff, length); + net_process_received_packet((uchar *)etherrxbuff, length); return length; } diff --cc drivers/net/zynq_gem.c index 37a7aeca69c,c723dbb0a69..caaf1a3b0e5 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@@ -387,14 -375,6 +387,14 @@@ static int zynq_gem_init(struct eth_dev zynq_slcr_gem_clk_setup(dev->iobase != ZYNQ_GEM_BASEADDR0, clk_rate); + /* set hardware address because of ... */ - if (!is_valid_ether_addr(dev->enetaddr)) { ++ if (!is_valid_ethaddr(dev->enetaddr)) { + printf("%s: mac address is not valid\n", dev->name); + return -1; + } + + zynq_gem_setup_mac(dev); + setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK); @@@ -462,8 -436,10 +462,8 @@@ static int zynq_gem_recv(struct eth_dev if (frame_len) { u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; addr &= ~(ARCH_DMA_MINALIGN - 1); - u32 size = roundup(frame_len, ARCH_DMA_MINALIGN); - invalidate_dcache_range(addr, addr + size); - NetReceive((u8 *)addr, frame_len); + net_process_received_packet((u8 *)addr, frame_len); if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) priv->rx_first_buf = priv->rxbd_current; diff --cc drivers/spi/Makefile index ace9c464beb,ee88aa162bc..1866d344fad --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@@ -48,7 -48,3 +48,5 @@@ obj-$(CONFIG_TEGRA20_SLINK) += tegra20_ obj-$(CONFIG_TI_QSPI) += ti_qspi.o obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o +obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o +obj-$(CONFIG_ZYNQMP_QSPI) += zynqmp_qspi.o - obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o diff --cc drivers/spi/zynq_spi.c index e9129da79d9,c5c3e1044fd..0208afc4a63 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@@ -275,3 -242,84 +242,84 @@@ static int zynq_spi_xfer(struct udevic return 0; } + + static int zynq_spi_set_speed(struct udevice *bus, uint speed) + { + struct zynq_spi_platdata *plat = bus->platdata; + struct zynq_spi_priv *priv = dev_get_priv(bus); + struct zynq_spi_regs *regs = priv->regs; + uint32_t confr; + u8 baud_rate_val = 0; + + if (speed > plat->frequency) + speed = plat->frequency; + + /* Set the clock frequency */ + confr = readl(®s->cr); + if (speed == 0) { + /* Set baudrate x8, if the freq is 0 */ + baud_rate_val = 0x2; + } else if (plat->speed_hz != speed) { + while ((baud_rate_val < 8) && + ((plat->frequency / + (2 << baud_rate_val)) > speed)) + baud_rate_val++; + plat->speed_hz = speed / (2 << baud_rate_val); + } + confr &= ~ZYNQ_SPI_CR_BRD_MASK; + confr |= (baud_rate_val << 3); + + writel(confr, ®s->cr); + priv->freq = speed; + + debug("zynq_spi_set_speed: regs=%p, mode=%d\n", priv->regs, priv->freq); + + return 0; + } + + static int zynq_spi_set_mode(struct udevice *bus, uint mode) + { + struct zynq_spi_priv *priv = dev_get_priv(bus); + struct zynq_spi_regs *regs = priv->regs; + uint32_t confr; + + /* Set the SPI Clock phase and polarities */ + confr = readl(®s->cr); + confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK); + + if (priv->mode & SPI_CPHA) + confr |= ZYNQ_SPI_CR_CPHA_MASK; + if (priv->mode & SPI_CPOL) + confr |= ZYNQ_SPI_CR_CPOL_MASK; + + writel(confr, ®s->cr); + priv->mode = mode; + + debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode); + + return 0; + } + + static const struct dm_spi_ops zynq_spi_ops = { + .claim_bus = zynq_spi_claim_bus, + .release_bus = zynq_spi_release_bus, + .xfer = zynq_spi_xfer, + .set_speed = zynq_spi_set_speed, + .set_mode = zynq_spi_set_mode, + }; + + static const struct udevice_id zynq_spi_ids[] = { - { .compatible = "xlnx,zynq-spi" }, ++ { .compatible = "xlnx,zynq-spi-r1p6" }, + { } + }; + + U_BOOT_DRIVER(zynq_spi) = { + .name = "zynq_spi", + .id = UCLASS_SPI, + .of_match = zynq_spi_ids, + .ops = &zynq_spi_ops, + .ofdata_to_platdata = zynq_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct zynq_spi_platdata), + .priv_auto_alloc_size = sizeof(struct zynq_spi_priv), + .probe = zynq_spi_probe, + }; diff --cc fs/fat/fat.c index e22df5405ca,bccc3e3ed8f..8ac73c40735 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@@ -319,15 -319,8 +319,15 @@@ get_cluster(fsdata *mydata, __u32 clust * into 'buffer'. * Update the number of bytes read in *gotsize or return -1 on fatal errors. */ +#ifndef CONFIG_ZYNQ_OCM - #if defined(CONFIG_ZYNQ) && defined(CONFIG_SPL_BUILD) ++#if defined(CONFIG_ARCH_ZYNQ) && defined(CONFIG_SPL_BUILD) +__section(.ddr) +#endif __u8 get_contents_vfatname_block[MAX_CLUSTSIZE] __aligned(ARCH_DMA_MINALIGN); +#else +__u8 *get_contents_vfatname_block = (__u8 *)FAT_BUFF_PTR_OCM; +#endif static int get_contents(fsdata *mydata, dir_entry *dentptr, loff_t pos, __u8 *buffer, loff_t maxsize, loff_t *gotsize) @@@ -578,13 -571,8 +578,13 @@@ static __u8 mkcksum(const char name[8] * Get the directory entry associated with 'filename' from the directory * starting at 'startsect' */ +#ifndef CONFIG_ZYNQ_OCM - #if defined(CONFIG_ZYNQ) && defined(CONFIG_SPL_BUILD) ++#if defined(CONFIG_ARCH_ZYNQ) && defined(CONFIG_SPL_BUILD) +__section(.ddr) +#endif __u8 get_dentfromdir_block[MAX_CLUSTSIZE] __aligned(ARCH_DMA_MINALIGN); +#endif static dir_entry *get_dentfromdir(fsdata *mydata, int startsect, char *filename, dir_entry *retdent, @@@ -819,13 -803,8 +819,13 @@@ exit return ret; } +#ifndef CONFIG_ZYNQ_OCM - #if defined(CONFIG_ZYNQ) && defined(CONFIG_SPL_BUILD) ++#if defined(CONFIG_ARCH_ZYNQ) && defined(CONFIG_SPL_BUILD) +__section(.ddr) +#endif __u8 do_fat_read_at_block[MAX_CLUSTSIZE] __aligned(ARCH_DMA_MINALIGN); +#endif int do_fat_read_at(const char *filename, loff_t pos, void *buffer, loff_t maxsize, int dols, int dogetsize, loff_t *size) diff --cc include/config_cmd_all.h index 9e62af27e14,4c46ddad2b5..c1e85a34d48 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@@ -94,9 -73,6 +73,8 @@@ #define CONFIG_CMD_UNIVERSE /* Tundra Universe Support */ #define CONFIG_CMD_UNZIP /* unzip from memory to memory */ #define CONFIG_CMD_USB /* USB Support */ - #define CONFIG_CMD_XIMG /* Load part of Multi Image */ #define CONFIG_CMD_ZFS /* ZFS Support */ +#define CONFIG_CMD_ZYNQ_AES /* AES support for Zynq */ +#define CONFIG_CMD_ZYNQ_RSA /* RSA-AES support for Zynq */ #endif /* _CONFIG_CMD_ALL_H */ diff --cc include/configs/xilinx-ppc405-generic.h index bb14c4cfcc9,75b119f8556..f7aa182062a --- a/include/configs/xilinx-ppc405-generic.h +++ b/include/configs/xilinx-ppc405-generic.h @@@ -11,269 -14,29 +11,267 @@@ #include "../board/xilinx/ppc405-generic/xparameters.h" -/* sdram */ -#define CONFIG_SYS_SDRAM_SIZE_MB 256 - -/* environment */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_SYS_ENV_OFFSET 0x3F0000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET) -#define CONFIG_ENV_OVERWRITE 1 - -/*Misc*/ -#define CONFIG_SYS_PROMPT "xlx-ppc405:/# " /* Monitor Command Prompt */ -#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" - -/*Flash*/ -#define CONFIG_SYS_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR -#define CONFIG_SYS_FLASH_SIZE (32*1024*1024) -#define CONFIG_SYS_MAX_FLASH_SECT 71 -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define MTDIDS_DEFAULT "nor0=ppc405-flash" -#define MTDPARTS_DEFAULT "mtdpartsa=ppc405-flash:-(user)" - -#include -#endif /* __CONFIG_H */ +/* cpu parameter */ +#define CONFIG_405 1 +#define CONFIG_4xx 1 +#define CONFIG_XILINX_405 1 + +/* PPC-specific memory layout */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (192 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + +/*Stack*/ +#define CONFIG_SYS_INIT_RAM_ADDR 0x800000/* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ + - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/*Speed*/ +#define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ + +/* Common PPC-specific settings */ +#define CONFIG_SYS_MEMTEST_START 0x00400000 + /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00C00000 + /* 4 ... 12 MB in DRAM */ +#define CONFIG_SYS_EXTBDINFO 1 + /* Extended board_into (bd_t) */ +#define CONFIG_SYS_HZ 1000 + /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + /* Initial Memory map for Linux */ + +/* The following table includes the supported baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/* use serial multi for all serial devices */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + +#ifdef XILINX_UARTLITE_BASEADDR +# define CONFIG_XILINX_UARTLITE +# if defined(XILINX_UARTLITE_BAUDRATE) +# define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE +# endif +#endif + +#if XILINX_UART16550_BASEADDR +# define CONFIG_SYS_NS16550 1 +# define CONFIG_SYS_NS16550_SERIAL +# define CONFIG_SYS_NS16550_COM1 ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000) +# define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ + +# if defined(__MICROBLAZEEL__) +# define CONFIG_SYS_NS16550_REG_SIZE -4 +# else +# define CONFIG_SYS_NS16550_REG_SIZE 4 +# endif + +/* CONS_INDEX for system with uartlite only mustn't define CONFIG_CONS_INDEX + * u-boot BSP generates CONFIG_CONS_INDEX for system with several uart16550 */ +# if !defined(CONFIG_CONS_INDEX) +# define CONFIG_CONS_INDEX 1 +# endif +#endif + +#if !defined(CONFIG_BAUDRATE) + #define CONFIG_BAUDRATE 115200 +#endif + +#undef CONFIG_SYS_ENET +#if defined(XILINX_EMACLITE_BASEADDR) + #define CONFIG_XILINX_EMACLITE 1 + #define CONFIG_SYS_ENET +#endif +#if defined(XILINX_LLTEMAC_BASEADDR) + #define CONFIG_XILINX_LL_TEMAC 1 + #define CONFIG_SYS_ENET +#endif + +#undef ET_DEBUG + + +/* interrupt controller */ +#ifdef XILINX_INTC_BASEADDR + #define CONFIG_SYS_INTC_0 1 + #define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR + #define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS +#endif + +/* timer */ +#ifdef XILINX_TIMER_BASEADDR + #if (XILINX_TIMER_IRQ != -1) + #define CONFIG_SYS_TIMER_0 1 + #define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR + #define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ + #define FREQUENCE XILINX_CLOCK_FREQ + #define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 ) + #endif +#else +# error Please setup TIMER in BSP +#endif + +/* + * memory layout - Example + * TEXT_BASE = 0x1200_0000; + * CONFIG_SYS_SRAM_BASE = 0x1000_0000; + * CONFIG_SYS_SRAM_SIZE = 0x0400_0000; + * + * CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000 + * CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000 + * CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000 + * + * 0x1000_0000 CONFIG_SYS_SDRAM_BASE + * FREE + * 0x1200_0000 TEXT_BASE + * U-BOOT code + * 0x1202_0000 + * FREE + * + * STACK + * 0x13F7_F000 CONFIG_SYS_MALLOC_BASE + * MALLOC_AREA 256kB Alloc + * 0x11FB_F000 CONFIG_SYS_MONITOR_BASE + * MONITOR_CODE 256kB Env + * 0x13FF_F000 CONFIG_SYS_GBL_DATA_OFFSET + * GLOBAL_DATA 4kB bd, gd + * 0x1400_0000 CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE + */ + +/* ddr sdram - main memory */ +#define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START +#define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE + +#if defined(XILINX_FLASH_START) /* Parallel Flash */ + #define FLASH + #define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START + #define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE + #define CONFIG_SYS_FLASH_CFI 1 + #define CONFIG_FLASH_CFI_DRIVER 1 + #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* ?empty sector */ + #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ + #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ + + /* Assume env is in flash, this may be undone lower down */ + #define CONFIG_ENV_IS_IN_FLASH 1 + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + + #define CONFIG_SYS_FLASH_PROTECTION + + #define CONFIG_ENV_ADDR XILINX_FLASH_START + #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#else /* No flash memory at all */ + /* ENV in RAM */ + #define RAMENV + #define CONFIG_SYS_NO_FLASH 1 + + #define CONFIG_ENV_IS_NOWHERE 1 + #undef CONFIG_ENV_IS_IN_FLASH + #undef CONFIG_ENV_IS_IN_SPI_FLASH + #define CONFIG_ENV_SIZE 0x1000 + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) + #define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */ +#endif + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ - #include - +#define CONFIG_CMD_ASKENV +/* FIXME: hack for zynq */ +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ECHO + +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_JFFS2 +#ifndef CONFIG_SYS_ENET + #undef CONFIG_CMD_NET + #undef CONFIG_NET_MULTI +#else + #define CONFIG_CMD_PING + #define CONFIG_NET_MULTI +#endif + +#if defined(FLASH) + #define CONFIG_CMD_FLASH + #define CONFIG_CMD_IMLS +#else + #undef CONFIG_CMD_IMLS + #undef CONFIG_CMD_FLASH + #undef CONFIG_CMD_SAVEENV + #undef CONFIG_CMD_SAVES +#endif + +#if !defined(RAMENV) + #define CONFIG_CMD_SAVEENV + #define CONFIG_CMD_SAVES +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256/* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +\ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot Argument Buffer Size */ +#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START /* default load address */ + +#define CONFIG_BOOTDELAY 4 +/* Don't define BOOTARGS, we get it from the DTB chosen fragment */ +#undef CONFIG_BOOTARGS +#define CONFIG_HOSTNAME XILINX_BOARD_NAME + +#define CONFIG_BOOTCOMMAND "" + +/* architecture dependent code */ +#define CONFIG_SYS_USR_EXCEP /* user exception */ +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_ENV_OVERWRITE /* Allow to overwrite the u-boot environment variables */ +#define CONFIG_IPADDR 192.168.10.90 +#define CONFIG_SERVERIP 192.168.10.101 +#define CONFIG_ETHADDR 00:0a:35:00:92:d4 +#define CONFIG_BOOTP_SERVERIP + +#define CONFIG_CMDLINE_EDITING + +/* Use the HUSH parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 + +#if defined(CONFIG_XILINX_LL_TEMAC) +# define CONFIG_MII 1 +# define CONFIG_CMD_MII 1 +# define CONFIG_PHY_GIGE 1 +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 +# define CONFIG_PHYLIB 1 +# define CONFIG_PHY_ATHEROS 1 +# define CONFIG_PHY_BROADCOM 1 +# define CONFIG_PHY_DAVICOM 1 +# define CONFIG_PHY_LXT 1 +# define CONFIG_PHY_MARVELL 1 +# define CONFIG_PHY_MICREL 1 +# define CONFIG_PHY_NATSEMI 1 +# define CONFIG_PHY_REALTEK 1 +# define CONFIG_PHY_VITESSE 1 +#else +# undef CONFIG_MII +# undef CONFIG_CMD_MII +# undef CONFIG_PHYLIB +#endif + +#endif /* __CONFIG_H */ diff --cc include/configs/xilinx-ppc440-generic.h index a224241b55f,8e684151efe..7799ae49abd --- a/include/configs/xilinx-ppc440-generic.h +++ b/include/configs/xilinx-ppc440-generic.h @@@ -9,276 -8,32 +9,274 @@@ #ifndef __CONFIG_H #define __CONFIG_H -/*CPU*/ -#define CONFIG_440 1 -#define CONFIG_XILINX_PPC440_GENERIC 1 #include "../board/xilinx/ppc440-generic/xparameters.h" -/*Mem Map*/ -#define CONFIG_SYS_SDRAM_SIZE_MB 256 +/* cpu parameter */ +#define CONFIG_4xx 1 +#define CONFIG_440 1 +#define CONFIG_XILINX_440 1 +#define CONFIG_XILINX_440_GENERIC 1 -/*Env*/ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OFFSET 0x340000 -#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET) +/* Gross XPAR_ hackery */ +#define XPAR_INTC_0_BASEADDR XILINX_INTC_BASEADDR +#define XPAR_INTC_MAX_NUM_INTR_INPUTS XILINX_INTC_NUM_INTR_INPUTS -/*Misc*/ -#define CONFIG_SYS_PROMPT "board:/# " /* Monitor Command Prompt */ -#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" +/* PPC-specific memory layout */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) -/*Flash*/ -#define CONFIG_SYS_FLASH_SIZE (32*1024*1024) -#define CONFIG_SYS_MAX_FLASH_SECT 259 -#define MTDIDS_DEFAULT "nor0=ml507-flash" -#define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)" +/*Stack*/ +#define CONFIG_SYS_INIT_RAM_ADDR 0x800000/* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ + - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -/*Generic Configs*/ -#include +/*Speed*/ +#define CONFIG_SYS_CLK_FREQ XILINX_CLOCK_FREQ -#endif /* __CONFIG_H */ +/* Common PPC-specific settings */ +#define CONFIG_SYS_MEMTEST_START 0x00400000 + /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00C00000 + /* 4 ... 12 MB in DRAM */ +#define CONFIG_SYS_EXTBDINFO 1 + /* Extended board_into (bd_t) */ +#define CONFIG_SYS_HZ 1000 + /* decrementer freq: 1 ms ticks */ + +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) + /* Initial Memory map for Linux */ + +/* The following table includes the supported baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/* use serial multi for all serial devices */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + +#ifdef XILINX_UARTLITE_BASEADDR +# define CONFIG_XILINX_UARTLITE +# if defined(XILINX_UARTLITE_BAUDRATE) +# define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE +# endif +#endif + +#if XILINX_UART16550_BASEADDR +# define CONFIG_SYS_NS16550 1 +# define CONFIG_SYS_NS16550_SERIAL +# define CONFIG_SYS_NS16550_COM1 ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000) +# define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ + +# if defined(__MICROBLAZEEL__) +# define CONFIG_SYS_NS16550_REG_SIZE -4 +# else +# define CONFIG_SYS_NS16550_REG_SIZE 4 +# endif + +/* CONS_INDEX for system with uartlite only mustn't define CONFIG_CONS_INDEX + * u-boot BSP generates CONFIG_CONS_INDEX for system with several uart16550 */ +# if !defined(CONFIG_CONS_INDEX) +# define CONFIG_CONS_INDEX 1 +# endif +#endif + +#if !defined(CONFIG_BAUDRATE) + #define CONFIG_BAUDRATE 115200 +#endif + +#undef CONFIG_SYS_ENET +#if defined(XILINX_EMACLITE_BASEADDR) + #define CONFIG_XILINX_EMACLITE 1 + #define CONFIG_SYS_ENET +#endif +#if defined(XILINX_LLTEMAC_BASEADDR) + #define CONFIG_XILINX_LL_TEMAC 1 + #define CONFIG_SYS_ENET +#endif + +#undef ET_DEBUG + + +/* interrupt controller */ +#ifdef XILINX_INTC_BASEADDR + #define CONFIG_SYS_INTC_0 1 + #define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR + #define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS +#endif + +/* timer */ +#ifdef XILINX_TIMER_BASEADDR + #if (XILINX_TIMER_IRQ != -1) + #define CONFIG_SYS_TIMER_0 1 + #define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR + #define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ + #define FREQUENCE XILINX_CLOCK_FREQ + #define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 ) + #endif +#else +# error Please setup TIMER in BSP +#endif + +/* + * memory layout - Example + * TEXT_BASE = 0x1200_0000; + * CONFIG_SYS_SRAM_BASE = 0x1000_0000; + * CONFIG_SYS_SRAM_SIZE = 0x0400_0000; + * + * CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000 + * CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000 + * CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000 + * + * 0x1000_0000 CONFIG_SYS_SDRAM_BASE + * FREE + * 0x1200_0000 TEXT_BASE + * U-BOOT code + * 0x1202_0000 + * FREE + * + * STACK + * 0x13F7_F000 CONFIG_SYS_MALLOC_BASE + * MALLOC_AREA 256kB Alloc + * 0x11FB_F000 CONFIG_SYS_MONITOR_BASE + * MONITOR_CODE 256kB Env + * 0x13FF_F000 CONFIG_SYS_GBL_DATA_OFFSET + * GLOBAL_DATA 4kB bd, gd + * 0x1400_0000 CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE + */ + +/* ddr sdram - main memory */ +#define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START +#define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE + +#if defined(XILINX_FLASH_START) /* Parallel Flash */ + #define FLASH + #define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START + #define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE + #define CONFIG_SYS_FLASH_CFI 1 + #define CONFIG_FLASH_CFI_DRIVER 1 + #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* ?empty sector */ + #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ + #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ + + /* Assume env is in flash, this may be undone lower down */ + #define CONFIG_ENV_IS_IN_FLASH 1 + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + + #define CONFIG_SYS_FLASH_PROTECTION + + #define CONFIG_ENV_ADDR XILINX_FLASH_START + #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#else /* No flash memory at all */ + /* ENV in RAM */ + #define RAMENV + #define CONFIG_SYS_NO_FLASH 1 + + #define CONFIG_ENV_IS_NOWHERE 1 + #undef CONFIG_ENV_IS_IN_FLASH + #undef CONFIG_ENV_IS_IN_SPI_FLASH + #define CONFIG_ENV_SIZE 0x1000 + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) + #define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */ +#endif + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ - #include - +#define CONFIG_CMD_ASKENV +/* FIXME: hack for zynq */ +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ECHO + +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_JFFS2 +#ifndef CONFIG_SYS_ENET + #undef CONFIG_CMD_NET + #undef CONFIG_NET_MULTI +#else + #define CONFIG_CMD_PING + #define CONFIG_NET_MULTI +#endif + +#if defined(FLASH) + #define CONFIG_CMD_FLASH + #define CONFIG_CMD_IMLS +#else + #undef CONFIG_CMD_IMLS + #undef CONFIG_CMD_FLASH + #undef CONFIG_CMD_SAVEENV + #undef CONFIG_CMD_SAVES +#endif + +#if !defined(RAMENV) + #define CONFIG_CMD_SAVEENV + #define CONFIG_CMD_SAVES +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256/* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +\ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot Argument Buffer Size */ +#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START /* default load address */ + +#define CONFIG_BOOTDELAY 4 +/* Don't define BOOTARGS, we get it from the DTB chosen fragment */ +#undef CONFIG_BOOTARGS +#define CONFIG_HOSTNAME XILINX_BOARD_NAME + +#define CONFIG_BOOTCOMMAND "" + +/* architecture dependent code */ +#define CONFIG_SYS_USR_EXCEP /* user exception */ +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_ENV_OVERWRITE /* Allow to overwrite the u-boot environment variables */ +#define CONFIG_IPADDR 192.168.10.90 +#define CONFIG_SERVERIP 192.168.10.101 +#define CONFIG_ETHADDR 00:0a:35:00:92:d4 +#define CONFIG_BOOTP_SERVERIP + +#define CONFIG_CMDLINE_EDITING + +/* Use the HUSH parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 + +#if defined(CONFIG_XILINX_LL_TEMAC) +# define CONFIG_MII 1 +# define CONFIG_CMD_MII 1 +# define CONFIG_PHY_GIGE 1 +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 +# define CONFIG_PHYLIB 1 +# define CONFIG_PHY_ATHEROS 1 +# define CONFIG_PHY_BROADCOM 1 +# define CONFIG_PHY_DAVICOM 1 +# define CONFIG_PHY_LXT 1 +# define CONFIG_PHY_MARVELL 1 +# define CONFIG_PHY_MICREL 1 +# define CONFIG_PHY_NATSEMI 1 +# define CONFIG_PHY_REALTEK 1 +# define CONFIG_PHY_VITESSE 1 +#else +# undef CONFIG_MII +# undef CONFIG_CMD_MII +# undef CONFIG_PHYLIB +#endif + +#endif /* __CONFIG_H */ diff --cc include/configs/xilinx_zynqmp.h index 9b5f2a19ab8,ad82ed62890..d37b93b3f51 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@@ -169,7 -105,7 +170,7 @@@ #define CONFIG_BOOTARGS "setenv bootargs console=ttyPS0,${baudrate} " \ "earlycon=cdns,mmio,0xff000000,${baudrate}n8" - #define CONFIG_PREBOOT "run bootargs; run sata_root" -#define CONFIG_PREBOOT "run bootargs" ++#define CONFIG_PREBOOT "run bootargs; run sata_root; run setup" #define CONFIG_BOOTCOMMAND "run $modeboot" #define CONFIG_BOOTDELAY 5 diff --cc include/configs/zynq-common.h index 55d721aa0ba,5526214df24..d311f475cf6 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@@ -42,16 -39,15 +42,17 @@@ /* DCC driver */ #if defined(CONFIG_ZYNQ_DCC) # define CONFIG_ARM_DCC - # define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ #else -# define CONFIG_ZYNQ_SERIAL +# if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1) +# define CONFIG_ZYNQ_SERIAL +# endif #endif + #define CONFIG_ZYNQ_GPIO + #define CONFIG_CMD_GPIO + /* Ethernet driver */ #if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1) - # define CONFIG_NET_MULTI # define CONFIG_ZYNQ_GEM # define CONFIG_MII # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN @@@ -73,9 -68,7 +74,8 @@@ /* SPI */ #ifdef CONFIG_ZYNQ_SPI - # define CONFIG_SPI_FLASH # define CONFIG_SPI_FLASH_SST +# define CONFIG_CMD_SPI # define CONFIG_CMD_SF #endif @@@ -177,30 -168,6 +177,30 @@@ # define CONFIG_CMD_FS_GENERIC #endif ++#undef CONFIG_ZYNQ_QSPI /* Temporary solution till DM is added */ +/* QSPI */ +#ifdef CONFIG_ZYNQ_QSPI +# define CONFIG_SF_DEFAULT_SPEED 30000000 - # define CONFIG_SPI_FLASH +# define CONFIG_SPI_FLASH_BAR +# define CONFIG_SPI_FLASH_SPANSION +# define CONFIG_SPI_FLASH_STMICRO +# define CONFIG_SPI_FLASH_WINBOND +# define CONFIG_SPI_FLASH_ISSI +# define CONFIG_CMD_SPI +# define CONFIG_CMD_SF +# define CONFIG_SF_DUAL_FLASH +#endif + +/* NAND */ +#ifdef CONFIG_NAND_ZYNQ +# define CONFIG_CMD_NAND +# define CONFIG_CMD_NAND_LOCK_UNLOCK +# define CONFIG_SYS_MAX_NAND_DEVICE 1 +# define CONFIG_SYS_NAND_SELF_INIT +# define CONFIG_SYS_NAND_ONFI_DETECTION +# define CONFIG_MTD_DEVICE +#endif + #define CONFIG_SYS_I2C_ZYNQ /* I2C */ #if defined(CONFIG_SYS_I2C_ZYNQ) @@@ -244,10 -202,7 +244,9 @@@ # endif # define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# define CONFIG_ENV_OFFSET 0xE0000 +# ifndef CONFIG_ENV_OFFSET +# define CONFIG_ENV_OFFSET 0xE0000 +# endif - # define CONFIG_CMD_SAVEENV #endif /* Default environment */ @@@ -438,39 -294,13 +436,37 @@@ # define CONFIG_SYS_MMC_MAX_DEVICE 1 #endif - #define CONFIG_SYS_LDSCRIPT "arch/arm/cpu/armv7/zynq/u-boot.lds" + #define CONFIG_SYS_LDSCRIPT "arch/arm/mach-zynq/u-boot.lds" /* Commands */ - #include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_TFTPPUT +#ifdef CONFIG_SYS_ENET +# define CONFIG_CMD_PING +# define CONFIG_CMD_DHCP +# define CONFIG_CMD_MII +# define CONFIG_CMD_TFTPPUT +#else +# undef CONFIG_CMD_NET +# undef CONFIG_CMD_NFS +#endif + +#if defined(CONFIG_CMD_ZYNQ_RSA) +# ifndef CONFIG_RSA +# define CONFIG_RSA +# endif +#define CONFIG_SHA256 +#define CONFIG_CMD_ZYNQ_AES +#endif + +#define CONFIG_CMD_BOOTZ +#undef CONFIG_BOOTM_NETBSD + +#define CONFIG_SYS_HZ 1000 + +/* For development/debugging */ +#ifdef DEBUG +# define CONFIG_CMD_REGINFO +# define CONFIG_PANIC_HANG +#endif /* SPL part */ #define CONFIG_CMD_SPL @@@ -480,18 -310,8 +476,18 @@@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_BOARD_INIT - #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/zynq/u-boot-spl.lds" + #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-zynq/u-boot-spl.lds" +/* FPGA support */ +#define CONFIG_SPL_FPGA_SUPPORT +#define CONFIG_SPL_FPGA_LOAD_ADDR 0x1000000 +/* #define CONFIG_SPL_FPGA_BIT */ +#ifdef CONFIG_SPL_FPGA_BIT +# define CONFIG_SPL_FPGA_LOAD_ARGS_NAME "download.bit" +#else +# define CONFIG_SPL_FPGA_LOAD_ARGS_NAME "fpga.bin" +#endif + /* MMC support */ #ifdef CONFIG_ZYNQ_SDHCI0 #define CONFIG_SPL_MMC_SUPPORT @@@ -500,7 -320,7 +496,7 @@@ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_FAT_SUPPORT --#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" ++#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #endif /* Disable dcache for SPL just for sure */ diff --cc include/configs/zynq_cse.h index db2da747067,00000000000..0b20e2c47b8 mode 100644,000000..100644 --- a/include/configs/zynq_cse.h +++ b/include/configs/zynq_cse.h @@@ -1,79 -1,0 +1,77 @@@ +/* + * (C) Copyright 2013 Xilinx. + * + * Configuration settings for the Xilinx Zynq CSE board. + * See zynq-common.h for Zynq common configs + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_CSE_H +#define __CONFIG_ZYNQ_CSE_H + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ZYNQ_DCC +#define _CONFIG_CMD_DEFAULT_H +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_SYS_DCACHE_OFF + +#if defined(CONFIG_CSE_QSPI) +# define CONFIG_ZYNQ_QSPI + +#elif defined(CONFIG_CSE_NAND) +# define CONFIG_NAND_ZYNQ + +#elif defined(CONFIG_CSE_NOR) +#undef CONFIG_SYS_NO_FLASH + +#endif + +#include + +/* Undef unneeded configs */ +#undef CONFIG_SYS_SDRAM_BASE - #undef CONFIG_OF_LIBFDT +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOARD_LATE_INIT +#undef CONFIG_FPGA +#undef CONFIG_FPGA_XILINX +#undef CONFIG_FPGA_ZYNQPL +#undef CONFIG_CMD_FPGA +#undef CONFIG_FIT +#undef CONFIG_FIT_VERBOSE +#undef CONFIG_CMD_BOOTZ +#undef CONFIG_BOOTCOMMAND +#undef CONFIG_SYS_HUSH_PARSER +#undef CONFIG_SYS_PROMPT_HUSH_PS2 +#undef CONFIG_BOOTDELAY +#undef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_ENV_SIZE +#undef CONFIG_CMDLINE_EDITING +#undef CONFIG_AUTO_COMPLETE +#undef CONFIG_ZLIB +#undef CONFIG_GZIP +#undef CONFIG_CMD_SPL + +/* Define needed configs */ - #define CONFIG_CMD_MEMORY +#define CONFIG_BOOTDELAY -1 /* -1 to Disable autoboot */ +#define CONFIG_SYS_MALLOC_LEN 0x4000 + +#if defined(CONFIG_CSE_QSPI) +# define CONFIG_SYS_SDRAM_SIZE (256 * 1024) +# define CONFIG_SYS_SDRAM_BASE 0xFFFD0000 +# define CONFIG_ENV_SIZE 1400 + +#elif defined(CONFIG_CSE_NAND) +# define CONFIG_SYS_SDRAM_SIZE (4 * 1024 * 1024) +# define CONFIG_SYS_SDRAM_BASE 0 +# define CONFIG_ENV_SIZE 0x10000 + +#elif defined(CONFIG_CSE_NOR) +# define CONFIG_SYS_SDRAM_SIZE (256 * 1024) +# define CONFIG_SYS_SDRAM_BASE 0xFFFD0000 +# define CONFIG_ENV_SIZE 1400 + +#endif + +#endif /* __CONFIG_ZYNQ_CSE_H */ diff --cc include/spi.h index 0a10d1e0a51,18362364cf0..851ca9e19c6 --- a/include/spi.h +++ b/include/spi.h @@@ -132,8 -131,7 +135,8 @@@ struct spi_slave unsigned int max_write_size; void *memory_map; u8 option; - u8 flags; + u8 dio; - u8 flags; ++ u32 flags; }; /**