From: Greg Kroah-Hartman Date: Fri, 3 Apr 2020 09:32:08 +0000 (+0200) Subject: 4.19-stable patches X-Git-Tag: v5.4.31~41 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=4a3f968322de417d9e804e4661fd8d7f8d200b02;p=thirdparty%2Fkernel%2Fstable-queue.git 4.19-stable patches added patches: drm-etnaviv-replace-mmu-flush-marker-with-flush-sequence.patch --- diff --git a/queue-4.19/drm-etnaviv-replace-mmu-flush-marker-with-flush-sequence.patch b/queue-4.19/drm-etnaviv-replace-mmu-flush-marker-with-flush-sequence.patch new file mode 100644 index 00000000000..9183495e4c5 --- /dev/null +++ b/queue-4.19/drm-etnaviv-replace-mmu-flush-marker-with-flush-sequence.patch @@ -0,0 +1,126 @@ +From 4900dda90af2cb13bc1d4c12ce94b98acc8fe64e Mon Sep 17 00:00:00 2001 +From: Lucas Stach +Date: Fri, 5 Jul 2019 19:17:23 +0200 +Subject: drm/etnaviv: replace MMU flush marker with flush sequence +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Lucas Stach + +commit 4900dda90af2cb13bc1d4c12ce94b98acc8fe64e upstream. + +If a MMU is shared between multiple GPUs, all of them need to flush their +TLBs, so a single marker that gets reset on the first flush won't do. +Replace the flush marker with a sequence number, so that it's possible to +check if the TLB is in sync with the current page table state for each GPU. + +Signed-off-by: Lucas Stach +Reviewed-by: Philipp Zabel +Reviewed-by: Guido Günther +Signed-off-by: Robert Beckett +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/etnaviv/etnaviv_buffer.c | 10 ++++++---- + drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 1 + + drivers/gpu/drm/etnaviv/etnaviv_mmu.c | 6 +++--- + drivers/gpu/drm/etnaviv/etnaviv_mmu.h | 2 +- + 4 files changed, 11 insertions(+), 8 deletions(-) + +--- a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c ++++ b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c +@@ -311,6 +311,8 @@ void etnaviv_buffer_queue(struct etnaviv + u32 return_target, return_dwords; + u32 link_target, link_dwords; + bool switch_context = gpu->exec_state != exec_state; ++ unsigned int new_flush_seq = READ_ONCE(gpu->mmu->flush_seq); ++ bool need_flush = gpu->flush_seq != new_flush_seq; + + lockdep_assert_held(&gpu->lock); + +@@ -325,14 +327,14 @@ void etnaviv_buffer_queue(struct etnaviv + * need to append a mmu flush load state, followed by a new + * link to this buffer - a total of four additional words. + */ +- if (gpu->mmu->need_flush || switch_context) { ++ if (need_flush || switch_context) { + u32 target, extra_dwords; + + /* link command */ + extra_dwords = 1; + + /* flush command */ +- if (gpu->mmu->need_flush) { ++ if (need_flush) { + if (gpu->mmu->version == ETNAVIV_IOMMU_V1) + extra_dwords += 1; + else +@@ -345,7 +347,7 @@ void etnaviv_buffer_queue(struct etnaviv + + target = etnaviv_buffer_reserve(gpu, buffer, extra_dwords); + +- if (gpu->mmu->need_flush) { ++ if (need_flush) { + /* Add the MMU flush */ + if (gpu->mmu->version == ETNAVIV_IOMMU_V1) { + CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_MMU, +@@ -365,7 +367,7 @@ void etnaviv_buffer_queue(struct etnaviv + SYNC_RECIPIENT_PE); + } + +- gpu->mmu->need_flush = false; ++ gpu->flush_seq = new_flush_seq; + } + + if (switch_context) { +--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h ++++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h +@@ -139,6 +139,7 @@ struct etnaviv_gpu { + + struct etnaviv_iommu *mmu; + struct etnaviv_cmdbuf_suballoc *cmdbuf_suballoc; ++ unsigned int flush_seq; + + /* Power Control: */ + struct clk *clk_bus; +--- a/drivers/gpu/drm/etnaviv/etnaviv_mmu.c ++++ b/drivers/gpu/drm/etnaviv/etnaviv_mmu.c +@@ -261,7 +261,7 @@ int etnaviv_iommu_map_gem(struct etnaviv + } + + list_add_tail(&mapping->mmu_node, &mmu->mappings); +- mmu->need_flush = true; ++ mmu->flush_seq++; + unlock: + mutex_unlock(&mmu->lock); + +@@ -280,7 +280,7 @@ void etnaviv_iommu_unmap_gem(struct etna + etnaviv_iommu_remove_mapping(mmu, mapping); + + list_del(&mapping->mmu_node); +- mmu->need_flush = true; ++ mmu->flush_seq++; + mutex_unlock(&mmu->lock); + } + +@@ -357,7 +357,7 @@ int etnaviv_iommu_get_suballoc_va(struct + mutex_unlock(&mmu->lock); + return ret; + } +- gpu->mmu->need_flush = true; ++ mmu->flush_seq++; + mutex_unlock(&mmu->lock); + + *iova = (u32)vram_node->start; +--- a/drivers/gpu/drm/etnaviv/etnaviv_mmu.h ++++ b/drivers/gpu/drm/etnaviv/etnaviv_mmu.h +@@ -48,7 +48,7 @@ struct etnaviv_iommu { + struct mutex lock; + struct list_head mappings; + struct drm_mm mm; +- bool need_flush; ++ unsigned int flush_seq; + }; + + struct etnaviv_gem_object; diff --git a/queue-4.19/series b/queue-4.19/series index 69141639c36..88feeca9c8c 100644 --- a/queue-4.19/series +++ b/queue-4.19/series @@ -9,3 +9,4 @@ initramfs-restore-default-compression-behavior.patch drm-amdgpu-fix-typo-for-vcn1-idle-check.patch tools-power-turbostat-fix-gcc-build-warnings.patch tools-power-turbostat-fix-missing-sys_lpi-counter-on.patch +drm-etnaviv-replace-mmu-flush-marker-with-flush-sequence.patch diff --git a/queue-4.19/tools-power-turbostat-fix-missing-sys_lpi-counter-on.patch b/queue-4.19/tools-power-turbostat-fix-missing-sys_lpi-counter-on.patch index ce0d470a682..cbdd8cd3aa6 100644 --- a/queue-4.19/tools-power-turbostat-fix-missing-sys_lpi-counter-on.patch +++ b/queue-4.19/tools-power-turbostat-fix-missing-sys_lpi-counter-on.patch @@ -18,14 +18,12 @@ from the pmc_core driver, which accesses the same counter value. Signed-off-by: Len Brown Signed-off-by: Sasha Levin --- - tools/power/x86/turbostat/turbostat.c | 23 ++++++++++++++--------- + tools/power/x86/turbostat/turbostat.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) -diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c -index fb665fdc722a4..2233cf722c692 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c -@@ -299,6 +299,10 @@ int *irqs_per_cpu; /* indexed by cpu_num */ +@@ -299,6 +299,10 @@ int *irqs_per_cpu; /* indexed by cpu_nu void setup_all_buffers(void); @@ -84,6 +82,3 @@ index fb665fdc722a4..2233cf722c692 100644 if (!quiet) decode_misc_feature_control(); --- -2.20.1 -