From: Chen-Yu Tsai Date: Mon, 2 Mar 2026 05:31:07 +0000 (+0800) Subject: arm64: dts: mediatek: mt8195-cherry-dojo: Describe M.2 M-key NVMe slot X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=4c434585ce6d485ee12ed6becb1524f933454aba;p=thirdparty%2Fkernel%2Flinux.git arm64: dts: mediatek: mt8195-cherry-dojo: Describe M.2 M-key NVMe slot The Dojo device has a M.2 M-key slot for an included NVMe on some models. Add a proper device tree description based on the new M.2 M-key binding. Power for the slot is controlled by the embedded controller. As far as the main SoC is concerned, it is always on. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Manivannan Sadhasivam Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts index 49664de99b882..57cc329f49c45 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts @@ -11,6 +11,28 @@ compatible = "google,dojo-sku7", "google,dojo-sku5", "google,dojo-sku3", "google,dojo-sku1", "google,dojo", "mediatek,mt8195"; + + nvme-connector { + compatible = "pcie-m2-m-connector"; + /* power is controlled by EC */ + vpcie3v3-supply = <&pp3300_z2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + nvme_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&pcie0_ep>; + }; + }; + }; + }; }; &audio_codec { @@ -72,6 +94,22 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie0_pins_default>; status = "okay"; + + pcie@0 { + compatible = "pciclass,0604"; + reg = <0 0 0 0 0>; + device_type = "pci"; + num-lanes = <2>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + port { + pcie0_ep: endpoint { + remote-endpoint = <&nvme_ep>; + }; + }; + }; }; &pciephy {