From: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Date: Wed, 10 Sep 2025 20:08:29 +0000 (-0300)
Subject: atomic: Consolidate atomic_write_barrier implementation
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=4d1b9dc6ec4d6aa28f3428d36086d79585fdc1bf;p=thirdparty%2Fglibc.git

atomic: Consolidate atomic_write_barrier implementation

All ABIs, except alpha and sparc, define it to
atomic_full_barrier/__sync_synchronize, which can be mapped to
__atomic_thread_fence (__ATOMIC_RELEASE).

For alpha, it uses a 'wmb' which does not map to any of C11
barriers.

For sparc it uses a stronger 'member #LoadStore | #StoreStore',
where the release barrier maps to just 'membar #StoreLoad'.  The
patch keeps the sparc definition.

For PowerPC, it allows the use of lwsync for additional chips
(since _ARCH_PWR4 does not cover all chips that support it).

Tested on aarch64-linux-gnu.

Co-authored-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
---

diff --git a/include/atomic.h b/include/atomic.h
index 94eb9b582e..07c5324f8b 100644
--- a/include/atomic.h
+++ b/include/atomic.h
@@ -99,11 +99,6 @@
 #endif
 
 
-#ifndef atomic_write_barrier
-# define atomic_write_barrier() atomic_full_barrier ()
-#endif
-
-
 #ifndef atomic_forced_read
 # define atomic_forced_read(x) \
   ({ __typeof (x) __x; __asm ("" : "=r" (__x) : "0" (x)); __x; })
@@ -258,6 +253,10 @@ void __atomic_link_error (void);
 # define atomic_read_barrier() atomic_thread_fence_acquire ()
 #endif
 
+#ifndef atomic_write_barrier
+# define atomic_write_barrier() atomic_thread_fence_release ()
+#endif
+
 
 /* ATOMIC_EXCHANGE_USES_CAS is non-zero if atomic_exchange operations
    are implemented based on a CAS loop; otherwise, this is zero and we assume
diff --git a/sysdeps/generic/malloc-machine.h b/sysdeps/generic/malloc-machine.h
index 4fb8e809cc..9b5e9b2dd1 100644
--- a/sysdeps/generic/malloc-machine.h
+++ b/sysdeps/generic/malloc-machine.h
@@ -22,10 +22,6 @@
 
 #include <atomic.h>
 
-#ifndef atomic_write_barrier
-# define atomic_write_barrier() atomic_full_barrier ()
-#endif
-
 #ifndef DEFAULT_TOP_PAD
 # define DEFAULT_TOP_PAD 131072
 #endif
diff --git a/sysdeps/powerpc/atomic-machine.h b/sysdeps/powerpc/atomic-machine.h
index e173b61e9c..e32408a09d 100644
--- a/sysdeps/powerpc/atomic-machine.h
+++ b/sysdeps/powerpc/atomic-machine.h
@@ -36,13 +36,4 @@
 # define MUTEX_HINT_REL
 #endif
 
-#ifdef _ARCH_PWR4
-/*
- * "light weight" sync can also be used for the release barrier.
- */
-# define atomic_write_barrier()	__asm ("lwsync" ::: "memory")
-#else
-# define atomic_write_barrier()	__asm ("sync" ::: "memory")
-#endif
-
 #endif
diff --git a/sysdeps/x86/atomic-machine.h b/sysdeps/x86/atomic-machine.h
index f46a0868e3..0051eede70 100644
--- a/sysdeps/x86/atomic-machine.h
+++ b/sysdeps/x86/atomic-machine.h
@@ -31,8 +31,6 @@
 
 #define ATOMIC_EXCHANGE_USES_CAS	0
 
-#define atomic_write_barrier() __asm ("" ::: "memory")
-
 #define atomic_spin_nop() __asm ("pause")
 
 #endif /* atomic-machine.h */