From: Zihao Yu <yuzihao@ict.ac.cn>
Date: Wed, 17 Mar 2021 08:17:25 +0000 (+0800)
Subject: riscv,entry: fix misaligned base for excp_vect_table
X-Git-Tag: v4.19.188~7
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=4f17a45f8e35068cfb25c66fdd85606962a3a448;p=thirdparty%2Fkernel%2Fstable.git

riscv,entry: fix misaligned base for excp_vect_table

[ Upstream commit ac8d0b901f0033b783156ab2dc1a0e73ec42409b ]

In RV64, the size of each entry in excp_vect_table is 8 bytes. If the
base of the table is not 8-byte aligned, loading an entry in the table
will raise a misaligned exception. Although such exception will be
handled by opensbi/bbl, this still causes performance degradation.

Signed-off-by: Zihao Yu <yuzihao@ict.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index a03821b2656aa..d9de22686e27d 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -449,6 +449,7 @@ ENDPROC(__fstate_restore)
 
 
 	.section ".rodata"
+	.align LGREG
 	/* Exception vector table */
 ENTRY(excp_vect_table)
 	RISCV_PTR do_trap_insn_misaligned