From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 5 Sep 2013 06:41:19 +0000 (+0200)
Subject: zynq: ddrc: Setup half of memory only for ECC case
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=50b95bdb97a51a4b9b8be3b9a93618dbcd78526f;p=thirdparty%2Fu-boot.git

zynq: ddrc: Setup half of memory only for ECC case

This patch is around for a while but it was lost
in past and Mike has pointed to it again.

Here is description from Mike which handle non ECC case:
While bringing up a board that uses only a single memory chip, and
hence only 16-bit DDR width, the memory size was somehow cut in half.
The cause turned out to be a line in ddrc.c that just divides the memory
size by two for no apparent reason when the bus width is 16.

The memory size is simply obtained from a constant in the configuration
header, so do not modify it. Tested this on my board and now the memory
size is correct.

Reported-by: Cayer Yves <ycayer@ciena.com>
Reported-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c
index ba6a6aee5cb..258283dbc29 100644
--- a/arch/arm/cpu/armv7/zynq/ddrc.c
+++ b/arch/arm/cpu/armv7/zynq/ddrc.c
@@ -41,10 +41,9 @@ void zynq_ddrc_init(void)
 		 * been initialized by writing any value.
 		 */
 		memset(0, 0, 1 * 1024 * 1024);
+
+		gd->ram_size /= 2;
 	} else {
 		puts("Memory: ECC disabled\n");
 	}
-
-	if (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)
-		gd->ram_size /= 2;
 }