From: Greg Kroah-Hartman Date: Fri, 2 Mar 2012 21:23:30 +0000 (-0800) Subject: 3.0-stable patches X-Git-Tag: v3.0.24~39 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=50e3faecdf70283a31b358c70fd11d14c7ab1b4f;p=thirdparty%2Fkernel%2Fstable-queue.git 3.0-stable patches added patches: arm-lpc32xx-fix-interrupt-controller-init.patch arm-lpc32xx-fix-irq-on-gpi_28.patch arm-lpc32xx-irq.c-clear-latched-event.patch arm-lpc32xx-serial.c-fixed-loop-limit.patch arm-lpc32xx-serial.c-hw-bug-workaround.patch drm-i915-prevent-a-machine-hang-by-checking-crtc-active-before-loading-lut.patch i2c-mxs-only-flag-completion-when-queue-is-completely-done.patch regulator-fix-the-ldo-configure-according-to-88pm860x-spec.patch s390-keys-enable-the-compat-keyctl-wrapper-on-s390x.patch watchdog-hpwdt-clean-up-set_memory_x-call-for-32-bit.patch --- diff --git a/queue-3.0/arm-lpc32xx-fix-interrupt-controller-init.patch b/queue-3.0/arm-lpc32xx-fix-interrupt-controller-init.patch new file mode 100644 index 00000000000..54c6c127078 --- /dev/null +++ b/queue-3.0/arm-lpc32xx-fix-interrupt-controller-init.patch @@ -0,0 +1,42 @@ +From 35dd0a75d4a382e7f769dd0277732e7aa5235718 Mon Sep 17 00:00:00 2001 +From: Roland Stigge +Date: Mon, 27 Feb 2012 17:28:02 +0100 +Subject: ARM: LPC32xx: Fix interrupt controller init + +From: Roland Stigge + +commit 35dd0a75d4a382e7f769dd0277732e7aa5235718 upstream. + +This patch fixes the initialization of the interrupt controller of the LPC32xx +by correctly setting up SIC1 and SIC2 instead of (wrongly) using the same value +as for the Main Interrupt Controller (MIC). + +Signed-off-by: Roland Stigge +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-lpc32xx/irq.c | 10 ++++++---- + 1 file changed, 6 insertions(+), 4 deletions(-) + +--- a/arch/arm/mach-lpc32xx/irq.c ++++ b/arch/arm/mach-lpc32xx/irq.c +@@ -389,13 +389,15 @@ void __init lpc32xx_init_irq(void) + + /* Setup SIC1 */ + __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE)); +- __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE)); +- __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE)); ++ __raw_writel(SIC1_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE)); ++ __raw_writel(SIC1_ATR_DEFAULT, ++ LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE)); + + /* Setup SIC2 */ + __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); +- __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE)); +- __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE)); ++ __raw_writel(SIC2_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE)); ++ __raw_writel(SIC2_ATR_DEFAULT, ++ LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE)); + + /* Configure supported IRQ's */ + for (i = 0; i < NR_IRQS; i++) { diff --git a/queue-3.0/arm-lpc32xx-fix-irq-on-gpi_28.patch b/queue-3.0/arm-lpc32xx-fix-irq-on-gpi_28.patch new file mode 100644 index 00000000000..eeefc12e86c --- /dev/null +++ b/queue-3.0/arm-lpc32xx-fix-irq-on-gpi_28.patch @@ -0,0 +1,46 @@ +From f6737055c1c432a9628a9a731f9881ad8e0a9eee Mon Sep 17 00:00:00 2001 +From: Roland Stigge +Date: Mon, 27 Feb 2012 17:28:02 +0100 +Subject: ARM: LPC32xx: Fix irq on GPI_28 + +From: Roland Stigge + +commit f6737055c1c432a9628a9a731f9881ad8e0a9eee upstream. + +The GPI_28 IRQ was not registered properly. The registration of +IRQ_LPC32XX_GPI_28 was added and the (wrong) IRQ_LPC32XX_GPI_11 at +LPC32XX_SIC1_IRQ(4) was replaced by IRQ_LPC32XX_GPI_28 (see manual of +LPC32xx / interrupt controller). + +Signed-off-by: Roland Stigge +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-lpc32xx/include/mach/irqs.h | 2 +- + arch/arm/mach-lpc32xx/irq.c | 4 ++++ + 2 files changed, 5 insertions(+), 1 deletion(-) + +--- a/arch/arm/mach-lpc32xx/include/mach/irqs.h ++++ b/arch/arm/mach-lpc32xx/include/mach/irqs.h +@@ -61,7 +61,7 @@ + */ + #define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1) + #define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2) +-#define IRQ_LPC32XX_GPI_11 LPC32XX_SIC1_IRQ(4) ++#define IRQ_LPC32XX_GPI_28 LPC32XX_SIC1_IRQ(4) + #define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6) + #define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7) + #define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8) +--- a/arch/arm/mach-lpc32xx/irq.c ++++ b/arch/arm/mach-lpc32xx/irq.c +@@ -118,6 +118,10 @@ static const struct lpc32xx_event_info l + .event_group = &lpc32xx_event_pin_regs, + .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT, + }, ++ [IRQ_LPC32XX_GPI_28] = { ++ .event_group = &lpc32xx_event_pin_regs, ++ .mask = LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT, ++ }, + [IRQ_LPC32XX_GPIO_00] = { + .event_group = &lpc32xx_event_int_regs, + .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT, diff --git a/queue-3.0/arm-lpc32xx-irq.c-clear-latched-event.patch b/queue-3.0/arm-lpc32xx-irq.c-clear-latched-event.patch new file mode 100644 index 00000000000..f0edf7a644d --- /dev/null +++ b/queue-3.0/arm-lpc32xx-irq.c-clear-latched-event.patch @@ -0,0 +1,40 @@ +From 94ed7830cba4dce57b18a2926b5d826bfd184bd6 Mon Sep 17 00:00:00 2001 +From: Roland Stigge +Date: Mon, 27 Feb 2012 17:28:02 +0100 +Subject: ARM: LPC32xx: irq.c: Clear latched event + +From: Roland Stigge + +commit 94ed7830cba4dce57b18a2926b5d826bfd184bd6 upstream. + +This patch fixes the wakeup disable function by clearing latched events. + +Signed-off-by: Roland Stigge +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-lpc32xx/irq.c | 11 ++++++++++- + 1 file changed, 10 insertions(+), 1 deletion(-) + +--- a/arch/arm/mach-lpc32xx/irq.c ++++ b/arch/arm/mach-lpc32xx/irq.c +@@ -305,9 +305,18 @@ static int lpc32xx_irq_wake(struct irq_d + + if (state) + eventreg |= lpc32xx_events[d->irq].mask; +- else ++ else { + eventreg &= ~lpc32xx_events[d->irq].mask; + ++ /* ++ * When disabling the wakeup, clear the latched ++ * event ++ */ ++ __raw_writel(lpc32xx_events[d->irq].mask, ++ lpc32xx_events[d->irq]. ++ event_group->rawstat_reg); ++ } ++ + __raw_writel(eventreg, + lpc32xx_events[d->irq].event_group->enab_reg); + diff --git a/queue-3.0/arm-lpc32xx-serial.c-fixed-loop-limit.patch b/queue-3.0/arm-lpc32xx-serial.c-fixed-loop-limit.patch new file mode 100644 index 00000000000..afe5e1a0197 --- /dev/null +++ b/queue-3.0/arm-lpc32xx-serial.c-fixed-loop-limit.patch @@ -0,0 +1,29 @@ +From ff424aa4c89d19082e8ae5a3351006bc8a4cd91b Mon Sep 17 00:00:00 2001 +From: Roland Stigge +Date: Mon, 27 Feb 2012 17:28:03 +0100 +Subject: ARM: LPC32xx: serial.c: Fixed loop limit + +From: Roland Stigge + +commit ff424aa4c89d19082e8ae5a3351006bc8a4cd91b upstream. + +This patch fixes a wrong loop limit on UART init. + +Signed-off-by: Roland Stigge +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-lpc32xx/serial.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/mach-lpc32xx/serial.c ++++ b/arch/arm/mach-lpc32xx/serial.c +@@ -187,7 +187,7 @@ void __init lpc32xx_serial_init(void) + + /* This needs to be done after all UART clocks are setup */ + __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); +- for (i = 0; i < ARRAY_SIZE(uartinit_data) - 1; i++) { ++ for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) { + /* Force a flush of the RX FIFOs to work around a HW bug */ + puart = serial_std_platform_data[i].mapbase; + __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); diff --git a/queue-3.0/arm-lpc32xx-serial.c-hw-bug-workaround.patch b/queue-3.0/arm-lpc32xx-serial.c-hw-bug-workaround.patch new file mode 100644 index 00000000000..63be8976f94 --- /dev/null +++ b/queue-3.0/arm-lpc32xx-serial.c-hw-bug-workaround.patch @@ -0,0 +1,81 @@ +From 2707208ee8a80dbbd5426f5aa1a934f766825bb5 Mon Sep 17 00:00:00 2001 +From: Roland Stigge +Date: Mon, 27 Feb 2012 17:28:02 +0100 +Subject: ARM: LPC32xx: serial.c: HW bug workaround + +From: Roland Stigge + +commit 2707208ee8a80dbbd5426f5aa1a934f766825bb5 upstream. + +This patch fixes a HW bug by flushing RX FIFOs of the UARTs on init. It was +ported from NXP's git.lpclinux.com tree. + +Signed-off-by: Roland Stigge +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-lpc32xx/serial.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/arch/arm/mach-lpc32xx/serial.c ++++ b/arch/arm/mach-lpc32xx/serial.c +@@ -88,6 +88,7 @@ struct uartinit { + char *uart_ck_name; + u32 ck_mode_mask; + void __iomem *pdiv_clk_reg; ++ resource_size_t mapbase; + }; + + static struct uartinit uartinit_data[] __initdata = { +@@ -97,6 +98,7 @@ static struct uartinit uartinit_data[] _ + .ck_mode_mask = + LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5), + .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL, ++ .mapbase = LPC32XX_UART5_BASE, + }, + #endif + #ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT +@@ -105,6 +107,7 @@ static struct uartinit uartinit_data[] _ + .ck_mode_mask = + LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3), + .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL, ++ .mapbase = LPC32XX_UART3_BASE, + }, + #endif + #ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT +@@ -113,6 +116,7 @@ static struct uartinit uartinit_data[] _ + .ck_mode_mask = + LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4), + .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL, ++ .mapbase = LPC32XX_UART4_BASE, + }, + #endif + #ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT +@@ -121,6 +125,7 @@ static struct uartinit uartinit_data[] _ + .ck_mode_mask = + LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6), + .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL, ++ .mapbase = LPC32XX_UART6_BASE, + }, + #endif + }; +@@ -165,6 +170,19 @@ void __init lpc32xx_serial_init(void) + + /* pre-UART clock divider set to 1 */ + __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg); ++ ++ /* ++ * Force a flush of the RX FIFOs to work around a ++ * HW bug ++ */ ++ puart = uartinit_data[i].mapbase; ++ __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); ++ __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); ++ j = LPC32XX_SUART_FIFO_SIZE; ++ while (j--) ++ tmp = __raw_readl( ++ LPC32XX_UART_DLL_FIFO(puart)); ++ __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); + } + + /* This needs to be done after all UART clocks are setup */ diff --git a/queue-3.0/drm-i915-prevent-a-machine-hang-by-checking-crtc-active-before-loading-lut.patch b/queue-3.0/drm-i915-prevent-a-machine-hang-by-checking-crtc-active-before-loading-lut.patch new file mode 100644 index 00000000000..8645519f99c --- /dev/null +++ b/queue-3.0/drm-i915-prevent-a-machine-hang-by-checking-crtc-active-before-loading-lut.patch @@ -0,0 +1,39 @@ +From aed3f09db39596e539f90b11a5016aea4d8442e1 Mon Sep 17 00:00:00 2001 +From: Alban Browaeys +Date: Fri, 24 Feb 2012 17:12:45 +0000 +Subject: drm/i915: Prevent a machine hang by checking crtc->active before loading lut + +From: Alban Browaeys + +commit aed3f09db39596e539f90b11a5016aea4d8442e1 upstream. + +Before loading the lut (gamma), check the active state of intel_crtc, +otherwise at least on gen2 hang ensue. + +This is reproducible in Xorg via: + xset dpms force off +then + xgamma -rgamma 2.0 # freeze. + +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44505 +Signed-off-by: Alban Browaeys +Signed-off-by: Chris Wilson +Reviewed-by: Jesse Barnes +Signed-off-by: Jesse Barnes +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_display.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/intel_display.c ++++ b/drivers/gpu/drm/i915/intel_display.c +@@ -5265,7 +5265,7 @@ void intel_crtc_load_lut(struct drm_crtc + int i; + + /* The clocks have to be on to load the palette. */ +- if (!crtc->enabled) ++ if (!crtc->enabled || !intel_crtc->active) + return; + + /* use legacy palette for Ironlake */ diff --git a/queue-3.0/i2c-mxs-only-flag-completion-when-queue-is-completely-done.patch b/queue-3.0/i2c-mxs-only-flag-completion-when-queue-is-completely-done.patch new file mode 100644 index 00000000000..c71a334563f --- /dev/null +++ b/queue-3.0/i2c-mxs-only-flag-completion-when-queue-is-completely-done.patch @@ -0,0 +1,80 @@ +From 844990daa2e69a4258049ba9c2bae1180657dac3 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang +Date: Fri, 13 Jan 2012 12:14:26 +0100 +Subject: i2c: mxs: only flag completion when queue is completely done +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Wolfram Sang + +commit 844990daa2e69a4258049ba9c2bae1180657dac3 upstream. + +The hardware generates an interrupt for every completed command in the +queue while the code assumed that it will only generate one interrupt +when the queue is empty. So, explicitly check if the queue is really +empty. This patch fixed problems which occurred due to high traffic on +the bus. While we are here, move the completion-initialization after the +parameter error checking. + +Signed-off-by: Wolfram Sang +Cc: Shawn Guo +Cc: Marek Vasut +Cc: Lothar Waßmann +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/i2c/busses/i2c-mxs.c | 13 ++++++++++--- + 1 file changed, 10 insertions(+), 3 deletions(-) + +--- a/drivers/i2c/busses/i2c-mxs.c ++++ b/drivers/i2c/busses/i2c-mxs.c +@@ -72,6 +72,7 @@ + + #define MXS_I2C_QUEUESTAT (0x70) + #define MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY 0x00002000 ++#define MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK 0x0000001F + + #define MXS_I2C_QUEUECMD (0x80) + +@@ -219,14 +220,14 @@ static int mxs_i2c_xfer_msg(struct i2c_a + int ret; + int flags; + +- init_completion(&i2c->cmd_complete); +- + dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", + msg->addr, msg->len, msg->flags, stop); + + if (msg->len == 0) + return -EINVAL; + ++ init_completion(&i2c->cmd_complete); ++ + flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0; + + if (msg->flags & I2C_M_RD) +@@ -286,6 +287,7 @@ static irqreturn_t mxs_i2c_isr(int this_ + { + struct mxs_i2c_dev *i2c = dev_id; + u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK; ++ bool is_last_cmd; + + if (!stat) + return IRQ_NONE; +@@ -300,9 +302,14 @@ static irqreturn_t mxs_i2c_isr(int this_ + else + i2c->cmd_err = 0; + +- complete(&i2c->cmd_complete); ++ is_last_cmd = (readl(i2c->regs + MXS_I2C_QUEUESTAT) & ++ MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK) == 0; ++ ++ if (is_last_cmd || i2c->cmd_err) ++ complete(&i2c->cmd_complete); + + writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR); ++ + return IRQ_HANDLED; + } + diff --git a/queue-3.0/regulator-fix-the-ldo-configure-according-to-88pm860x-spec.patch b/queue-3.0/regulator-fix-the-ldo-configure-according-to-88pm860x-spec.patch new file mode 100644 index 00000000000..fa0b0fbe039 --- /dev/null +++ b/queue-3.0/regulator-fix-the-ldo-configure-according-to-88pm860x-spec.patch @@ -0,0 +1,41 @@ +From 3380643b0eaa7ecf99c4f095bdfcb6e5df471616 Mon Sep 17 00:00:00 2001 +From: "Jett.Zhou" +Date: Thu, 23 Feb 2012 19:52:08 +0800 +Subject: regulator: fix the ldo configure according to 88pm860x spec + +From: "Jett.Zhou" + +commit 3380643b0eaa7ecf99c4f095bdfcb6e5df471616 upstream. + +Signed-off-by: Jett.Zhou +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/regulator/88pm8607.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/regulator/88pm8607.c ++++ b/drivers/regulator/88pm8607.c +@@ -195,7 +195,7 @@ static const unsigned int LDO12_suspend_ + }; + + static const unsigned int LDO13_table[] = { +- 1300000, 1800000, 2000000, 2500000, 2800000, 3000000, 0, 0, ++ 1200000, 1300000, 1800000, 2000000, 2500000, 2800000, 3000000, 0, + }; + + static const unsigned int LDO13_suspend_table[] = { +@@ -388,10 +388,10 @@ static struct pm8607_regulator_info pm86 + PM8607_LDO( 7, LDO7, 0, 3, SUPPLIES_EN12, 1), + PM8607_LDO( 8, LDO8, 0, 3, SUPPLIES_EN12, 2), + PM8607_LDO( 9, LDO9, 0, 3, SUPPLIES_EN12, 3), +- PM8607_LDO(10, LDO10, 0, 3, SUPPLIES_EN12, 4), ++ PM8607_LDO(10, LDO10, 0, 4, SUPPLIES_EN12, 4), + PM8607_LDO(12, LDO12, 0, 4, SUPPLIES_EN12, 5), + PM8607_LDO(13, VIBRATOR_SET, 1, 3, VIBRATOR_SET, 0), +- PM8607_LDO(14, LDO14, 0, 4, SUPPLIES_EN12, 6), ++ PM8607_LDO(14, LDO14, 0, 3, SUPPLIES_EN12, 6), + }; + + static int __devinit pm8607_regulator_probe(struct platform_device *pdev) diff --git a/queue-3.0/s390-keys-enable-the-compat-keyctl-wrapper-on-s390x.patch b/queue-3.0/s390-keys-enable-the-compat-keyctl-wrapper-on-s390x.patch new file mode 100644 index 00000000000..a83dce08b43 --- /dev/null +++ b/queue-3.0/s390-keys-enable-the-compat-keyctl-wrapper-on-s390x.patch @@ -0,0 +1,48 @@ +From 1d057720609ed052a6371fe1d53300e5e6328e94 Mon Sep 17 00:00:00 2001 +From: David Howells +Date: Fri, 24 Feb 2012 18:01:27 +0100 +Subject: S390: KEYS: Enable the compat keyctl wrapper on s390x + +From: David Howells + +commit 1d057720609ed052a6371fe1d53300e5e6328e94 upstream. + +Enable the compat keyctl wrapper on s390x so that 32-bit s390 userspace can +call the keyctl() syscall. + +There's an s390x assembly wrapper that truncates all the register values to +32-bits and this then calls compat_sys_keyctl() - but the latter only exists if +CONFIG_KEYS_COMPAT is enabled, and the s390 Kconfig doesn't enable it. + +Without this patch, 32-bit calls to the keyctl() syscall are given an ENOSYS +error: + + [root@devel4 ~]# keyctl show + Session Keyring + -3: key inaccessible (Function not implemented) + +Signed-off-by: David Howells +Acked-by: dan@danny.cz +Cc: Carsten Otte +Reviewed-by: Christian Borntraeger +Cc: linux-s390@vger.kernel.org +Signed-off-by: Heiko Carstens +Signed-off-by: Martin Schwidefsky +Signed-off-by: Greg Kroah-Hartman + +--- + arch/s390/Kconfig | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/arch/s390/Kconfig ++++ b/arch/s390/Kconfig +@@ -228,6 +228,9 @@ config COMPAT + config SYSVIPC_COMPAT + def_bool y if COMPAT && SYSVIPC + ++config KEYS_COMPAT ++ def_bool y if COMPAT && KEYS ++ + config AUDIT_ARCH + def_bool y + diff --git a/queue-3.0/series b/queue-3.0/series index 9fc45f82f1c..4fea4972727 100644 --- a/queue-3.0/series +++ b/queue-3.0/series @@ -1,3 +1,13 @@ autofs-work-around-unhappy-compat-problem-on-x86-64.patch fix-autofs-compile-without-config_compat.patch compat-fix-compile-breakage-on-s390.patch +drm-i915-prevent-a-machine-hang-by-checking-crtc-active-before-loading-lut.patch +arm-lpc32xx-serial.c-hw-bug-workaround.patch +arm-lpc32xx-serial.c-fixed-loop-limit.patch +arm-lpc32xx-irq.c-clear-latched-event.patch +arm-lpc32xx-fix-interrupt-controller-init.patch +arm-lpc32xx-fix-irq-on-gpi_28.patch +watchdog-hpwdt-clean-up-set_memory_x-call-for-32-bit.patch +i2c-mxs-only-flag-completion-when-queue-is-completely-done.patch +regulator-fix-the-ldo-configure-according-to-88pm860x-spec.patch +s390-keys-enable-the-compat-keyctl-wrapper-on-s390x.patch diff --git a/queue-3.0/watchdog-hpwdt-clean-up-set_memory_x-call-for-32-bit.patch b/queue-3.0/watchdog-hpwdt-clean-up-set_memory_x-call-for-32-bit.patch new file mode 100644 index 00000000000..4879b06f6f8 --- /dev/null +++ b/queue-3.0/watchdog-hpwdt-clean-up-set_memory_x-call-for-32-bit.patch @@ -0,0 +1,52 @@ +From 97d2a10d5804d585ab0b58efbd710948401b886a Mon Sep 17 00:00:00 2001 +From: Maxim Uvarov +Date: Sun, 15 Jan 2012 20:02:50 -0800 +Subject: watchdog: hpwdt: clean up set_memory_x call for 32 bit + +From: Maxim Uvarov + +commit 97d2a10d5804d585ab0b58efbd710948401b886a upstream. + +1. address has to be page aligned. +2. set_memory_x uses page size argument, not size. +Bug causes with following commit: + commit da28179b4e90dda56912ee825c7eaa62fc103797 + Author: Mingarelli, Thomas + Date: Mon Nov 7 10:59:00 2011 +0100 + + watchdog: hpwdt: Changes to handle NX secure bit in 32bit path + + commit e67d668e147c3b4fec638c9e0ace04319f5ceccd upstream. + + This patch makes use of the set_memory_x() kernel API in order + to make necessary BIOS calls to source NMIs. + +Signed-off-by: Maxim Uvarov +Signed-off-by: Wim Van Sebroeck +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/watchdog/hpwdt.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/watchdog/hpwdt.c ++++ b/drivers/watchdog/hpwdt.c +@@ -216,7 +216,7 @@ static int __devinit cru_detect(unsigned + + cmn_regs.u1.reax = CRU_BIOS_SIGNATURE_VALUE; + +- set_memory_x((unsigned long)bios32_entrypoint, (2 * PAGE_SIZE)); ++ set_memory_x((unsigned long)bios32_map, 2); + asminline_call(&cmn_regs, bios32_entrypoint); + + if (cmn_regs.u1.ral != 0) { +@@ -235,7 +235,8 @@ static int __devinit cru_detect(unsigned + cru_rom_addr = + ioremap(cru_physical_address, cru_length); + if (cru_rom_addr) { +- set_memory_x((unsigned long)cru_rom_addr, cru_length); ++ set_memory_x((unsigned long)cru_rom_addr & PAGE_MASK, ++ (cru_length + PAGE_SIZE - 1) >> PAGE_SHIFT); + retval = 0; + } + }