From: Catalin Marinas <catalin.marinas@arm.com>
Date: Fri, 28 Nov 2025 15:47:53 +0000 (+0000)
Subject: Merge branch 'for-next/sysreg' into for-next/core
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=52c4d1d62424c574fa048235598ce37bd4ed1e32;p=thirdparty%2Fkernel%2Flinux.git

Merge branch 'for-next/sysreg' into for-next/core

* for-next/sysreg:
  : arm64 sysreg updates/cleanups
  arm64/sysreg: Remove unused define ARM64_FEATURE_FIELD_BITS
  KVM: arm64: selftests: Consider all 7 possible levels of cache
  KVM: arm64: selftests: Remove ARM64_FEATURE_FIELD_BITS and its last user
  arm64/sysreg: Add ICH_VMCR_EL2
  arm64/sysreg: Move generation of RES0/RES1/UNKN to function
  arm64/sysreg: Support feature-specific fields with 'Prefix' descriptor
  arm64/sysreg: Fix checks for incomplete sysreg definitions
  arm64/sysreg: Replace TCR_EL1 field macros
---

52c4d1d62424c574fa048235598ce37bd4ed1e32
diff --cc arch/arm64/include/asm/cputype.h
index 024b4fa976a85,f14eb942cb4ae..08860d482e600
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@@ -247,9 -247,9 +247,9 @@@
  /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
  #define MIDR_FUJITSU_ERRATUM_010001		MIDR_FUJITSU_A64FX
  #define MIDR_FUJITSU_ERRATUM_010001_MASK	(~MIDR_CPU_VAR_REV(1, 0))
- #define TCR_CLEAR_FUJITSU_ERRATUM_010001	(TCR_NFD1 | TCR_NFD0)
+ #define TCR_CLEAR_FUJITSU_ERRATUM_010001	(TCR_EL1_NFD1 | TCR_EL1_NFD0)
  
 -#ifndef __ASSEMBLY__
 +#ifndef __ASSEMBLER__
  
  #include <asm/sysreg.h>
  
diff --cc arch/arm64/include/asm/sysreg.h
index 9c9a96643412d,d9aa76d08e13a..9123ecf6b9936
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@@ -1129,9 -1129,7 +1129,7 @@@
  #define gicr_insn(insn)			read_sysreg_s(GICV5_OP_GICR_##insn)
  #define gic_insn(v, insn)		write_sysreg_s(v, GICV5_OP_GIC_##insn)
  
- #define ARM64_FEATURE_FIELD_BITS	4
- 
 -#ifdef __ASSEMBLY__
 +#ifdef __ASSEMBLER__
  
  	.macro	mrs_s, rt, sreg
  	 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt))
diff --cc tools/arch/arm64/include/asm/sysreg.h
index 10c457d468e82,0f60b68eac1bf..178b7322bf049
--- a/tools/arch/arm64/include/asm/sysreg.h
+++ b/tools/arch/arm64/include/asm/sysreg.h
@@@ -1078,9 -1078,7 +1078,7 @@@
  #define GCS_CAP(x)	((((unsigned long)x) & GCS_CAP_ADDR_MASK) | \
  					       GCS_CAP_VALID_TOKEN)
  
- #define ARM64_FEATURE_FIELD_BITS	4
- 
 -#ifdef __ASSEMBLY__
 +#ifdef __ASSEMBLER__
  
  	.macro	mrs_s, rt, sreg
  	 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt))