From: Greg Kroah-Hartman Date: Wed, 26 Oct 2022 17:02:10 +0000 (+0200) Subject: 4.14-stable patches X-Git-Tag: v5.10.151~46 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=54466bc7aaa38e1542d967f4dfc9d3cfb5e19d26;p=thirdparty%2Fkernel%2Fstable-queue.git 4.14-stable patches added patches: arm64-errata-remove-aes-hwcap-for-compat-tasks.patch r8152-add-pid-for-the-lenovo-onelink-dock.patch --- diff --git a/queue-4.14/arm64-errata-remove-aes-hwcap-for-compat-tasks.patch b/queue-4.14/arm64-errata-remove-aes-hwcap-for-compat-tasks.patch new file mode 100644 index 00000000000..3f4632b0d5a --- /dev/null +++ b/queue-4.14/arm64-errata-remove-aes-hwcap-for-compat-tasks.patch @@ -0,0 +1,154 @@ +From 44b3834b2eed595af07021b1c64e6f9bc396398b Mon Sep 17 00:00:00 2001 +From: James Morse +Date: Thu, 14 Jul 2022 17:15:23 +0100 +Subject: arm64: errata: Remove AES hwcap for COMPAT tasks + +From: James Morse + +commit 44b3834b2eed595af07021b1c64e6f9bc396398b upstream. + +Cortex-A57 and Cortex-A72 have an erratum where an interrupt that +occurs between a pair of AES instructions in aarch32 mode may corrupt +the ELR. The task will subsequently produce the wrong AES result. + +The AES instructions are part of the cryptographic extensions, which are +optional. User-space software will detect the support for these +instructions from the hwcaps. If the platform doesn't support these +instructions a software implementation should be used. + +Remove the hwcap bits on affected parts to indicate user-space should +not use the AES instructions. + +Acked-by: Ard Biesheuvel +Signed-off-by: James Morse +Link: https://lore.kernel.org/r/20220714161523.279570-3-james.morse@arm.com +Signed-off-by: Will Deacon +[florian: resolved conflicts in arch/arm64/tools/cpucaps and cpu_errata.c] +Signed-off-by: Florian Fainelli +Signed-off-by: Greg Kroah-Hartman +--- + Documentation/arm64/silicon-errata.txt | 2 ++ + arch/arm64/Kconfig | 16 ++++++++++++++++ + arch/arm64/include/asm/cpucaps.h | 3 ++- + arch/arm64/kernel/cpu_errata.c | 16 ++++++++++++++++ + arch/arm64/kernel/cpufeature.c | 13 ++++++++++++- + 5 files changed, 48 insertions(+), 2 deletions(-) + +--- a/Documentation/arm64/silicon-errata.txt ++++ b/Documentation/arm64/silicon-errata.txt +@@ -53,7 +53,9 @@ stable kernels. + | ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 | + | ARM | Cortex-A57 | #852523 | N/A | + | ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 | ++| ARM | Cortex-A57 | #1742098 | ARM64_ERRATUM_1742098 | + | ARM | Cortex-A72 | #853709 | N/A | ++| ARM | Cortex-A72 | #1655431 | ARM64_ERRATUM_1742098 | + | ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 | + | ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 | + | ARM | Cortex-A76 | #1188873 | ARM64_ERRATUM_1188873 | +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -472,6 +472,22 @@ config ARM64_ERRATUM_1188873 + + If unsure, say Y. + ++config ARM64_ERRATUM_1742098 ++ bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" ++ depends on COMPAT ++ default y ++ help ++ This option removes the AES hwcap for aarch32 user-space to ++ workaround erratum 1742098 on Cortex-A57 and Cortex-A72. ++ ++ Affected parts may corrupt the AES state if an interrupt is ++ taken between a pair of AES instructions. These instructions ++ are only present if the cryptography extensions are present. ++ All software should have a fallback implementation for CPUs ++ that don't implement the cryptography extensions. ++ ++ If unsure, say Y. ++ + config CAVIUM_ERRATUM_22375 + bool "Cavium erratum 22375, 24313" + default y +--- a/arch/arm64/include/asm/cpucaps.h ++++ b/arch/arm64/include/asm/cpucaps.h +@@ -47,7 +47,8 @@ + #define ARM64_SSBS 27 + #define ARM64_WORKAROUND_1188873 28 + #define ARM64_SPECTRE_BHB 29 ++#define ARM64_WORKAROUND_1742098 30 + +-#define ARM64_NCAPS 30 ++#define ARM64_NCAPS 31 + + #endif /* __ASM_CPUCAPS_H */ +--- a/arch/arm64/kernel/cpu_errata.c ++++ b/arch/arm64/kernel/cpu_errata.c +@@ -576,6 +576,14 @@ check_branch_predictor(const struct arm6 + return (need_wa > 0); + } + ++#ifdef CONFIG_ARM64_ERRATUM_1742098 ++static struct midr_range broken_aarch32_aes[] = { ++ MIDR_RANGE(MIDR_CORTEX_A57, 0, 1, 0xf, 0xf), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), ++ {}, ++}; ++#endif ++ + const struct arm64_cpu_capabilities arm64_errata[] = { + #if defined(CONFIG_ARM64_ERRATUM_826319) || \ + defined(CONFIG_ARM64_ERRATUM_827319) || \ +@@ -741,6 +749,14 @@ const struct arm64_cpu_capabilities arm6 + .matches = is_spectre_bhb_affected, + .cpu_enable = spectre_bhb_enable_mitigation, + }, ++#ifdef CONFIG_ARM64_ERRATUM_1742098 ++ { ++ .desc = "ARM erratum 1742098", ++ .capability = ARM64_WORKAROUND_1742098, ++ CAP_MIDR_RANGE_LIST(broken_aarch32_aes), ++ .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, ++ }, ++#endif + { + } + }; +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -30,6 +30,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -1010,6 +1011,14 @@ static void cpu_enable_ssbs(const struct + } + #endif /* CONFIG_ARM64_SSBD */ + ++static void elf_hwcap_fixup(void) ++{ ++#ifdef CONFIG_ARM64_ERRATUM_1742098 ++ if (cpus_have_const_cap(ARM64_WORKAROUND_1742098)) ++ compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; ++#endif /* ARM64_ERRATUM_1742098 */ ++} ++ + static const struct arm64_cpu_capabilities arm64_features[] = { + { + .desc = "GIC system register CPU interface", +@@ -1588,8 +1597,10 @@ void __init setup_cpu_features(void) + mark_const_caps_ready(); + setup_elf_hwcaps(arm64_elf_hwcaps); + +- if (system_supports_32bit_el0()) ++ if (system_supports_32bit_el0()) { + setup_elf_hwcaps(compat_elf_hwcaps); ++ elf_hwcap_fixup(); ++ } + + /* Advertise that we have computed the system capabilities */ + set_sys_caps_initialised(); diff --git a/queue-4.14/r8152-add-pid-for-the-lenovo-onelink-dock.patch b/queue-4.14/r8152-add-pid-for-the-lenovo-onelink-dock.patch new file mode 100644 index 00000000000..b8b4c3fb7d8 --- /dev/null +++ b/queue-4.14/r8152-add-pid-for-the-lenovo-onelink-dock.patch @@ -0,0 +1,56 @@ +From 1bd3a383075c64d638e65d263c9267b08ee7733c Mon Sep 17 00:00:00 2001 +From: Jean-Francois Le Fillatre +Date: Wed, 24 Aug 2022 21:14:36 +0200 +Subject: r8152: add PID for the Lenovo OneLink+ Dock + +From: Jean-Francois Le Fillatre + +commit 1bd3a383075c64d638e65d263c9267b08ee7733c upstream. + +The Lenovo OneLink+ Dock contains an RTL8153 controller that behaves as +a broken CDC device by default. Add the custom Lenovo PID to the r8152 +driver to support it properly. + +Also, systems compatible with this dock provide a BIOS option to enable +MAC address passthrough (as per Lenovo document "ThinkPad Docking +Solutions 2017"). Add the custom PID to the MAC passthrough list too. + +Tested on a ThinkPad 13 1st gen with the expected results: + +passthrough disabled: Invalid header when reading pass-thru MAC addr +passthrough enabled: Using pass-thru MAC addr XX:XX:XX:XX:XX:XX + +Signed-off-by: Jean-Francois Le Fillatre +Signed-off-by: David S. Miller +Signed-off-by: Greg Kroah-Hartman +--- + drivers/net/usb/cdc_ether.c | 7 +++++++ + drivers/net/usb/r8152.c | 1 + + 2 files changed, 8 insertions(+) + +--- a/drivers/net/usb/cdc_ether.c ++++ b/drivers/net/usb/cdc_ether.c +@@ -777,6 +777,13 @@ static const struct usb_device_id produc + }, + #endif + ++/* Lenovo ThinkPad OneLink+ Dock (based on Realtek RTL8153) */ ++{ ++ USB_DEVICE_AND_INTERFACE_INFO(LENOVO_VENDOR_ID, 0x3054, USB_CLASS_COMM, ++ USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE), ++ .driver_info = 0, ++}, ++ + /* ThinkPad USB-C Dock (based on Realtek RTL8153) */ + { + USB_DEVICE_AND_INTERFACE_INFO(LENOVO_VENDOR_ID, 0x3062, USB_CLASS_COMM, +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -5312,6 +5312,7 @@ static const struct usb_device_id rtl815 + {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)}, + {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, + {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, ++ {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3054)}, + {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)}, + {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)}, + {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, diff --git a/queue-4.14/series b/queue-4.14/series index 241b960b855..c1521a1ae02 100644 --- a/queue-4.14/series +++ b/queue-4.14/series @@ -4,3 +4,5 @@ x86-microcode-amd-apply-the-patch-early-on-every-logical-thread.patch ata-ahci-imx-fix-module_alias.patch ata-ahci-match-em_max_slots-with-sata_pmp_max_ports.patch kvm-arm64-vgic-fix-exit-condition-in-scan_its_table.patch +arm64-errata-remove-aes-hwcap-for-compat-tasks.patch +r8152-add-pid-for-the-lenovo-onelink-dock.patch