From: Julian Seward Date: Sun, 30 Jan 2005 19:52:28 +0000 (+0000) Subject: Half-hearted attempt to make instruction disassembly print more X-Git-Tag: svn/VALGRIND_3_0_1^2~555 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=5552912cf3bab676ac2fe6aeb0de3608aed6f0d4;p=thirdparty%2Fvalgrind.git Half-hearted attempt to make instruction disassembly print more closely to the syntax emitted by gcc, to assist in (semi-)automated testing of the front end. git-svn-id: svn://svn.valgrind.org/vex/trunk@779 --- diff --git a/VEX/priv/guest-amd64/toIR.c b/VEX/priv/guest-amd64/toIR.c index 61a61fc429..2b86862e49 100644 --- a/VEX/priv/guest-amd64/toIR.c +++ b/VEX/priv/guest-amd64/toIR.c @@ -445,9 +445,12 @@ IRBB* bbToIR_AMD64 ( UChar* amd64code, } guest_rip_curr_instr = guest_rip_bbstart + delta; - +vex_traceflags = VEX_TRACE_FE; +if (amd64code[delta] != 0xC3) +vex_printf("LALALA "); dres = disInstr( resteerOK, chase_into_ok, delta, subarch_guest, &size, &guest_next ); +vex_traceflags = 0; insn_verbose = False; /* Print the resulting IR, if needed. */ @@ -1434,19 +1437,19 @@ static HChar* name_AMD64Condcode ( AMD64Condcode cond ) case AMD64CondO: return "o"; case AMD64CondNO: return "no"; case AMD64CondB: return "b"; - case AMD64CondNB: return "nb"; - case AMD64CondZ: return "z"; - case AMD64CondNZ: return "nz"; + case AMD64CondNB: return "ae"; /*"nb";*/ + case AMD64CondZ: return "e"; /*"z";*/ + case AMD64CondNZ: return "ne"; /*"nz";*/ case AMD64CondBE: return "be"; - case AMD64CondNBE: return "nbe"; + case AMD64CondNBE: return "a"; /*"nbe";*/ case AMD64CondS: return "s"; case AMD64CondNS: return "ns"; case AMD64CondP: return "p"; case AMD64CondNP: return "np"; case AMD64CondL: return "l"; - case AMD64CondNL: return "nl"; + case AMD64CondNL: return "ge"; /*"nl";*/ case AMD64CondLE: return "le"; - case AMD64CondNLE: return "nle"; + case AMD64CondNLE: return "g"; /*"nle";*/ case AMD64CondAlways: return "ALWAYS"; default: vpanic("name_AMD64Condcode"); } @@ -1563,7 +1566,7 @@ static HChar* nameGrp2 ( Int opc_aux ) { static HChar* grp2_names[8] = { "rol", "ror", "rcl", "rcr", "shl", "shr", "shl", "sar" }; - if (opc_aux < 0 || opc_aux > 7) vpanic("nameGrp2(x86)"); + if (opc_aux < 0 || opc_aux > 7) vpanic("nameGrp2(amd64)"); return grp2_names[opc_aux]; } @@ -1846,7 +1849,7 @@ IRTemp disAMode ( Int* len, Prefix pfx, ULong delta, HChar* buf ) /* ! 14 */ case 0x15: case 0x16: case 0x17: { UChar rm = and8(mod_reg_rm, 7); ULong d = getSDisp32(delta); - DIS(buf, "%s0x%llx(%s)", sorbTxt(pfx), d, nameIRegB(pfx,8,rm)); + DIS(buf, "%s%lld(%s)", sorbTxt(pfx), d, nameIRegB(pfx,8,rm)); *len = 5; return disAMode_copy2tmp( handleSegOverride(pfx, @@ -1898,9 +1901,15 @@ IRTemp disAMode ( Int* len, Prefix pfx, ULong delta, HChar* buf ) delta++; if ((!index_is_SP) && (!base_is_BPor13)) { - DIS(buf, "%s(%s,%s,%d)", sorbTxt(pfx), - nameIRegB(pfx,8,base_r), - nameIRegX(pfx,8,index_r), 1<