From: Sasha Levin Date: Mon, 12 Aug 2024 01:09:16 +0000 (-0400) Subject: Fixes for 5.15 X-Git-Tag: v6.1.105~99 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=5739803bf0745dfe63a83dc6249903c3a3be2261;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 5.15 Signed-off-by: Sasha Levin --- diff --git a/queue-5.15/alsa-usb-audio-re-add-scratchamp-quirk-entries.patch b/queue-5.15/alsa-usb-audio-re-add-scratchamp-quirk-entries.patch new file mode 100644 index 00000000000..2b914773efd --- /dev/null +++ b/queue-5.15/alsa-usb-audio-re-add-scratchamp-quirk-entries.patch @@ -0,0 +1,44 @@ +From 544ebeddde77fee8df4008f57f4de6e461d28381 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 8 Aug 2024 10:18:01 +0200 +Subject: ALSA: usb-audio: Re-add ScratchAmp quirk entries + +From: Takashi Iwai + +[ Upstream commit 03898691d42e0170e7d00f07cbe21ce0e9f3a8fa ] + +At the code refactoring of USB-audio quirk handling, I assumed that +the quirk entries of Stanton ScratchAmp devices were only about the +device name, and moved them completely into the rename table. +But it seems that the device requires the quirk entry so that it's +probed by the driver itself. + +This re-adds back the quirk entries of ScratchAmp, but in a +minimalistic manner. + +Fixes: 5436f59bc5bc ("ALSA: usb-audio: Move device rename and profile quirks to an internal table") +Link: https://patch.msgid.link/20240808081803.22300-1-tiwai@suse.de +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/usb/quirks-table.h | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h +index 6d332c9eb4445..b03d671f218d6 100644 +--- a/sound/usb/quirks-table.h ++++ b/sound/usb/quirks-table.h +@@ -2594,6 +2594,10 @@ YAMAHA_DEVICE(0x7010, "UB99"), + } + }, + ++/* Stanton ScratchAmp */ ++{ USB_DEVICE(0x103d, 0x0100) }, ++{ USB_DEVICE(0x103d, 0x0101) }, ++ + /* Novation EMS devices */ + { + USB_DEVICE_VENDOR_SPEC(0x1235, 0x0001), +-- +2.43.0 + diff --git a/queue-5.15/arm64-add-neoverse-v2-part.patch b/queue-5.15/arm64-add-neoverse-v2-part.patch new file mode 100644 index 00000000000..9bc91907896 --- /dev/null +++ b/queue-5.15/arm64-add-neoverse-v2-part.patch @@ -0,0 +1,45 @@ +From a08b46ab30842b7ef822efadaa6e64788c8c630a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:09:22 +0100 +Subject: arm64: Add Neoverse-V2 part + +From: Besar Wicaksono + +[ Upstream commit f4d9d9dcc70b96b5e5d7801bd5fbf8491b07b13d ] + +Add the part number and MIDR for Neoverse-V2 + +Signed-off-by: Besar Wicaksono +Reviewed-by: James Clark +Link: https://lore.kernel.org/r/20240109192310.16234-2-bwicaksono@nvidia.com +Signed-off-by: Will Deacon +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index 3656bbbb7c7b6..d6d3f15c80aae 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -85,6 +85,7 @@ + #define ARM_CPU_PART_CORTEX_X2 0xD48 + #define ARM_CPU_PART_NEOVERSE_N2 0xD49 + #define ARM_CPU_PART_CORTEX_A78C 0xD4B ++#define ARM_CPU_PART_NEOVERSE_V2 0xD4F + + #define APM_CPU_PART_POTENZA 0x000 + +@@ -139,6 +140,7 @@ + #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) + #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) ++#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +-- +2.43.0 + diff --git a/queue-5.15/arm64-barrier-restore-spec_bar-macro.patch b/queue-5.15/arm64-barrier-restore-spec_bar-macro.patch new file mode 100644 index 00000000000..9a2fea9c6d7 --- /dev/null +++ b/queue-5.15/arm64-barrier-restore-spec_bar-macro.patch @@ -0,0 +1,47 @@ +From b4b37c4707232acab500fee74e60c3539f030954 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:09:23 +0100 +Subject: arm64: barrier: Restore spec_bar() macro + +From: Mark Rutland + +[ Upstream commit ebfc726eae3f31bdb5fae1bbd74ef235d71046ca ] + +Upcoming errata workarounds will need to use SB from C code. Restore the +spec_bar() macro so that we can use SB. + +This is effectively a revert of commit: + + 4f30ba1cce36d413 ("arm64: barrier: Remove spec_bar() macro") + +Signed-off-by: Mark Rutland +Cc: Catalin Marinas +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240508081400.235362-2-mark.rutland@arm.com +Signed-off-by: Will Deacon +[ Mark: fix conflict ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/barrier.h | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h +index 1c5a005984582..6e3f4eea1f34d 100644 +--- a/arch/arm64/include/asm/barrier.h ++++ b/arch/arm64/include/asm/barrier.h +@@ -26,6 +26,10 @@ + #define __tsb_csync() asm volatile("hint #18" : : : "memory") + #define csdb() asm volatile("hint #20" : : : "memory") + ++#define spec_bar() asm volatile(ALTERNATIVE("dsb nsh\nisb\n", \ ++ SB_BARRIER_INSN"nop\n", \ ++ ARM64_HAS_SB)) ++ + #ifdef CONFIG_ARM64_PSEUDO_NMI + #define pmr_sync() \ + do { \ +-- +2.43.0 + diff --git a/queue-5.15/arm64-cpufeature-force-hwcap-to-be-based-on-the-sysr.patch b/queue-5.15/arm64-cpufeature-force-hwcap-to-be-based-on-the-sysr.patch new file mode 100644 index 00000000000..c6359d8698f --- /dev/null +++ b/queue-5.15/arm64-cpufeature-force-hwcap-to-be-based-on-the-sysr.patch @@ -0,0 +1,99 @@ +From 3f0d239eb82c07864069dd4869834a102dd2bc2b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:09:21 +0100 +Subject: arm64: cpufeature: Force HWCAP to be based on the sysreg visible to + user-space + +From: James Morse + +[ Upstream commit 237405ebef580a7352a52129b2465c117145eafa ] + +arm64 advertises hardware features to user-space via HWCAPs, and by +emulating access to the CPUs id registers. The cpufeature code has a +sanitised system-wide view of an id register, and a sanitised user-space +view of an id register, where some features use their 'safe' value +instead of the hardware value. + +It is currently possible for a HWCAP to be advertised where the user-space +view of the id register does not show the feature as supported. +Erratum workaround need to remove both the HWCAP, and the feature from +the user-space view of the id register. This involves duplicating the +code, and spreading it over cpufeature.c and cpu_errata.c. + +Make the HWCAP code use the user-space view of id registers. This ensures +the values never diverge, and allows erratum workaround to remove HWCAP +by modifying the user-space view of the id register. + +Signed-off-by: James Morse +Reviewed-by: Suzuki K Poulose +Link: https://lore.kernel.org/r/20220909165938.3931307-2-james.morse@arm.com +Signed-off-by: Catalin Marinas +[ Mark: fixup lack of 'width' parameter ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/kernel/cpufeature.c | 36 +++++++++++++++++++++++++++------- + 1 file changed, 29 insertions(+), 7 deletions(-) + +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index f17d6cdea2605..1bb55f4a3421d 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -1319,17 +1319,39 @@ feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) + return val >= entry->min_field_value; + } + +-static bool +-has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) ++static u64 ++read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) + { +- u64 val; +- + WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); + if (scope == SCOPE_SYSTEM) +- val = read_sanitised_ftr_reg(entry->sys_reg); ++ return read_sanitised_ftr_reg(entry->sys_reg); + else +- val = __read_sysreg_by_encoding(entry->sys_reg); ++ return __read_sysreg_by_encoding(entry->sys_reg); ++} ++ ++static bool ++has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) ++{ ++ int mask; ++ struct arm64_ftr_reg *regp; ++ u64 val = read_scoped_sysreg(entry, scope); ++ ++ regp = get_arm64_ftr_reg(entry->sys_reg); ++ if (!regp) ++ return false; ++ ++ mask = cpuid_feature_extract_unsigned_field(regp->user_mask, ++ entry->field_pos); ++ if (!mask) ++ return false; ++ ++ return feature_matches(val, entry); ++} + ++static bool ++has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) ++{ ++ u64 val = read_scoped_sysreg(entry, scope); + return feature_matches(val, entry); + } + +@@ -2376,7 +2398,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { + }; + + #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ +- .matches = has_cpuid_feature, \ ++ .matches = has_user_cpuid_feature, \ + .sys_reg = reg, \ + .field_pos = field, \ + .sign = s, \ +-- +2.43.0 + diff --git a/queue-5.15/arm64-cputype-add-cortex-a720-definitions.patch b/queue-5.15/arm64-cputype-add-cortex-a720-definitions.patch new file mode 100644 index 00000000000..f0589ac7dea --- /dev/null +++ b/queue-5.15/arm64-cputype-add-cortex-a720-definitions.patch @@ -0,0 +1,52 @@ +From 76b659e7c33f3b1d8be0b284e566b98a9d73b625 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:09:28 +0100 +Subject: arm64: cputype: Add Cortex-A720 definitions + +From: Mark Rutland + +[ Upstream commit add332c40328cf06fe35e4b3cde8ec315c4629e5 ] + +Add cputype definitions for Cortex-A720. These will be used for errata +detection in subsequent patches. + +These values can be found in Table A-186 ("MIDR_EL1 bit descriptions") +in issue 0002-05 of the Cortex-A720 TRM, which can be found at: + + https://developer.arm.com/documentation/102530/0002/?lang=en + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240603111812.1514101-3-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index e246d7fad17a9..edfd6ac14a127 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -87,6 +87,7 @@ + #define ARM_CPU_PART_CORTEX_A78C 0xD4B + #define ARM_CPU_PART_CORTEX_X3 0xD4E + #define ARM_CPU_PART_NEOVERSE_V2 0xD4F ++#define ARM_CPU_PART_CORTEX_A720 0xD81 + #define ARM_CPU_PART_CORTEX_X4 0xD82 + #define ARM_CPU_PART_NEOVERSE_V3 0xD84 + +@@ -145,6 +146,7 @@ + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) + #define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3) + #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) ++#define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720) + #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) + #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) +-- +2.43.0 + diff --git a/queue-5.15/arm64-cputype-add-cortex-a725-definitions.patch b/queue-5.15/arm64-cputype-add-cortex-a725-definitions.patch new file mode 100644 index 00000000000..5e8c017b9b9 --- /dev/null +++ b/queue-5.15/arm64-cputype-add-cortex-a725-definitions.patch @@ -0,0 +1,54 @@ +From badfaf28d9a3de7c76c32ff2fd3c9d3b7687834d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:09:33 +0100 +Subject: arm64: cputype: Add Cortex-A725 definitions + +From: Mark Rutland + +[ Upstream commit 9ef54a384526911095db465e77acc1cb5266b32c ] + +Add cputype definitions for Cortex-A725. These will be used for errata +detection in subsequent patches. + +These values can be found in the Cortex-A725 TRM: + + https://developer.arm.com/documentation/107652/0001/ + +... in table A-247 ("MIDR_EL1 bit descriptions"). + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Reviewed-by: Anshuman Khandual +Link: https://lore.kernel.org/r/20240801101803.1982459-3-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index d1f5ec68ec726..59f135b280a8a 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -92,6 +92,7 @@ + #define ARM_CPU_PART_CORTEX_X4 0xD82 + #define ARM_CPU_PART_NEOVERSE_V3 0xD84 + #define ARM_CPU_PART_CORTEX_X925 0xD85 ++#define ARM_CPU_PART_CORTEX_A725 0xD87 + + #define APM_CPU_PART_POTENZA 0x000 + +@@ -153,6 +154,7 @@ + #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) + #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) + #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925) ++#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +-- +2.43.0 + diff --git a/queue-5.15/arm64-cputype-add-cortex-x1c-definitions.patch b/queue-5.15/arm64-cputype-add-cortex-x1c-definitions.patch new file mode 100644 index 00000000000..4e9446f4bc1 --- /dev/null +++ b/queue-5.15/arm64-cputype-add-cortex-x1c-definitions.patch @@ -0,0 +1,54 @@ +From ecd4763458565b9d4c4e7801f419cb1c0d5803ae Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:09:32 +0100 +Subject: arm64: cputype: Add Cortex-X1C definitions + +From: Mark Rutland + +[ Upstream commit 58d245e03c324d083a0ec3b9ab8ebd46ec9848d7 ] + +Add cputype definitions for Cortex-X1C. These will be used for errata +detection in subsequent patches. + +These values can be found in the Cortex-X1C TRM: + + https://developer.arm.com/documentation/101968/0002/ + +... in section B2.107 ("MIDR_EL1, Main ID Register, EL1"). + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Reviewed-by: Anshuman Khandual +Link: https://lore.kernel.org/r/20240801101803.1982459-2-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index 95492fa88a244..d1f5ec68ec726 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -85,6 +85,7 @@ + #define ARM_CPU_PART_CORTEX_X2 0xD48 + #define ARM_CPU_PART_NEOVERSE_N2 0xD49 + #define ARM_CPU_PART_CORTEX_A78C 0xD4B ++#define ARM_CPU_PART_CORTEX_X1C 0xD4C + #define ARM_CPU_PART_CORTEX_X3 0xD4E + #define ARM_CPU_PART_NEOVERSE_V2 0xD4F + #define ARM_CPU_PART_CORTEX_A720 0xD81 +@@ -145,6 +146,7 @@ + #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) + #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) ++#define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C) + #define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3) + #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) + #define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720) +-- +2.43.0 + diff --git a/queue-5.15/arm64-cputype-add-cortex-x3-definitions.patch b/queue-5.15/arm64-cputype-add-cortex-x3-definitions.patch new file mode 100644 index 00000000000..53fc8887444 --- /dev/null +++ b/queue-5.15/arm64-cputype-add-cortex-x3-definitions.patch @@ -0,0 +1,52 @@ +From 5bb9e36d291a23d7dfb4d2b38c8df2f4f4562a82 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:09:27 +0100 +Subject: arm64: cputype: Add Cortex-X3 definitions + +From: Mark Rutland + +[ Upstream commit be5a6f238700f38b534456608588723fba96c5ab ] + +Add cputype definitions for Cortex-X3. These will be used for errata +detection in subsequent patches. + +These values can be found in Table A-263 ("MIDR_EL1 bit descriptions") +in issue 07 of the Cortex-X3 TRM, which can be found at: + + https://developer.arm.com/documentation/101593/0102/?lang=en + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240603111812.1514101-2-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index 17fb978191d68..e246d7fad17a9 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -85,6 +85,7 @@ + #define ARM_CPU_PART_CORTEX_X2 0xD48 + #define ARM_CPU_PART_NEOVERSE_N2 0xD49 + #define ARM_CPU_PART_CORTEX_A78C 0xD4B ++#define ARM_CPU_PART_CORTEX_X3 0xD4E + #define ARM_CPU_PART_NEOVERSE_V2 0xD4F + #define ARM_CPU_PART_CORTEX_X4 0xD82 + #define ARM_CPU_PART_NEOVERSE_V3 0xD84 +@@ -142,6 +143,7 @@ + #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) + #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) ++#define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3) + #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) + #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) + #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) +-- +2.43.0 + diff --git a/queue-5.15/arm64-cputype-add-cortex-x4-definitions.patch b/queue-5.15/arm64-cputype-add-cortex-x4-definitions.patch new file mode 100644 index 00000000000..f60a6da6bb1 --- /dev/null +++ b/queue-5.15/arm64-cputype-add-cortex-x4-definitions.patch @@ -0,0 +1,53 @@ +From 59d5a80cadb5f76ba468b58a9017677795bcab43 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:09:24 +0100 +Subject: arm64: cputype: Add Cortex-X4 definitions + +From: Mark Rutland + +[ Upstream commit 02a0a04676fa7796d9cbc9eb5ca120aaa194d2dd ] + +Add cputype definitions for Cortex-X4. These will be used for errata +detection in subsequent patches. + +These values can be found in Table B-249 ("MIDR_EL1 bit descriptions") +in issue 0002-05 of the Cortex-X4 TRM, which can be found at: + + https://developer.arm.com/documentation/102484/0002/?lang=en + +Signed-off-by: Mark Rutland +Cc: Catalin Marinas +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240508081400.235362-3-mark.rutland@arm.com +Signed-off-by: Will Deacon +[ Mark: fix conflict (dealt with upstream via a later merge) ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index d6d3f15c80aae..d222cd4983944 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -86,6 +86,7 @@ + #define ARM_CPU_PART_NEOVERSE_N2 0xD49 + #define ARM_CPU_PART_CORTEX_A78C 0xD4B + #define ARM_CPU_PART_NEOVERSE_V2 0xD4F ++#define ARM_CPU_PART_CORTEX_X4 0xD82 + + #define APM_CPU_PART_POTENZA 0x000 + +@@ -141,6 +142,7 @@ + #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) + #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) ++#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +-- +2.43.0 + diff --git a/queue-5.15/arm64-cputype-add-cortex-x925-definitions.patch b/queue-5.15/arm64-cputype-add-cortex-x925-definitions.patch new file mode 100644 index 00000000000..a1c2a6de320 --- /dev/null +++ b/queue-5.15/arm64-cputype-add-cortex-x925-definitions.patch @@ -0,0 +1,52 @@ +From 4a946e5283e18f84883442038232137294cfe73f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:09:29 +0100 +Subject: arm64: cputype: Add Cortex-X925 definitions + +From: Mark Rutland + +[ Upstream commit fd2ff5f0b320f418288e7a1f919f648fbc8a0dfc ] + +Add cputype definitions for Cortex-X925. These will be used for errata +detection in subsequent patches. + +These values can be found in Table A-285 ("MIDR_EL1 bit descriptions") +in issue 0001-05 of the Cortex-X925 TRM, which can be found at: + + https://developer.arm.com/documentation/102807/0001/?lang=en + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240603111812.1514101-4-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index edfd6ac14a127..95492fa88a244 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -90,6 +90,7 @@ + #define ARM_CPU_PART_CORTEX_A720 0xD81 + #define ARM_CPU_PART_CORTEX_X4 0xD82 + #define ARM_CPU_PART_NEOVERSE_V3 0xD84 ++#define ARM_CPU_PART_CORTEX_X925 0xD85 + + #define APM_CPU_PART_POTENZA 0x000 + +@@ -149,6 +150,7 @@ + #define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720) + #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) + #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) ++#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +-- +2.43.0 + diff --git a/queue-5.15/arm64-cputype-add-neoverse-v3-definitions.patch b/queue-5.15/arm64-cputype-add-neoverse-v3-definitions.patch new file mode 100644 index 00000000000..031e93d6699 --- /dev/null +++ b/queue-5.15/arm64-cputype-add-neoverse-v3-definitions.patch @@ -0,0 +1,53 @@ +From ef5ca491014b14ed609c43e98957af2da405ee00 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:09:25 +0100 +Subject: arm64: cputype: Add Neoverse-V3 definitions + +From: Mark Rutland + +[ Upstream commit 0ce85db6c2141b7ffb95709d76fc55a27ff3cdc1 ] + +Add cputype definitions for Neoverse-V3. These will be used for errata +detection in subsequent patches. + +These values can be found in Table B-249 ("MIDR_EL1 bit descriptions") +in issue 0001-04 of the Neoverse-V3 TRM, which can be found at: + + https://developer.arm.com/documentation/107734/0001/?lang=en + +Signed-off-by: Mark Rutland +Cc: Catalin Marinas +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240508081400.235362-4-mark.rutland@arm.com +Signed-off-by: Will Deacon +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index d222cd4983944..17fb978191d68 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -87,6 +87,7 @@ + #define ARM_CPU_PART_CORTEX_A78C 0xD4B + #define ARM_CPU_PART_NEOVERSE_V2 0xD4F + #define ARM_CPU_PART_CORTEX_X4 0xD82 ++#define ARM_CPU_PART_NEOVERSE_V3 0xD84 + + #define APM_CPU_PART_POTENZA 0x000 + +@@ -143,6 +144,7 @@ + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) + #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) + #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) ++#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +-- +2.43.0 + diff --git a/queue-5.15/arm64-errata-add-workaround-for-arm-errata-3194386-a.patch b/queue-5.15/arm64-errata-add-workaround-for-arm-errata-3194386-a.patch new file mode 100644 index 00000000000..45de6859a8d --- /dev/null +++ b/queue-5.15/arm64-errata-add-workaround-for-arm-errata-3194386-a.patch @@ -0,0 +1,221 @@ +From 0a54951123b4dfe0f483af00a6bec791db5f8585 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:09:26 +0100 +Subject: arm64: errata: Add workaround for Arm errata 3194386 and 3312417 + +From: Mark Rutland + +[ Upstream commit 7187bb7d0b5c7dfa18ca82e9e5c75e13861b1d88 ] + +Cortex-X4 and Neoverse-V3 suffer from errata whereby an MSR to the SSBS +special-purpose register does not affect subsequent speculative +instructions, permitting speculative store bypassing for a window of +time. This is described in their Software Developer Errata Notice (SDEN) +documents: + +* Cortex-X4 SDEN v8.0, erratum 3194386: + https://developer.arm.com/documentation/SDEN-2432808/0800/ + +* Neoverse-V3 SDEN v6.0, erratum 3312417: + https://developer.arm.com/documentation/SDEN-2891958/0600/ + +To workaround these errata, it is necessary to place a speculation +barrier (SB) after MSR to the SSBS special-purpose register. This patch +adds the requisite SB after writes to SSBS within the kernel, and hides +the presence of SSBS from EL0 such that userspace software which cares +about SSBS will manipulate this via prctl(PR_GET_SPECULATION_CTRL, ...). + +Signed-off-by: Mark Rutland +Cc: Catalin Marinas +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240508081400.235362-5-mark.rutland@arm.com +Signed-off-by: Will Deacon +[ Mark: fix conflicts & renames, drop unneeded cpucaps.h, fold in user_feature_fixup() ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + Documentation/arm64/silicon-errata.rst | 4 +++ + arch/arm64/Kconfig | 41 ++++++++++++++++++++++++++ + arch/arm64/kernel/cpu_errata.c | 19 ++++++++++++ + arch/arm64/kernel/cpufeature.c | 12 ++++++++ + arch/arm64/kernel/proton-pack.c | 12 ++++++++ + arch/arm64/tools/cpucaps | 1 + + 6 files changed, 89 insertions(+) + +diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst +index df7c53102a5f9..33595bc79dea6 100644 +--- a/Documentation/arm64/silicon-errata.rst ++++ b/Documentation/arm64/silicon-errata.rst +@@ -108,6 +108,8 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-A710 | #2224489 | ARM64_ERRATUM_2224489 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-X4 | #3194386 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N1 | #1349291 | N/A | +@@ -120,6 +122,8 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_2253138 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3312417 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | MMU-500 | #841119,826419 | N/A | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | MMU-600 | #1076982,1209401| N/A | +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index 68874d3856b91..bc89287d38ed1 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -848,6 +848,47 @@ config ARM64_ERRATUM_2224489 + + If unsure, say Y. + ++config ARM64_WORKAROUND_SPECULATIVE_SSBS ++ bool ++ ++config ARM64_ERRATUM_3194386 ++ bool "Cortex-X4: 3194386: workaround for MSR SSBS not self-synchronizing" ++ select ARM64_WORKAROUND_SPECULATIVE_SSBS ++ default y ++ help ++ This option adds the workaround for ARM Cortex-X4 erratum 3194386. ++ ++ On affected cores "MSR SSBS, #0" instructions may not affect ++ subsequent speculative instructions, which may permit unexepected ++ speculative store bypassing. ++ ++ Work around this problem by placing a speculation barrier after ++ kernel changes to SSBS. The presence of the SSBS special-purpose ++ register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such ++ that userspace will use the PR_SPEC_STORE_BYPASS prctl to change ++ SSBS. ++ ++ If unsure, say Y. ++ ++config ARM64_ERRATUM_3312417 ++ bool "Neoverse-V3: 3312417: workaround for MSR SSBS not self-synchronizing" ++ select ARM64_WORKAROUND_SPECULATIVE_SSBS ++ default y ++ help ++ This option adds the workaround for ARM Neoverse-V3 erratum 3312417. ++ ++ On affected cores "MSR SSBS, #0" instructions may not affect ++ subsequent speculative instructions, which may permit unexepected ++ speculative store bypassing. ++ ++ Work around this problem by placing a speculation barrier after ++ kernel changes to SSBS. The presence of the SSBS special-purpose ++ register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such ++ that userspace will use the PR_SPEC_STORE_BYPASS prctl to change ++ SSBS. ++ ++ If unsure, say Y. ++ + config CAVIUM_ERRATUM_22375 + bool "Cavium erratum 22375, 24313" + default y +diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c +index 4f12d8c1e55b9..0cf60010a0825 100644 +--- a/arch/arm64/kernel/cpu_errata.c ++++ b/arch/arm64/kernel/cpu_errata.c +@@ -402,6 +402,18 @@ static struct midr_range trbe_write_out_of_range_cpus[] = { + }; + #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ + ++#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS ++static const struct midr_range erratum_spec_ssbs_list[] = { ++#ifdef CONFIG_ARM64_ERRATUM_3194386 ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), ++#endif ++#ifdef CONFIG_ARM64_ERRATUM_3312417 ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), ++#endif ++ {} ++}; ++#endif ++ + const struct arm64_cpu_capabilities arm64_errata[] = { + #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE + { +@@ -648,6 +660,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { + .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, + CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus), + }, ++#endif ++#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS ++ { ++ .desc = "ARM errata 3194386, 3312417", ++ .capability = ARM64_WORKAROUND_SPECULATIVE_SSBS, ++ ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list), ++ }, + #endif + { + } +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index 1bb55f4a3421d..299c9ac6bc818 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -1939,6 +1939,17 @@ static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) + } + #endif /* CONFIG_ARM64_MTE */ + ++static void user_feature_fixup(void) ++{ ++ if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { ++ struct arm64_ftr_reg *regp; ++ ++ regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); ++ if (regp) ++ regp->user_mask &= ~GENMASK(7, 4); /* SSBS */ ++ } ++} ++ + static void elf_hwcap_fixup(void) + { + #ifdef CONFIG_ARM64_ERRATUM_1742098 +@@ -2972,6 +2983,7 @@ void __init setup_cpu_features(void) + u32 cwg; + + setup_system_capabilities(); ++ user_feature_fixup(); + setup_elf_hwcaps(arm64_elf_hwcaps); + + if (system_supports_32bit_el0()) { +diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c +index 7515ed1f0669a..c0149af8c9e97 100644 +--- a/arch/arm64/kernel/proton-pack.c ++++ b/arch/arm64/kernel/proton-pack.c +@@ -558,6 +558,18 @@ static enum mitigation_state spectre_v4_enable_hw_mitigation(void) + + /* SCTLR_EL1.DSSBS was initialised to 0 during boot */ + set_pstate_ssbs(0); ++ ++ /* ++ * SSBS is self-synchronizing and is intended to affect subsequent ++ * speculative instructions, but some CPUs can speculate with a stale ++ * value of SSBS. ++ * ++ * Mitigate this with an unconditional speculation barrier, as CPUs ++ * could mis-speculate branches and bypass a conditional barrier. ++ */ ++ if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS)) ++ spec_bar(); ++ + return SPECTRE_MITIGATED; + } + +diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps +index fcaeec5a51258..e7f4ae17f31b0 100644 +--- a/arch/arm64/tools/cpucaps ++++ b/arch/arm64/tools/cpucaps +@@ -70,3 +70,4 @@ WORKAROUND_NVIDIA_CARMEL_CNP + WORKAROUND_QCOM_FALKOR_E1003 + WORKAROUND_REPEAT_TLBI + WORKAROUND_SPECULATIVE_AT ++WORKAROUND_SPECULATIVE_SSBS +-- +2.43.0 + diff --git a/queue-5.15/arm64-errata-expand-speculative-ssbs-workaround-agai.patch b/queue-5.15/arm64-errata-expand-speculative-ssbs-workaround-agai.patch new file mode 100644 index 00000000000..0598e4059f6 --- /dev/null +++ b/queue-5.15/arm64-errata-expand-speculative-ssbs-workaround-agai.patch @@ -0,0 +1,219 @@ +From b6e8285e32d4b5c8b2c23b66d4948d3da2c802e9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:09:34 +0100 +Subject: arm64: errata: Expand speculative SSBS workaround (again) + +From: Mark Rutland + +[ Upstream commit b0672bbe133ebb6f7be21fce1d742d52f25bcdc7 ] + +A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS +special-purpose register does not affect subsequent speculative +instructions, permitting speculative store bypassing for a window of +time. + +We worked around this for a number of CPUs in commits: + +* 7187bb7d0b5c7dfa ("arm64: errata: Add workaround for Arm errata 3194386 and 3312417") +* 75b3c43eab594bfb ("arm64: errata: Expand speculative SSBS workaround") + +Since then, similar errata have been published for a number of other Arm +Ltd CPUs, for which the same mitigation is sufficient. This is described +in their respective Software Developer Errata Notice (SDEN) documents: + +* Cortex-A76 (MP052) SDEN v31.0, erratum 3324349 + https://developer.arm.com/documentation/SDEN-885749/3100/ + +* Cortex-A77 (MP074) SDEN v19.0, erratum 3324348 + https://developer.arm.com/documentation/SDEN-1152370/1900/ + +* Cortex-A78 (MP102) SDEN v21.0, erratum 3324344 + https://developer.arm.com/documentation/SDEN-1401784/2100/ + +* Cortex-A78C (MP138) SDEN v16.0, erratum 3324346 + https://developer.arm.com/documentation/SDEN-1707916/1600/ + +* Cortex-A78C (MP154) SDEN v10.0, erratum 3324347 + https://developer.arm.com/documentation/SDEN-2004089/1000/ + +* Cortex-A725 (MP190) SDEN v5.0, erratum 3456106 + https://developer.arm.com/documentation/SDEN-2832921/0500/ + +* Cortex-X1 (MP077) SDEN v21.0, erratum 3324344 + https://developer.arm.com/documentation/SDEN-1401782/2100/ + +* Cortex-X1C (MP136) SDEN v16.0, erratum 3324346 + https://developer.arm.com/documentation/SDEN-1707914/1600/ + +* Neoverse-N1 (MP050) SDEN v32.0, erratum 3324349 + https://developer.arm.com/documentation/SDEN-885747/3200/ + +* Neoverse-V1 (MP076) SDEN v19.0, erratum 3324341 + https://developer.arm.com/documentation/SDEN-1401781/1900/ + +Note that due to the manner in which Arm develops IP and tracks errata, +some CPUs share a common erratum number and some CPUs have multiple +erratum numbers for the same HW issue. + +On parts without SB, it is necessary to use ISB for the workaround. The +spec_bar() macro used in the mitigation will expand to a "DSB SY; ISB" +sequence in this case, which is sufficient on all affected parts. + +Enable the existing mitigation by adding the relevant MIDRs to +erratum_spec_ssbs_list. The list is sorted alphanumerically (involving +moving Neoverse-V3 after Neoverse-V2) so that this is easy to audit and +potentially extend again in future. The Kconfig text is also updated to +clarify the set of affected parts and the mitigation. + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Reviewed-by: Anshuman Khandual +Acked-by: Will Deacon +Link: https://lore.kernel.org/r/20240801101803.1982459-4-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: fix conflicts in silicon-errata.rst ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + Documentation/arm64/silicon-errata.rst | 18 ++++++++++++++++++ + arch/arm64/Kconfig | 22 ++++++++++++++++------ + arch/arm64/kernel/cpu_errata.c | 11 ++++++++++- + 3 files changed, 44 insertions(+), 7 deletions(-) + +diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst +index 1740c0dfd5503..9868eb45c56a0 100644 +--- a/Documentation/arm64/silicon-errata.rst ++++ b/Documentation/arm64/silicon-errata.rst +@@ -96,8 +96,16 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A76 | #3324349 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A77 | #3324348 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A78 | #3324344 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A78C | #3324346,3324347| ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-A510 | #2441009 | ARM64_ERRATUM_2441009 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-A510 | #2457168 | ARM64_ERRATUM_2457168 | +@@ -112,6 +120,12 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-A720 | #3456091 | ARM64_ERRATUM_3194386 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-X1C | #3324346 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-X2 | #3324338 | ARM64_ERRATUM_3194386 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-X3 | #3324335 | ARM64_ERRATUM_3194386 | +@@ -126,6 +140,8 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Neoverse-N1 | #3324349 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 | +@@ -134,6 +150,8 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N2 | #3324339 | ARM64_ERRATUM_3194386 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Neoverse-V1 | #3324341 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 | +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index 91a956605925b..2d77e9269eb50 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -849,18 +849,28 @@ config ARM64_ERRATUM_2224489 + If unsure, say Y. + + config ARM64_ERRATUM_3194386 +- bool "Cortex-{A720,X4,X925}/Neoverse-V3: workaround for MSR SSBS not self-synchronizing" ++ bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" + default y + help + This option adds the workaround for the following errata: + ++ * ARM Cortex-A76 erratum 3324349 ++ * ARM Cortex-A77 erratum 3324348 ++ * ARM Cortex-A78 erratum 3324344 ++ * ARM Cortex-A78C erratum 3324346 ++ * ARM Cortex-A78C erratum 3324347 + * ARM Cortex-A710 erratam 3324338 + * ARM Cortex-A720 erratum 3456091 ++ * ARM Cortex-A725 erratum 3456106 ++ * ARM Cortex-X1 erratum 3324344 ++ * ARM Cortex-X1C erratum 3324346 + * ARM Cortex-X2 erratum 3324338 + * ARM Cortex-X3 erratum 3324335 + * ARM Cortex-X4 erratum 3194386 + * ARM Cortex-X925 erratum 3324334 ++ * ARM Neoverse-N1 erratum 3324349 + * ARM Neoverse N2 erratum 3324339 ++ * ARM Neoverse-V1 erratum 3324341 + * ARM Neoverse V2 erratum 3324336 + * ARM Neoverse-V3 erratum 3312417 + +@@ -868,11 +878,11 @@ config ARM64_ERRATUM_3194386 + subsequent speculative instructions, which may permit unexepected + speculative store bypassing. + +- Work around this problem by placing a speculation barrier after +- kernel changes to SSBS. The presence of the SSBS special-purpose +- register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such +- that userspace will use the PR_SPEC_STORE_BYPASS prctl to change +- SSBS. ++ Work around this problem by placing a Speculation Barrier (SB) or ++ Instruction Synchronization Barrier (ISB) after kernel changes to ++ SSBS. The presence of the SSBS special-purpose register is hidden ++ from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace ++ will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. + + If unsure, say Y. + +diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c +index f360ec1619bd5..c358bc1c2954e 100644 +--- a/arch/arm64/kernel/cpu_errata.c ++++ b/arch/arm64/kernel/cpu_errata.c +@@ -404,15 +404,24 @@ static struct midr_range trbe_write_out_of_range_cpus[] = { + + #ifdef CONFIG_ARM64_ERRATUM_3194386 + static const struct midr_range erratum_spec_ssbs_list[] = { ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A77), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), +- MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), + {} + }; + #endif +-- +2.43.0 + diff --git a/queue-5.15/arm64-errata-expand-speculative-ssbs-workaround.patch b/queue-5.15/arm64-errata-expand-speculative-ssbs-workaround.patch new file mode 100644 index 00000000000..9b54f38ed1f --- /dev/null +++ b/queue-5.15/arm64-errata-expand-speculative-ssbs-workaround.patch @@ -0,0 +1,167 @@ +From a6a068a79b7b3e004eca91ab768dd26e39b8610c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:09:31 +0100 +Subject: arm64: errata: Expand speculative SSBS workaround + +From: Mark Rutland + +[ Upstream commit 75b3c43eab594bfbd8184ec8ee1a6b820950819a ] + +A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS +special-purpose register does not affect subsequent speculative +instructions, permitting speculative store bypassing for a window of +time. + +We worked around this for Cortex-X4 and Neoverse-V3, in commit: + + 7187bb7d0b5c7dfa ("arm64: errata: Add workaround for Arm errata 3194386 and 3312417") + +... as per their Software Developer Errata Notice (SDEN) documents: + +* Cortex-X4 SDEN v8.0, erratum 3194386: + https://developer.arm.com/documentation/SDEN-2432808/0800/ + +* Neoverse-V3 SDEN v6.0, erratum 3312417: + https://developer.arm.com/documentation/SDEN-2891958/0600/ + +Since then, similar errata have been published for a number of other Arm Ltd +CPUs, for which the mitigation is the same. This is described in their +respective SDEN documents: + +* Cortex-A710 SDEN v19.0, errataum 3324338 + https://developer.arm.com/documentation/SDEN-1775101/1900/?lang=en + +* Cortex-A720 SDEN v11.0, erratum 3456091 + https://developer.arm.com/documentation/SDEN-2439421/1100/?lang=en + +* Cortex-X2 SDEN v19.0, erratum 3324338 + https://developer.arm.com/documentation/SDEN-1775100/1900/?lang=en + +* Cortex-X3 SDEN v14.0, erratum 3324335 + https://developer.arm.com/documentation/SDEN-2055130/1400/?lang=en + +* Cortex-X925 SDEN v8.0, erratum 3324334 + https://developer.arm.com/documentation/109108/800/?lang=en + +* Neoverse-N2 SDEN v17.0, erratum 3324339 + https://developer.arm.com/documentation/SDEN-1982442/1700/?lang=en + +* Neoverse-V2 SDEN v9.0, erratum 3324336 + https://developer.arm.com/documentation/SDEN-2332927/900/?lang=en + +Note that due to shared design lineage, some CPUs share the same erratum +number. + +Add these to the existing mitigation under CONFIG_ARM64_ERRATUM_3194386. +As listing all of the erratum IDs in the runtime description would be +unwieldy, this is reduced to: + + "SSBS not fully self-synchronizing" + +... matching the description of the errata in all of the SDENs. + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240603111812.1514101-6-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: fix conflicts and renames ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + Documentation/arm64/silicon-errata.rst | 14 ++++++++++++++ + arch/arm64/Kconfig | 9 ++++++++- + arch/arm64/kernel/cpu_errata.c | 9 ++++++++- + 3 files changed, 30 insertions(+), 2 deletions(-) + +diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst +index 13d77af92edf7..1740c0dfd5503 100644 +--- a/Documentation/arm64/silicon-errata.rst ++++ b/Documentation/arm64/silicon-errata.rst +@@ -108,8 +108,18 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-A710 | #2224489 | ARM64_ERRATUM_2224489 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A710 | #3324338 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-A720 | #3456091 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-X2 | #3324338 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-X3 | #3324335 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Cortex-X4 | #3194386 | ARM64_ERRATUM_3194386 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Cortex-X925 | #3324334 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N1 | #1349291 | N/A | +@@ -122,6 +132,10 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_2253138 | + +----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Neoverse-N2 | #3324339 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ ++| ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 | +++----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | MMU-500 | #841119,826419 | N/A | +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index 623b30c21c00d..91a956605925b 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -849,12 +849,19 @@ config ARM64_ERRATUM_2224489 + If unsure, say Y. + + config ARM64_ERRATUM_3194386 +- bool "Cortex-X4/Neoverse-V3: workaround for MSR SSBS not self-synchronizing" ++ bool "Cortex-{A720,X4,X925}/Neoverse-V3: workaround for MSR SSBS not self-synchronizing" + default y + help + This option adds the workaround for the following errata: + ++ * ARM Cortex-A710 erratam 3324338 ++ * ARM Cortex-A720 erratum 3456091 ++ * ARM Cortex-X2 erratum 3324338 ++ * ARM Cortex-X3 erratum 3324335 + * ARM Cortex-X4 erratum 3194386 ++ * ARM Cortex-X925 erratum 3324334 ++ * ARM Neoverse N2 erratum 3324339 ++ * ARM Neoverse V2 erratum 3324336 + * ARM Neoverse-V3 erratum 3312417 + + On affected cores "MSR SSBS, #0" instructions may not affect +diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c +index 0fe2d65e646fe..f360ec1619bd5 100644 +--- a/arch/arm64/kernel/cpu_errata.c ++++ b/arch/arm64/kernel/cpu_errata.c +@@ -404,8 +404,15 @@ static struct midr_range trbe_write_out_of_range_cpus[] = { + + #ifdef CONFIG_ARM64_ERRATUM_3194386 + static const struct midr_range erratum_spec_ssbs_list[] = { ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), + {} + }; + #endif +@@ -659,7 +666,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { + #endif + #ifdef CONFIG_ARM64_ERRATUM_3194386 + { +- .desc = "ARM errata 3194386, 3312417", ++ .desc = "SSBS not fully self-synchronizing", + .capability = ARM64_WORKAROUND_SPECULATIVE_SSBS, + ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list), + }, +-- +2.43.0 + diff --git a/queue-5.15/arm64-errata-unify-speculative-ssbs-errata-logic.patch b/queue-5.15/arm64-errata-unify-speculative-ssbs-errata-logic.patch new file mode 100644 index 00000000000..65339a6e7d1 --- /dev/null +++ b/queue-5.15/arm64-errata-unify-speculative-ssbs-errata-logic.patch @@ -0,0 +1,141 @@ +From ff3189206408d7c69183627bb3059f67c658e17c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:09:30 +0100 +Subject: arm64: errata: Unify speculative SSBS errata logic + +From: Mark Rutland + +[ Upstream commit ec768766608092087dfb5c1fc45a16a6f524dee2 ] + +Cortex-X4 erratum 3194386 and Neoverse-V3 erratum 3312417 are identical, +with duplicate Kconfig text and some unsightly ifdeffery. While we try +to share code behind CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS, having +separate options results in a fair amount of boilerplate code, and this +will only get worse as we expand the set of affected CPUs. + +To reduce this boilerplate, unify the two behind a common Kconfig +option. This removes the duplicate text and Kconfig logic, and removes +the need for the intermediate ARM64_WORKAROUND_SPECULATIVE_SSBS option. +The set of affected CPUs is described as a list so that this can easily +be extended. + +I've used ARM64_ERRATUM_3194386 (matching the Neoverse-V3 erratum ID) as +the common option, matching the way we use ARM64_ERRATUM_1319367 to +cover Cortex-A57 erratum 1319537 and Cortex-A72 erratum 1319367. + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240603111812.1514101-5-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: fix conflicts & renames, drop unneeded cpucaps.h ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + Documentation/arm64/silicon-errata.rst | 2 +- + arch/arm64/Kconfig | 28 ++++---------------------- + arch/arm64/kernel/cpu_errata.c | 8 ++------ + arch/arm64/kernel/proton-pack.c | 2 +- + 4 files changed, 8 insertions(+), 32 deletions(-) + +diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst +index 33595bc79dea6..13d77af92edf7 100644 +--- a/Documentation/arm64/silicon-errata.rst ++++ b/Documentation/arm64/silicon-errata.rst +@@ -122,7 +122,7 @@ stable kernels. + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_2253138 | + +----------------+-----------------+-----------------+-----------------------------+ +-| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3312417 | ++| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 | + +----------------+-----------------+-----------------+-----------------------------+ + | ARM | MMU-500 | #841119,826419 | N/A | + +----------------+-----------------+-----------------+-----------------------------+ +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index bc89287d38ed1..623b30c21c00d 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -848,34 +848,14 @@ config ARM64_ERRATUM_2224489 + + If unsure, say Y. + +-config ARM64_WORKAROUND_SPECULATIVE_SSBS +- bool +- + config ARM64_ERRATUM_3194386 +- bool "Cortex-X4: 3194386: workaround for MSR SSBS not self-synchronizing" +- select ARM64_WORKAROUND_SPECULATIVE_SSBS ++ bool "Cortex-X4/Neoverse-V3: workaround for MSR SSBS not self-synchronizing" + default y + help +- This option adds the workaround for ARM Cortex-X4 erratum 3194386. +- +- On affected cores "MSR SSBS, #0" instructions may not affect +- subsequent speculative instructions, which may permit unexepected +- speculative store bypassing. +- +- Work around this problem by placing a speculation barrier after +- kernel changes to SSBS. The presence of the SSBS special-purpose +- register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such +- that userspace will use the PR_SPEC_STORE_BYPASS prctl to change +- SSBS. ++ This option adds the workaround for the following errata: + +- If unsure, say Y. +- +-config ARM64_ERRATUM_3312417 +- bool "Neoverse-V3: 3312417: workaround for MSR SSBS not self-synchronizing" +- select ARM64_WORKAROUND_SPECULATIVE_SSBS +- default y +- help +- This option adds the workaround for ARM Neoverse-V3 erratum 3312417. ++ * ARM Cortex-X4 erratum 3194386 ++ * ARM Neoverse-V3 erratum 3312417 + + On affected cores "MSR SSBS, #0" instructions may not affect + subsequent speculative instructions, which may permit unexepected +diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c +index 0cf60010a0825..0fe2d65e646fe 100644 +--- a/arch/arm64/kernel/cpu_errata.c ++++ b/arch/arm64/kernel/cpu_errata.c +@@ -402,14 +402,10 @@ static struct midr_range trbe_write_out_of_range_cpus[] = { + }; + #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ + +-#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS +-static const struct midr_range erratum_spec_ssbs_list[] = { + #ifdef CONFIG_ARM64_ERRATUM_3194386 ++static const struct midr_range erratum_spec_ssbs_list[] = { + MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), +-#endif +-#ifdef CONFIG_ARM64_ERRATUM_3312417 + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), +-#endif + {} + }; + #endif +@@ -661,7 +657,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { + CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus), + }, + #endif +-#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS ++#ifdef CONFIG_ARM64_ERRATUM_3194386 + { + .desc = "ARM errata 3194386, 3312417", + .capability = ARM64_WORKAROUND_SPECULATIVE_SSBS, +diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c +index c0149af8c9e97..ebce46c4e942c 100644 +--- a/arch/arm64/kernel/proton-pack.c ++++ b/arch/arm64/kernel/proton-pack.c +@@ -567,7 +567,7 @@ static enum mitigation_state spectre_v4_enable_hw_mitigation(void) + * Mitigate this with an unconditional speculation barrier, as CPUs + * could mis-speculate branches and bypass a conditional barrier. + */ +- if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS)) ++ if (IS_ENABLED(CONFIG_ARM64_ERRATUM_3194386)) + spec_bar(); + + return SPECTRE_MITIGATED; +-- +2.43.0 + diff --git a/queue-5.15/asoc-codecs-wcd938x-sdw-correct-soundwire-ports-mask.patch b/queue-5.15/asoc-codecs-wcd938x-sdw-correct-soundwire-ports-mask.patch new file mode 100644 index 00000000000..3a569eca476 --- /dev/null +++ b/queue-5.15/asoc-codecs-wcd938x-sdw-correct-soundwire-ports-mask.patch @@ -0,0 +1,51 @@ +From b89197fbe8f56d3e95ef6ee1b46cc0c798c6eadc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 26 Jul 2024 16:10:42 +0200 +Subject: ASoC: codecs: wcd938x-sdw: Correct Soundwire ports mask + +From: Krzysztof Kozlowski + +[ Upstream commit 3f6fb03dae9c7dfba7670858d29e03c8faaa89fe ] + +Device has up to WCD938X_MAX_SWR_PORTS number of ports and the array +assigned to prop.src_dpn_prop and prop.sink_dpn_prop has +0..WCD938X_MAX_SWR_PORTS-1 elements. On the other hand, GENMASK(high, +low) creates an inclusive mask between , so we need the mask +from 0 up to WCD938X_MAX_SWR_PORTS-1. + +Theoretically, too wide mask could cause an out of bounds read in +sdw_get_slave_dpn_prop() in stream.c, however only in the case of buggy +driver, e.g. adding incorrect number of ports via +sdw_stream_add_slave(). + +Fixes: 16572522aece ("ASoC: codecs: wcd938x-sdw: add SoundWire driver") +Signed-off-by: Krzysztof Kozlowski +Link: https://patch.msgid.link/20240726-asoc-wcd-wsa-swr-ports-genmask-v1-2-d4d7a8b56f05@linaro.org +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/wcd938x-sdw.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/sound/soc/codecs/wcd938x-sdw.c b/sound/soc/codecs/wcd938x-sdw.c +index 84a67bd98dc05..cfe694fddd139 100644 +--- a/sound/soc/codecs/wcd938x-sdw.c ++++ b/sound/soc/codecs/wcd938x-sdw.c +@@ -250,12 +250,12 @@ static int wcd9380_probe(struct sdw_slave *pdev, + SDW_SCP_INT1_PARITY; + pdev->prop.lane_control_support = true; + if (wcd->is_tx) { +- pdev->prop.source_ports = GENMASK(WCD938X_MAX_SWR_PORTS, 0); ++ pdev->prop.source_ports = GENMASK(WCD938X_MAX_SWR_PORTS - 1, 0); + pdev->prop.src_dpn_prop = wcd938x_dpn_prop; + wcd->ch_info = &wcd938x_sdw_tx_ch_info[0]; + pdev->prop.wake_capable = true; + } else { +- pdev->prop.sink_ports = GENMASK(WCD938X_MAX_SWR_PORTS, 0); ++ pdev->prop.sink_ports = GENMASK(WCD938X_MAX_SWR_PORTS - 1, 0); + pdev->prop.sink_dpn_prop = wcd938x_dpn_prop; + wcd->ch_info = &wcd938x_sdw_rx_ch_info[0]; + } +-- +2.43.0 + diff --git a/queue-5.15/asoc-codecs-wsa881x-correct-soundwire-ports-mask.patch b/queue-5.15/asoc-codecs-wsa881x-correct-soundwire-ports-mask.patch new file mode 100644 index 00000000000..a2f24e1fabe --- /dev/null +++ b/queue-5.15/asoc-codecs-wsa881x-correct-soundwire-ports-mask.patch @@ -0,0 +1,44 @@ +From fd9ea284f86f74ef3edb9eb4e6864f497e9d91fa Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 26 Jul 2024 16:10:44 +0200 +Subject: ASoC: codecs: wsa881x: Correct Soundwire ports mask + +From: Krzysztof Kozlowski + +[ Upstream commit eb11c3bb64ad0a05aeacdb01039863aa2aa3614b ] + +Device has up to WSA881X_MAX_SWR_PORTS number of ports and the array +assigned to prop.sink_dpn_prop has 0..WSA881X_MAX_SWR_PORTS-1 elements. +On the other hand, GENMASK(high, low) creates an inclusive mask between +, so we need the mask from 0 up to WSA881X_MAX_SWR_PORTS-1. + +Theoretically, too wide mask could cause an out of bounds read in +sdw_get_slave_dpn_prop() in stream.c, however only in the case of buggy +driver, e.g. adding incorrect number of ports via +sdw_stream_add_slave(). + +Fixes: a0aab9e1404a ("ASoC: codecs: add wsa881x amplifier support") +Signed-off-by: Krzysztof Kozlowski +Link: https://patch.msgid.link/20240726-asoc-wcd-wsa-swr-ports-genmask-v1-4-d4d7a8b56f05@linaro.org +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/wsa881x.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/sound/soc/codecs/wsa881x.c b/sound/soc/codecs/wsa881x.c +index 8559047694873..c8d3dc6341037 100644 +--- a/sound/soc/codecs/wsa881x.c ++++ b/sound/soc/codecs/wsa881x.c +@@ -1120,7 +1120,7 @@ static int wsa881x_probe(struct sdw_slave *pdev, + wsa881x->sconfig.frame_rate = 48000; + wsa881x->sconfig.direction = SDW_DATA_DIR_RX; + wsa881x->sconfig.type = SDW_STREAM_PDM; +- pdev->prop.sink_ports = GENMASK(WSA881X_MAX_SWR_PORTS, 0); ++ pdev->prop.sink_ports = GENMASK(WSA881X_MAX_SWR_PORTS - 1, 0); + pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop; + pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; + gpiod_direction_output(wsa881x->sd_n, 1); +-- +2.43.0 + diff --git a/queue-5.15/asoc-meson-axg-fifo-fix-irq-scheduling-issue-with-pr.patch b/queue-5.15/asoc-meson-axg-fifo-fix-irq-scheduling-issue-with-pr.patch new file mode 100644 index 00000000000..3592c8b0e64 --- /dev/null +++ b/queue-5.15/asoc-meson-axg-fifo-fix-irq-scheduling-issue-with-pr.patch @@ -0,0 +1,86 @@ +From 65cc8a10ec933b168fbb0a632d67261a6d38c05e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 7 Aug 2024 18:27:03 +0200 +Subject: ASoC: meson: axg-fifo: fix irq scheduling issue with PREEMPT_RT + +From: Jerome Brunet + +[ Upstream commit 5003d0ce5c7da3a02c0aff771f516f99731e7390 ] + +With PREEMPT_RT enabled a spinlock_t becomes a sleeping lock. + +This is usually not a problem with spinlocks used in IRQ context since +IRQ handlers get threaded. However, if IRQF_ONESHOT is set, the primary +handler won't be force-threaded and runs always in hardirq context. This is +a problem because spinlock_t requires a preemptible context on PREEMPT_RT. + +In this particular instance, regmap mmio uses spinlock_t to protect the +register access and IRQF_ONESHOT is set on the IRQ. In this case, it is +actually better to do everything in threaded handler and it solves the +problem with PREEMPT_RT. + +Reported-by: Arseniy Krasnov +Closes: https://lore.kernel.org/linux-amlogic/20240729131652.3012327-1-avkrasnov@salutedevices.com +Suggested-by: Sebastian Andrzej Siewior +Fixes: b11d26660dff ("ASoC: meson: axg-fifo: use threaded irq to check periods") +Signed-off-by: Jerome Brunet +Reviewed-by: Sebastian Andrzej Siewior +Link: https://patch.msgid.link/20240807162705.4024136-1-jbrunet@baylibre.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/meson/axg-fifo.c | 26 ++++++++++---------------- + 1 file changed, 10 insertions(+), 16 deletions(-) + +diff --git a/sound/soc/meson/axg-fifo.c b/sound/soc/meson/axg-fifo.c +index 94b169a5493b5..5218e40aeb1bb 100644 +--- a/sound/soc/meson/axg-fifo.c ++++ b/sound/soc/meson/axg-fifo.c +@@ -207,25 +207,18 @@ static irqreturn_t axg_fifo_pcm_irq_block(int irq, void *dev_id) + status = FIELD_GET(STATUS1_INT_STS, status); + axg_fifo_ack_irq(fifo, status); + +- /* Use the thread to call period elapsed on nonatomic links */ +- if (status & FIFO_INT_COUNT_REPEAT) +- return IRQ_WAKE_THREAD; ++ if (status & ~FIFO_INT_COUNT_REPEAT) ++ dev_dbg(axg_fifo_dev(ss), "unexpected irq - STS 0x%02x\n", ++ status); + +- dev_dbg(axg_fifo_dev(ss), "unexpected irq - STS 0x%02x\n", +- status); ++ if (status & FIFO_INT_COUNT_REPEAT) { ++ snd_pcm_period_elapsed(ss); ++ return IRQ_HANDLED; ++ } + + return IRQ_NONE; + } + +-static irqreturn_t axg_fifo_pcm_irq_block_thread(int irq, void *dev_id) +-{ +- struct snd_pcm_substream *ss = dev_id; +- +- snd_pcm_period_elapsed(ss); +- +- return IRQ_HANDLED; +-} +- + int axg_fifo_pcm_open(struct snd_soc_component *component, + struct snd_pcm_substream *ss) + { +@@ -251,8 +244,9 @@ int axg_fifo_pcm_open(struct snd_soc_component *component, + if (ret) + return ret; + +- ret = request_threaded_irq(fifo->irq, axg_fifo_pcm_irq_block, +- axg_fifo_pcm_irq_block_thread, ++ /* Use the threaded irq handler only with non-atomic links */ ++ ret = request_threaded_irq(fifo->irq, NULL, ++ axg_fifo_pcm_irq_block, + IRQF_ONESHOT, dev_name(dev), ss); + if (ret) + return ret; +-- +2.43.0 + diff --git a/queue-5.15/bpf-kprobe-remove-unused-declaring-of-bpf_kprobe_ove.patch b/queue-5.15/bpf-kprobe-remove-unused-declaring-of-bpf_kprobe_ove.patch new file mode 100644 index 00000000000..62469c47797 --- /dev/null +++ b/queue-5.15/bpf-kprobe-remove-unused-declaring-of-bpf_kprobe_ove.patch @@ -0,0 +1,39 @@ +From 132cacfd235dc70833daabec7799f9c5ef27a970 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 5 Aug 2024 14:01:21 +0900 +Subject: bpf: kprobe: remove unused declaring of bpf_kprobe_override + +From: Menglong Dong + +[ Upstream commit 0e8b53979ac86eddb3fd76264025a70071a25574 ] + +After the commit 66665ad2f102 ("tracing/kprobe: bpf: Compare instruction +pointer with original one"), "bpf_kprobe_override" is not used anywhere +anymore, and we can remove it now. + +Link: https://lore.kernel.org/all/20240710085939.11520-1-dongml2@chinatelecom.cn/ + +Fixes: 66665ad2f102 ("tracing/kprobe: bpf: Compare instruction pointer with original one") +Signed-off-by: Menglong Dong +Acked-by: Jiri Olsa +Signed-off-by: Masami Hiramatsu (Google) +Signed-off-by: Sasha Levin +--- + include/linux/trace_events.h | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/include/linux/trace_events.h b/include/linux/trace_events.h +index 511c43ce94213..d5618d96ade67 100644 +--- a/include/linux/trace_events.h ++++ b/include/linux/trace_events.h +@@ -828,7 +828,6 @@ do { \ + struct perf_event; + + DECLARE_PER_CPU(struct pt_regs, perf_trace_regs); +-DECLARE_PER_CPU(int, bpf_kprobe_override); + + extern int perf_trace_init(struct perf_event *event); + extern void perf_trace_destroy(struct perf_event *event); +-- +2.43.0 + diff --git a/queue-5.15/ext4-fix-wrong-unit-use-in-ext4_mb_find_by_goal.patch b/queue-5.15/ext4-fix-wrong-unit-use-in-ext4_mb_find_by_goal.patch new file mode 100644 index 00000000000..3e75bd0d0ba --- /dev/null +++ b/queue-5.15/ext4-fix-wrong-unit-use-in-ext4_mb_find_by_goal.patch @@ -0,0 +1,39 @@ +From d7d3ef7445bf32e235ed84ac9a68107e6293b708 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 3 Jun 2023 23:03:11 +0800 +Subject: ext4: fix wrong unit use in ext4_mb_find_by_goal + +From: Kemeng Shi + +[ Upstream commit 99c515e3a860576ba90c11acbc1d6488dfca6463 ] + +We need start in block unit while fe_start is in cluster unit. Use +ext4_grp_offs_to_block helper to convert fe_start to get start in +block unit. + +Signed-off-by: Kemeng Shi +Reviewed-by: Ojaswin Mujoo +Link: https://lore.kernel.org/r/20230603150327.3596033-4-shikemeng@huaweicloud.com +Signed-off-by: Theodore Ts'o +Signed-off-by: Sasha Levin +--- + fs/ext4/mballoc.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c +index 1145664a0bb71..630a5e5a380e2 100644 +--- a/fs/ext4/mballoc.c ++++ b/fs/ext4/mballoc.c +@@ -2270,8 +2270,7 @@ int ext4_mb_find_by_goal(struct ext4_allocation_context *ac, + if (max >= ac->ac_g_ex.fe_len && ac->ac_g_ex.fe_len == sbi->s_stripe) { + ext4_fsblk_t start; + +- start = ext4_group_first_block_no(ac->ac_sb, e4b->bd_group) + +- ex.fe_start; ++ start = ext4_grp_offs_to_block(ac->ac_sb, &ex); + /* use do_div to get remainder (would be 64-bit modulo) */ + if (do_div(start, sbi->s_stripe) == 0) { + ac->ac_found++; +-- +2.43.0 + diff --git a/queue-5.15/i2c-qcom-geni-add-desc-struct-to-prepare-support-for.patch b/queue-5.15/i2c-qcom-geni-add-desc-struct-to-prepare-support-for.patch new file mode 100644 index 00000000000..3e56be85603 --- /dev/null +++ b/queue-5.15/i2c-qcom-geni-add-desc-struct-to-prepare-support-for.patch @@ -0,0 +1,173 @@ +From 563606693cd1d2b34691aaff0e0f54f4afaecce7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 29 Nov 2022 15:47:05 +0100 +Subject: i2c: qcom-geni: add desc struct to prepare support for I2C Master Hub + variant + +From: Neil Armstrong + +[ Upstream commit 14d02fbadb5dc1cdf66078ef8430dd1cd22bfd53 ] + +The I2C Master Hub is a stripped down version of the GENI Serial Engine +QUP Wrapper Controller but only supporting I2C serial engines without +DMA support. + +Those I2C serial engines variants have some requirements: +- a separate "core" clock +- doesn't support DMA, thus no memory interconnect path +- fixed FIFO size not discoverable in the HW_PARAM_0 register + +Add a desc struct specifying all those requirements which will be used in +a next change when adding the I2C Master Hub serial engine compatible. + +Signed-off-by: Neil Armstrong +Reviewed-by: Konrad Dybcio +Signed-off-by: Wolfram Sang +Stable-dep-of: 9ba48db9f77c ("i2c: qcom-geni: Add missing geni_icc_disable in geni_i2c_runtime_resume") +Signed-off-by: Sasha Levin +--- + drivers/i2c/busses/i2c-qcom-geni.c | 50 ++++++++++++++++++++++++++++-- + 1 file changed, 47 insertions(+), 3 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c +index fc1dcc19f2a17..f811999e3aac9 100644 +--- a/drivers/i2c/busses/i2c-qcom-geni.c ++++ b/drivers/i2c/busses/i2c-qcom-geni.c +@@ -88,6 +88,7 @@ struct geni_i2c_dev { + int cur_wr; + int cur_rd; + spinlock_t lock; ++ struct clk *core_clk; + u32 clk_freq_out; + const struct geni_i2c_clk_fld *clk_fld; + int suspended; +@@ -99,6 +100,13 @@ struct geni_i2c_dev { + bool gpi_mode; + }; + ++struct geni_i2c_desc { ++ bool has_core_clk; ++ char *icc_ddr; ++ bool no_dma_support; ++ unsigned int tx_fifo_depth; ++}; ++ + struct geni_i2c_err_log { + int err; + const char *msg; +@@ -755,6 +763,7 @@ static int geni_i2c_probe(struct platform_device *pdev) + u32 proto, tx_depth, fifo_disable; + int ret; + struct device *dev = &pdev->dev; ++ const struct geni_i2c_desc *desc = NULL; + + gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL); + if (!gi2c) +@@ -767,6 +776,14 @@ static int geni_i2c_probe(struct platform_device *pdev) + if (IS_ERR(gi2c->se.base)) + return PTR_ERR(gi2c->se.base); + ++ desc = device_get_match_data(&pdev->dev); ++ ++ if (desc && desc->has_core_clk) { ++ gi2c->core_clk = devm_clk_get(dev, "core"); ++ if (IS_ERR(gi2c->core_clk)) ++ return PTR_ERR(gi2c->core_clk); ++ } ++ + gi2c->se.clk = devm_clk_get(dev, "se"); + if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev)) + return PTR_ERR(gi2c->se.clk); +@@ -810,7 +827,7 @@ static int geni_i2c_probe(struct platform_device *pdev) + gi2c->adap.dev.of_node = dev->of_node; + strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); + +- ret = geni_icc_get(&gi2c->se, "qup-memory"); ++ ret = geni_icc_get(&gi2c->se, desc ? desc->icc_ddr : "qup-memory"); + if (ret) + return ret; + /* +@@ -820,12 +837,17 @@ static int geni_i2c_probe(struct platform_device *pdev) + */ + gi2c->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; + gi2c->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; +- gi2c->se.icc_paths[GENI_TO_DDR].avg_bw = Bps_to_icc(gi2c->clk_freq_out); ++ if (!desc || desc->icc_ddr) ++ gi2c->se.icc_paths[GENI_TO_DDR].avg_bw = Bps_to_icc(gi2c->clk_freq_out); + + ret = geni_icc_set_bw(&gi2c->se); + if (ret) + return ret; + ++ ret = clk_prepare_enable(gi2c->core_clk); ++ if (ret) ++ return ret; ++ + ret = geni_se_resources_on(&gi2c->se); + if (ret) { + dev_err(dev, "Error turning on resources %d\n", ret); +@@ -835,10 +857,15 @@ static int geni_i2c_probe(struct platform_device *pdev) + if (proto != GENI_SE_I2C) { + dev_err(dev, "Invalid proto %d\n", proto); + geni_se_resources_off(&gi2c->se); ++ clk_disable_unprepare(gi2c->core_clk); + return -ENXIO; + } + +- fifo_disable = readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; ++ if (desc && desc->no_dma_support) ++ fifo_disable = false; ++ else ++ fifo_disable = readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; ++ + if (fifo_disable) { + /* FIFO is disabled, so we can only use GPI DMA */ + gi2c->gpi_mode = true; +@@ -852,6 +879,16 @@ static int geni_i2c_probe(struct platform_device *pdev) + } else { + gi2c->gpi_mode = false; + tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se); ++ ++ /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */ ++ if (!tx_depth && desc) ++ tx_depth = desc->tx_fifo_depth; ++ ++ if (!tx_depth) { ++ dev_err(dev, "Invalid TX FIFO depth\n"); ++ return -EINVAL; ++ } ++ + gi2c->tx_wm = tx_depth - 1; + geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth); + geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, +@@ -860,6 +897,7 @@ static int geni_i2c_probe(struct platform_device *pdev) + dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth); + } + ++ clk_disable_unprepare(gi2c->core_clk); + ret = geni_se_resources_off(&gi2c->se); + if (ret) { + dev_err(dev, "Error turning off resources %d\n", ret); +@@ -925,6 +963,8 @@ static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev) + gi2c->suspended = 1; + } + ++ clk_disable_unprepare(gi2c->core_clk); ++ + return geni_icc_disable(&gi2c->se); + } + +@@ -937,6 +977,10 @@ static int __maybe_unused geni_i2c_runtime_resume(struct device *dev) + if (ret) + return ret; + ++ ret = clk_prepare_enable(gi2c->core_clk); ++ if (ret) ++ return ret; ++ + ret = geni_se_resources_on(&gi2c->se); + if (ret) + return ret; +-- +2.43.0 + diff --git a/queue-5.15/i2c-qcom-geni-add-missing-clk_disable_unprepare-in-g.patch b/queue-5.15/i2c-qcom-geni-add-missing-clk_disable_unprepare-in-g.patch new file mode 100644 index 00000000000..a60fdd930b8 --- /dev/null +++ b/queue-5.15/i2c-qcom-geni-add-missing-clk_disable_unprepare-in-g.patch @@ -0,0 +1,42 @@ +From b9fab584c4f59346c3397e566b2172bf35e5d282 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 3 Aug 2024 14:10:41 +0800 +Subject: i2c: qcom-geni: Add missing clk_disable_unprepare in + geni_i2c_runtime_resume + +From: Gaosheng Cui + +[ Upstream commit b93d16bee557302d4e588375ececd833cc048acc ] + +Add the missing clk_disable_unprepare() before return in +geni_i2c_runtime_resume(). + +Fixes: 14d02fbadb5d ("i2c: qcom-geni: add desc struct to prepare support for I2C Master Hub variant") +Signed-off-by: Gaosheng Cui +Reviewed-by: Vladimir Zapolskiy +Signed-off-by: Andi Shyti +Stable-dep-of: 9ba48db9f77c ("i2c: qcom-geni: Add missing geni_icc_disable in geni_i2c_runtime_resume") +Signed-off-by: Sasha Levin +--- + drivers/i2c/busses/i2c-qcom-geni.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c +index f811999e3aac9..27a7cca3918c6 100644 +--- a/drivers/i2c/busses/i2c-qcom-geni.c ++++ b/drivers/i2c/busses/i2c-qcom-geni.c +@@ -982,8 +982,10 @@ static int __maybe_unused geni_i2c_runtime_resume(struct device *dev) + return ret; + + ret = geni_se_resources_on(&gi2c->se); +- if (ret) ++ if (ret) { ++ clk_disable_unprepare(gi2c->core_clk); + return ret; ++ } + + enable_irq(gi2c->irq); + gi2c->suspended = 0; +-- +2.43.0 + diff --git a/queue-5.15/i2c-qcom-geni-add-missing-geni_icc_disable-in-geni_i.patch b/queue-5.15/i2c-qcom-geni-add-missing-geni_icc_disable-in-geni_i.patch new file mode 100644 index 00000000000..b0949465dd9 --- /dev/null +++ b/queue-5.15/i2c-qcom-geni-add-missing-geni_icc_disable-in-geni_i.patch @@ -0,0 +1,37 @@ +From f9edc08d44840561dfcf88791c40eab30d6a9598 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 6 Aug 2024 20:53:31 +0800 +Subject: i2c: qcom-geni: Add missing geni_icc_disable in + geni_i2c_runtime_resume + +From: Gaosheng Cui + +[ Upstream commit 9ba48db9f77ce0001dbb882476fa46e092feb695 ] + +Add the missing geni_icc_disable() before return in +geni_i2c_runtime_resume(). + +Fixes: bf225ed357c6 ("i2c: i2c-qcom-geni: Add interconnect support") +Signed-off-by: Gaosheng Cui +Reviewed-by: Vladimir Zapolskiy +Signed-off-by: Andi Shyti +Signed-off-by: Sasha Levin +--- + drivers/i2c/busses/i2c-qcom-geni.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c +index 27a7cca3918c6..8eb64b09cf58e 100644 +--- a/drivers/i2c/busses/i2c-qcom-geni.c ++++ b/drivers/i2c/busses/i2c-qcom-geni.c +@@ -984,6 +984,7 @@ static int __maybe_unused geni_i2c_runtime_resume(struct device *dev) + ret = geni_se_resources_on(&gi2c->se); + if (ret) { + clk_disable_unprepare(gi2c->core_clk); ++ geni_icc_disable(&gi2c->se); + return ret; + } + +-- +2.43.0 + diff --git a/queue-5.15/i2c-qcom-geni-add-support-for-gpi-dma.patch b/queue-5.15/i2c-qcom-geni-add-support-for-gpi-dma.patch new file mode 100644 index 00000000000..4a8f0c7cecb --- /dev/null +++ b/queue-5.15/i2c-qcom-geni-add-support-for-gpi-dma.patch @@ -0,0 +1,436 @@ +From 7d1839cf943c210a5741981a805f402cc4ec3668 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 21 Feb 2022 15:57:16 +0530 +Subject: i2c: qcom-geni: Add support for GPI DMA + +From: Vinod Koul + +[ Upstream commit d8703554f4dea9775417525b22b3d65ed1c6b16e ] + +QUP Serial engines supports data transfers thru FIFO mode, SE DMA mode +and lastly GPI DMA mode. Former two are already supported and this adds +supports for the last mode. + +In GPI DMA mode, the firmware is issued commands by driver to perform +DMA and setup the serial port. + +Signed-off-by: Vinod Koul +Reviewed-by: Bjorn Andersson +Signed-off-by: Wolfram Sang +Stable-dep-of: 9ba48db9f77c ("i2c: qcom-geni: Add missing geni_icc_disable in geni_i2c_runtime_resume") +Signed-off-by: Sasha Levin +--- + drivers/i2c/busses/i2c-qcom-geni.c | 308 ++++++++++++++++++++++++++--- + 1 file changed, 280 insertions(+), 28 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c +index 6d635a7c104ce..fc1dcc19f2a17 100644 +--- a/drivers/i2c/busses/i2c-qcom-geni.c ++++ b/drivers/i2c/busses/i2c-qcom-geni.c +@@ -3,7 +3,9 @@ + + #include + #include ++#include + #include ++#include + #include + #include + #include +@@ -48,6 +50,9 @@ + #define LOW_COUNTER_SHFT 10 + #define CYCLE_COUNTER_MSK GENMASK(9, 0) + ++#define I2C_PACK_TX BIT(0) ++#define I2C_PACK_RX BIT(1) ++ + enum geni_i2c_err_code { + GP_IRQ0, + NACK, +@@ -89,6 +94,9 @@ struct geni_i2c_dev { + void *dma_buf; + size_t xfer_len; + dma_addr_t dma_addr; ++ struct dma_chan *tx_c; ++ struct dma_chan *rx_c; ++ bool gpi_mode; + }; + + struct geni_i2c_err_log { +@@ -456,12 +464,207 @@ static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, + return gi2c->err; + } + ++static void i2c_gpi_cb_result(void *cb, const struct dmaengine_result *result) ++{ ++ struct geni_i2c_dev *gi2c = cb; ++ ++ if (result->result != DMA_TRANS_NOERROR) { ++ dev_err(gi2c->se.dev, "DMA txn failed:%d\n", result->result); ++ gi2c->err = -EIO; ++ } else if (result->residue) { ++ dev_dbg(gi2c->se.dev, "DMA xfer has pending: %d\n", result->residue); ++ } ++ ++ complete(&gi2c->done); ++} ++ ++static void geni_i2c_gpi_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, ++ void *tx_buf, dma_addr_t tx_addr, ++ void *rx_buf, dma_addr_t rx_addr) ++{ ++ if (tx_buf) { ++ dma_unmap_single(gi2c->se.dev->parent, tx_addr, msg->len, DMA_TO_DEVICE); ++ i2c_put_dma_safe_msg_buf(tx_buf, msg, false); ++ } ++ ++ if (rx_buf) { ++ dma_unmap_single(gi2c->se.dev->parent, rx_addr, msg->len, DMA_FROM_DEVICE); ++ i2c_put_dma_safe_msg_buf(rx_buf, msg, false); ++ } ++} ++ ++static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, ++ struct dma_slave_config *config, dma_addr_t *dma_addr_p, ++ void **buf, unsigned int op, struct dma_chan *dma_chan) ++{ ++ struct gpi_i2c_config *peripheral; ++ unsigned int flags; ++ void *dma_buf; ++ dma_addr_t addr; ++ enum dma_data_direction map_dirn; ++ enum dma_transfer_direction dma_dirn; ++ struct dma_async_tx_descriptor *desc; ++ int ret; ++ ++ peripheral = config->peripheral_config; ++ ++ dma_buf = i2c_get_dma_safe_msg_buf(msg, 1); ++ if (!dma_buf) ++ return -ENOMEM; ++ ++ if (op == I2C_WRITE) ++ map_dirn = DMA_TO_DEVICE; ++ else ++ map_dirn = DMA_FROM_DEVICE; ++ ++ addr = dma_map_single(gi2c->se.dev->parent, dma_buf, msg->len, map_dirn); ++ if (dma_mapping_error(gi2c->se.dev->parent, addr)) { ++ i2c_put_dma_safe_msg_buf(dma_buf, msg, false); ++ return -ENOMEM; ++ } ++ ++ /* set the length as message for rx txn */ ++ peripheral->rx_len = msg->len; ++ peripheral->op = op; ++ ++ ret = dmaengine_slave_config(dma_chan, config); ++ if (ret) { ++ dev_err(gi2c->se.dev, "dma config error: %d for op:%d\n", ret, op); ++ goto err_config; ++ } ++ ++ peripheral->set_config = 0; ++ peripheral->multi_msg = true; ++ flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK; ++ ++ if (op == I2C_WRITE) ++ dma_dirn = DMA_MEM_TO_DEV; ++ else ++ dma_dirn = DMA_DEV_TO_MEM; ++ ++ desc = dmaengine_prep_slave_single(dma_chan, addr, msg->len, dma_dirn, flags); ++ if (!desc) { ++ dev_err(gi2c->se.dev, "prep_slave_sg failed\n"); ++ ret = -EIO; ++ goto err_config; ++ } ++ ++ desc->callback_result = i2c_gpi_cb_result; ++ desc->callback_param = gi2c; ++ ++ dmaengine_submit(desc); ++ *dma_addr_p = addr; ++ ++ return 0; ++ ++err_config: ++ dma_unmap_single(gi2c->se.dev->parent, addr, msg->len, map_dirn); ++ i2c_put_dma_safe_msg_buf(dma_buf, msg, false); ++ return ret; ++} ++ ++static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], int num) ++{ ++ struct dma_slave_config config = {}; ++ struct gpi_i2c_config peripheral = {}; ++ int i, ret = 0, timeout; ++ dma_addr_t tx_addr, rx_addr; ++ void *tx_buf = NULL, *rx_buf = NULL; ++ const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; ++ ++ config.peripheral_config = &peripheral; ++ config.peripheral_size = sizeof(peripheral); ++ ++ peripheral.pack_enable = I2C_PACK_TX | I2C_PACK_RX; ++ peripheral.cycle_count = itr->t_cycle_cnt; ++ peripheral.high_count = itr->t_high_cnt; ++ peripheral.low_count = itr->t_low_cnt; ++ peripheral.clk_div = itr->clk_div; ++ peripheral.set_config = 1; ++ peripheral.multi_msg = false; ++ ++ for (i = 0; i < num; i++) { ++ gi2c->cur = &msgs[i]; ++ gi2c->err = 0; ++ dev_dbg(gi2c->se.dev, "msg[%d].len:%d\n", i, gi2c->cur->len); ++ ++ peripheral.stretch = 0; ++ if (i < num - 1) ++ peripheral.stretch = 1; ++ ++ peripheral.addr = msgs[i].addr; ++ ++ if (msgs[i].flags & I2C_M_RD) { ++ ret = geni_i2c_gpi(gi2c, &msgs[i], &config, ++ &rx_addr, &rx_buf, I2C_READ, gi2c->rx_c); ++ if (ret) ++ goto err; ++ } ++ ++ ret = geni_i2c_gpi(gi2c, &msgs[i], &config, ++ &tx_addr, &tx_buf, I2C_WRITE, gi2c->tx_c); ++ if (ret) ++ goto err; ++ ++ if (msgs[i].flags & I2C_M_RD) ++ dma_async_issue_pending(gi2c->rx_c); ++ dma_async_issue_pending(gi2c->tx_c); ++ ++ timeout = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); ++ if (!timeout) { ++ dev_err(gi2c->se.dev, "I2C timeout gpi flags:%d addr:0x%x\n", ++ gi2c->cur->flags, gi2c->cur->addr); ++ gi2c->err = -ETIMEDOUT; ++ goto err; ++ } ++ ++ if (gi2c->err) { ++ ret = gi2c->err; ++ goto err; ++ } ++ ++ geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); ++ } ++ ++ return num; ++ ++err: ++ dev_err(gi2c->se.dev, "GPI transfer failed: %d\n", ret); ++ dmaengine_terminate_sync(gi2c->rx_c); ++ dmaengine_terminate_sync(gi2c->tx_c); ++ geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); ++ return ret; ++} ++ ++static int geni_i2c_fifo_xfer(struct geni_i2c_dev *gi2c, ++ struct i2c_msg msgs[], int num) ++{ ++ int i, ret = 0; ++ ++ for (i = 0; i < num; i++) { ++ u32 m_param = i < (num - 1) ? STOP_STRETCH : 0; ++ ++ m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK); ++ ++ gi2c->cur = &msgs[i]; ++ if (msgs[i].flags & I2C_M_RD) ++ ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param); ++ else ++ ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param); ++ ++ if (ret) ++ return ret; ++ } ++ ++ return num; ++} ++ + static int geni_i2c_xfer(struct i2c_adapter *adap, + struct i2c_msg msgs[], + int num) + { + struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap); +- int i, ret; ++ int ret; + + gi2c->err = 0; + reinit_completion(&gi2c->done); +@@ -475,28 +678,17 @@ static int geni_i2c_xfer(struct i2c_adapter *adap, + } + + qcom_geni_i2c_conf(gi2c); +- for (i = 0; i < num; i++) { +- u32 m_param = i < (num - 1) ? STOP_STRETCH : 0; +- +- m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK); +- +- gi2c->cur = &msgs[i]; +- if (msgs[i].flags & I2C_M_RD) +- ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param); +- else +- ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param); + +- if (ret) +- break; +- } +- if (ret == 0) +- ret = num; ++ if (gi2c->gpi_mode) ++ ret = geni_i2c_gpi_xfer(gi2c, msgs, num); ++ else ++ ret = geni_i2c_fifo_xfer(gi2c, msgs, num); + + pm_runtime_mark_last_busy(gi2c->se.dev); + pm_runtime_put_autosuspend(gi2c->se.dev); + gi2c->cur = NULL; + gi2c->err = 0; +- return ret; ++ return num; + } + + static u32 geni_i2c_func(struct i2c_adapter *adap) +@@ -517,11 +709,50 @@ static const struct acpi_device_id geni_i2c_acpi_match[] = { + MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match); + #endif + ++static void release_gpi_dma(struct geni_i2c_dev *gi2c) ++{ ++ if (gi2c->rx_c) ++ dma_release_channel(gi2c->rx_c); ++ ++ if (gi2c->tx_c) ++ dma_release_channel(gi2c->tx_c); ++} ++ ++static int setup_gpi_dma(struct geni_i2c_dev *gi2c) ++{ ++ int ret; ++ ++ geni_se_select_mode(&gi2c->se, GENI_GPI_DMA); ++ gi2c->tx_c = dma_request_chan(gi2c->se.dev, "tx"); ++ if (IS_ERR(gi2c->tx_c)) { ++ ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->tx_c), ++ "Failed to get tx DMA ch\n"); ++ if (ret < 0) ++ goto err_tx; ++ } ++ ++ gi2c->rx_c = dma_request_chan(gi2c->se.dev, "rx"); ++ if (IS_ERR(gi2c->rx_c)) { ++ ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->rx_c), ++ "Failed to get rx DMA ch\n"); ++ if (ret < 0) ++ goto err_rx; ++ } ++ ++ dev_dbg(gi2c->se.dev, "Grabbed GPI dma channels\n"); ++ return 0; ++ ++err_rx: ++ dma_release_channel(gi2c->tx_c); ++err_tx: ++ return ret; ++} ++ + static int geni_i2c_probe(struct platform_device *pdev) + { + struct geni_i2c_dev *gi2c; + struct resource *res; +- u32 proto, tx_depth; ++ u32 proto, tx_depth, fifo_disable; + int ret; + struct device *dev = &pdev->dev; + +@@ -601,27 +832,43 @@ static int geni_i2c_probe(struct platform_device *pdev) + return ret; + } + proto = geni_se_read_proto(&gi2c->se); +- tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se); + if (proto != GENI_SE_I2C) { + dev_err(dev, "Invalid proto %d\n", proto); + geni_se_resources_off(&gi2c->se); + return -ENXIO; + } +- gi2c->tx_wm = tx_depth - 1; +- geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth); +- geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, PACKING_BYTES_PW, +- true, true, true); ++ ++ fifo_disable = readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; ++ if (fifo_disable) { ++ /* FIFO is disabled, so we can only use GPI DMA */ ++ gi2c->gpi_mode = true; ++ ret = setup_gpi_dma(gi2c); ++ if (ret) { ++ dev_err(dev, "Failed to setup GPI DMA mode:%d ret\n", ret); ++ return ret; ++ } ++ ++ dev_dbg(dev, "Using GPI DMA mode for I2C\n"); ++ } else { ++ gi2c->gpi_mode = false; ++ tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se); ++ gi2c->tx_wm = tx_depth - 1; ++ geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth); ++ geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, ++ PACKING_BYTES_PW, true, true, true); ++ ++ dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth); ++ } ++ + ret = geni_se_resources_off(&gi2c->se); + if (ret) { + dev_err(dev, "Error turning off resources %d\n", ret); +- return ret; ++ goto err_dma; + } + + ret = geni_icc_disable(&gi2c->se); + if (ret) +- return ret; +- +- dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth); ++ goto err_dma; + + gi2c->suspended = 1; + pm_runtime_set_suspended(gi2c->se.dev); +@@ -633,12 +880,16 @@ static int geni_i2c_probe(struct platform_device *pdev) + if (ret) { + dev_err(dev, "Error adding i2c adapter %d\n", ret); + pm_runtime_disable(gi2c->se.dev); +- return ret; ++ goto err_dma; + } + + dev_dbg(dev, "Geni-I2C adaptor successfully added\n"); + + return 0; ++ ++err_dma: ++ release_gpi_dma(gi2c); ++ return ret; + } + + static int geni_i2c_remove(struct platform_device *pdev) +@@ -646,6 +897,7 @@ static int geni_i2c_remove(struct platform_device *pdev) + struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev); + + i2c_del_adapter(&gi2c->adap); ++ release_gpi_dma(gi2c); + pm_runtime_disable(gi2c->se.dev); + return 0; + } +-- +2.43.0 + diff --git a/queue-5.15/i2c-smbus-improve-handling-of-stuck-alerts.patch b/queue-5.15/i2c-smbus-improve-handling-of-stuck-alerts.patch new file mode 100644 index 00000000000..796fe07438e --- /dev/null +++ b/queue-5.15/i2c-smbus-improve-handling-of-stuck-alerts.patch @@ -0,0 +1,122 @@ +From cea76e82c7f10e3e7dbf50b62b514ed579ecba53 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 10 Jan 2022 09:28:56 -0800 +Subject: i2c: smbus: Improve handling of stuck alerts + +From: Guenter Roeck + +[ Upstream commit 37c526f00bc1c4f847fc800085f8f009d2e11be6 ] + +The following messages were observed while testing alert functionality +on systems with multiple I2C devices on a single bus if alert was active +on more than one chip. + +smbus_alert 3-000c: SMBALERT# from dev 0x0c, flag 0 +smbus_alert 3-000c: no driver alert()! + +and: + +smbus_alert 3-000c: SMBALERT# from dev 0x28, flag 0 + +Once it starts, this message repeats forever at high rate. There is no +device at any of the reported addresses. + +Analysis shows that this is seen if multiple devices have the alert pin +active. Apparently some devices do not support SMBus arbitration correctly. +They keep sending address bits after detecting an address collision and +handle the collision not at all or too late. +Specifically, address 0x0c is seen with ADT7461A at address 0x4c and +ADM1021 at address 0x18 if alert is active on both chips. Address 0x28 is +seen with ADT7483 at address 0x2a and ADT7461 at address 0x4c if alert is +active on both chips. + +Once the system is in bad state (alert is set by more than one chip), +it often only recovers by power cycling. + +To reduce the impact of this problem, abort the endless loop in +smbus_alert() if the same address is read more than once and not +handled by a driver. + +Fixes: b5527a7766f0 ("i2c: Add SMBus alert support") +Signed-off-by: Guenter Roeck +[wsa: it also fixed an interrupt storm in one of my experiments] +Tested-by: Wolfram Sang +[wsa: rebased, moved a comment as well, improved the 'invalid' value] +Signed-off-by: Wolfram Sang +Signed-off-by: Sasha Levin +--- + drivers/i2c/i2c-smbus.c | 32 +++++++++++++++++++++++++------- + 1 file changed, 25 insertions(+), 7 deletions(-) + +diff --git a/drivers/i2c/i2c-smbus.c b/drivers/i2c/i2c-smbus.c +index d3d06e3b4f3b3..dcbc4b29aa729 100644 +--- a/drivers/i2c/i2c-smbus.c ++++ b/drivers/i2c/i2c-smbus.c +@@ -34,6 +34,7 @@ static int smbus_do_alert(struct device *dev, void *addrp) + struct i2c_client *client = i2c_verify_client(dev); + struct alert_data *data = addrp; + struct i2c_driver *driver; ++ int ret; + + if (!client || client->addr != data->addr) + return 0; +@@ -47,16 +48,21 @@ static int smbus_do_alert(struct device *dev, void *addrp) + device_lock(dev); + if (client->dev.driver) { + driver = to_i2c_driver(client->dev.driver); +- if (driver->alert) ++ if (driver->alert) { ++ /* Stop iterating after we find the device */ + driver->alert(client, data->type, data->data); +- else ++ ret = -EBUSY; ++ } else { + dev_warn(&client->dev, "no driver alert()!\n"); +- } else ++ ret = -EOPNOTSUPP; ++ } ++ } else { + dev_dbg(&client->dev, "alert with no driver\n"); ++ ret = -ENODEV; ++ } + device_unlock(dev); + +- /* Stop iterating after we find the device */ +- return -EBUSY; ++ return ret; + } + + /* +@@ -67,6 +73,7 @@ static irqreturn_t smbus_alert(int irq, void *d) + { + struct i2c_smbus_alert *alert = d; + struct i2c_client *ara; ++ unsigned short prev_addr = I2C_CLIENT_END; /* Not a valid address */ + + ara = alert->ara; + +@@ -94,8 +101,19 @@ static irqreturn_t smbus_alert(int irq, void *d) + data.addr, data.data); + + /* Notify driver for the device which issued the alert */ +- device_for_each_child(&ara->adapter->dev, &data, +- smbus_do_alert); ++ status = device_for_each_child(&ara->adapter->dev, &data, ++ smbus_do_alert); ++ /* ++ * If we read the same address more than once, and the alert ++ * was not handled by a driver, it won't do any good to repeat ++ * the loop because it will never terminate. ++ * Bail out in this case. ++ * Note: This assumes that a driver with alert handler handles ++ * the alert properly and clears it if necessary. ++ */ ++ if (data.addr == prev_addr && status != -EBUSY) ++ break; ++ prev_addr = data.addr; + } + + return IRQ_HANDLED; +-- +2.43.0 + diff --git a/queue-5.15/i2c-smbus-send-alert-notifications-to-all-devices-if.patch b/queue-5.15/i2c-smbus-send-alert-notifications-to-all-devices-if.patch new file mode 100644 index 00000000000..3ac3ae39852 --- /dev/null +++ b/queue-5.15/i2c-smbus-send-alert-notifications-to-all-devices-if.patch @@ -0,0 +1,106 @@ +From fc54bf92179b7a65a312e0bebb7fb7e5ce3bf3f3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Jul 2024 07:19:41 -0700 +Subject: i2c: smbus: Send alert notifications to all devices if source not + found + +From: Guenter Roeck + +[ Upstream commit f6c29f710c1ff2590109f83be3e212b86c01e0f3 ] + +If a SMBus alert is received and the originating device is not found, +the reason may be that the address reported on the SMBus alert address +is corrupted, for example because multiple devices asserted alert and +do not correctly implement SMBus arbitration. + +If this happens, call alert handlers on all devices connected to the +given I2C bus, in the hope that this cleans up the situation. + +This change reliably fixed the problem on a system with multiple devices +on a single bus. Example log where the device on address 0x18 (ADM1021) +and on address 0x4c (ADT7461A) both had the alert line asserted: + +smbus_alert 3-000c: SMBALERT# from dev 0x0c, flag 0 +smbus_alert 3-000c: no driver alert()! +smbus_alert 3-000c: SMBALERT# from dev 0x0c, flag 0 +smbus_alert 3-000c: no driver alert()! +lm90 3-0018: temp1 out of range, please check! +lm90 3-0018: Disabling ALERT# +lm90 3-0029: Everything OK +lm90 3-002a: Everything OK +lm90 3-004c: temp1 out of range, please check! +lm90 3-004c: temp2 out of range, please check! +lm90 3-004c: Disabling ALERT# + +Fixes: b5527a7766f0 ("i2c: Add SMBus alert support") +Signed-off-by: Guenter Roeck +[wsa: fixed a typo in the commit message] +Signed-off-by: Wolfram Sang +Signed-off-by: Sasha Levin +--- + drivers/i2c/i2c-smbus.c | 38 +++++++++++++++++++++++++++++++++++--- + 1 file changed, 35 insertions(+), 3 deletions(-) + +diff --git a/drivers/i2c/i2c-smbus.c b/drivers/i2c/i2c-smbus.c +index dcbc4b29aa729..44582cf29e162 100644 +--- a/drivers/i2c/i2c-smbus.c ++++ b/drivers/i2c/i2c-smbus.c +@@ -65,6 +65,32 @@ static int smbus_do_alert(struct device *dev, void *addrp) + return ret; + } + ++/* Same as above, but call back all drivers with alert handler */ ++ ++static int smbus_do_alert_force(struct device *dev, void *addrp) ++{ ++ struct i2c_client *client = i2c_verify_client(dev); ++ struct alert_data *data = addrp; ++ struct i2c_driver *driver; ++ ++ if (!client || (client->flags & I2C_CLIENT_TEN)) ++ return 0; ++ ++ /* ++ * Drivers should either disable alerts, or provide at least ++ * a minimal handler. Lock so the driver won't change. ++ */ ++ device_lock(dev); ++ if (client->dev.driver) { ++ driver = to_i2c_driver(client->dev.driver); ++ if (driver->alert) ++ driver->alert(client, data->type, data->data); ++ } ++ device_unlock(dev); ++ ++ return 0; ++} ++ + /* + * The alert IRQ handler needs to hand work off to a task which can issue + * SMBus calls, because those sleeping calls can't be made in IRQ context. +@@ -106,13 +132,19 @@ static irqreturn_t smbus_alert(int irq, void *d) + /* + * If we read the same address more than once, and the alert + * was not handled by a driver, it won't do any good to repeat +- * the loop because it will never terminate. +- * Bail out in this case. ++ * the loop because it will never terminate. Try again, this ++ * time calling the alert handlers of all devices connected to ++ * the bus, and abort the loop afterwards. If this helps, we ++ * are all set. If it doesn't, there is nothing else we can do, ++ * so we might as well abort the loop. + * Note: This assumes that a driver with alert handler handles + * the alert properly and clears it if necessary. + */ +- if (data.addr == prev_addr && status != -EBUSY) ++ if (data.addr == prev_addr && status != -EBUSY) { ++ device_for_each_child(&ara->adapter->dev, &data, ++ smbus_do_alert_force); + break; ++ } + prev_addr = data.addr; + } + +-- +2.43.0 + diff --git a/queue-5.15/kprobes-fix-to-check-symbol-prefixes-correctly.patch b/queue-5.15/kprobes-fix-to-check-symbol-prefixes-correctly.patch new file mode 100644 index 00000000000..04c4c88d9cc --- /dev/null +++ b/queue-5.15/kprobes-fix-to-check-symbol-prefixes-correctly.patch @@ -0,0 +1,40 @@ +From 24cc7d92e0dd8522761dd8a75a64f55ce3a5c20c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 2 Aug 2024 22:53:15 +0900 +Subject: kprobes: Fix to check symbol prefixes correctly + +From: Masami Hiramatsu (Google) + +[ Upstream commit 8c8acb8f26cbde665b233dd1b9bbcbb9b86822dc ] + +Since str_has_prefix() takes the prefix as the 2nd argument and the string +as the first, is_cfi_preamble_symbol() always fails to check the prefix. +Fix the function parameter order so that it correctly check the prefix. + +Link: https://lore.kernel.org/all/172260679559.362040.7360872132937227206.stgit@devnote2/ + +Fixes: de02f2ac5d8c ("kprobes: Prohibit probing on CFI preamble symbol") +Signed-off-by: Masami Hiramatsu (Google) +Signed-off-by: Sasha Levin +--- + kernel/kprobes.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/kernel/kprobes.c b/kernel/kprobes.c +index 258d425b2c4a5..0d463859ad329 100644 +--- a/kernel/kprobes.c ++++ b/kernel/kprobes.c +@@ -1545,8 +1545,8 @@ static bool is_cfi_preamble_symbol(unsigned long addr) + if (lookup_symbol_name(addr, symbuf)) + return false; + +- return str_has_prefix("__cfi_", symbuf) || +- str_has_prefix("__pfx_", symbuf); ++ return str_has_prefix(symbuf, "__cfi_") || ++ str_has_prefix(symbuf, "__pfx_"); + } + + static int check_kprobe_address_safe(struct kprobe *p, +-- +2.43.0 + diff --git a/queue-5.15/series b/queue-5.15/series index 2c19598b854..7435f316e44 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -408,3 +408,32 @@ sunrpc-fix-a-race-to-wake-a-sync-task.patch profiling-remove-profile-sleep-support.patch scsi-mpt3sas-avoid-iommu-page-faults-on-report-zones.patch sched-cputime-fix-mul_u64_u64_div_u64-precision-for-cputime.patch +ext4-fix-wrong-unit-use-in-ext4_mb_find_by_goal.patch +arm64-cpufeature-force-hwcap-to-be-based-on-the-sysr.patch +arm64-add-neoverse-v2-part.patch +arm64-barrier-restore-spec_bar-macro.patch +arm64-cputype-add-cortex-x4-definitions.patch +arm64-cputype-add-neoverse-v3-definitions.patch +arm64-errata-add-workaround-for-arm-errata-3194386-a.patch +arm64-cputype-add-cortex-x3-definitions.patch +arm64-cputype-add-cortex-a720-definitions.patch +arm64-cputype-add-cortex-x925-definitions.patch +arm64-errata-unify-speculative-ssbs-errata-logic.patch +arm64-errata-expand-speculative-ssbs-workaround.patch +arm64-cputype-add-cortex-x1c-definitions.patch +arm64-cputype-add-cortex-a725-definitions.patch +arm64-errata-expand-speculative-ssbs-workaround-agai.patch +i2c-smbus-improve-handling-of-stuck-alerts.patch +asoc-codecs-wcd938x-sdw-correct-soundwire-ports-mask.patch +asoc-codecs-wsa881x-correct-soundwire-ports-mask.patch +spi-spidev-add-missing-spi_device_id-for-bh2228fv.patch +i2c-smbus-send-alert-notifications-to-all-devices-if.patch +bpf-kprobe-remove-unused-declaring-of-bpf_kprobe_ove.patch +kprobes-fix-to-check-symbol-prefixes-correctly.patch +i2c-qcom-geni-add-support-for-gpi-dma.patch +i2c-qcom-geni-add-desc-struct-to-prepare-support-for.patch +i2c-qcom-geni-add-missing-clk_disable_unprepare-in-g.patch +i2c-qcom-geni-add-missing-geni_icc_disable-in-geni_i.patch +spi-spi-fsl-lpspi-fix-scldiv-calculation.patch +alsa-usb-audio-re-add-scratchamp-quirk-entries.patch +asoc-meson-axg-fifo-fix-irq-scheduling-issue-with-pr.patch diff --git a/queue-5.15/spi-spi-fsl-lpspi-fix-scldiv-calculation.patch b/queue-5.15/spi-spi-fsl-lpspi-fix-scldiv-calculation.patch new file mode 100644 index 00000000000..19ce60309e5 --- /dev/null +++ b/queue-5.15/spi-spi-fsl-lpspi-fix-scldiv-calculation.patch @@ -0,0 +1,57 @@ +From 9ae5a0d12e39abb5fcb2900e39e07ee0c66e3e38 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 4 Aug 2024 13:36:11 +0200 +Subject: spi: spi-fsl-lpspi: Fix scldiv calculation + +From: Stefan Wahren + +[ Upstream commit 730bbfaf7d4890bd99e637db7767dc68cfeb24e7 ] + +The effective SPI clock frequency should never exceed speed_hz +otherwise this might result in undefined behavior of the SPI device. + +Currently the scldiv calculation could violate this constraint. +For the example parameters perclk_rate = 24 MHz and speed_hz = 7 MHz, +the function fsl_lpspi_set_bitrate will determine perscale = 0 and +scldiv = 1, which is a effective SPI clock of 8 MHz. + +So fix this by rounding up the quotient of perclk_rate and speed_hz. +While this never change within the loop, we can pull this out. + +Fixes: 5314987de5e5 ("spi: imx: add lpspi bus driver") +Signed-off-by: Stefan Wahren +Link: https://patch.msgid.link/20240804113611.83613-1-wahrenst@gmx.net +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + drivers/spi/spi-fsl-lpspi.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c +index c5ff6e8c45be0..c21d7959dcd23 100644 +--- a/drivers/spi/spi-fsl-lpspi.c ++++ b/drivers/spi/spi-fsl-lpspi.c +@@ -297,7 +297,7 @@ static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi) + static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi) + { + struct lpspi_config config = fsl_lpspi->config; +- unsigned int perclk_rate, scldiv; ++ unsigned int perclk_rate, scldiv, div; + u8 prescale; + + perclk_rate = clk_get_rate(fsl_lpspi->clk_per); +@@ -308,8 +308,10 @@ static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi) + return -EINVAL; + } + ++ div = DIV_ROUND_UP(perclk_rate, config.speed_hz); ++ + for (prescale = 0; prescale < 8; prescale++) { +- scldiv = perclk_rate / config.speed_hz / (1 << prescale) - 2; ++ scldiv = div / (1 << prescale) - 2; + if (scldiv < 256) { + fsl_lpspi->config.prescale = prescale; + break; +-- +2.43.0 + diff --git a/queue-5.15/spi-spidev-add-missing-spi_device_id-for-bh2228fv.patch b/queue-5.15/spi-spidev-add-missing-spi_device_id-for-bh2228fv.patch new file mode 100644 index 00000000000..549b1e54735 --- /dev/null +++ b/queue-5.15/spi-spidev-add-missing-spi_device_id-for-bh2228fv.patch @@ -0,0 +1,42 @@ +From 5e88adab9bf2229475bf4e7b4488ef057d301296 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Jul 2024 15:35:47 +0200 +Subject: spi: spidev: Add missing spi_device_id for bh2228fv + +From: Geert Uytterhoeven + +[ Upstream commit e4c4638b6a10427d30e29d22351c375886025f47 ] + +When the of_device_id entry for "rohm,bh2228fv" was added, the +corresponding spi_device_id was forgotten, causing a warning message +during boot-up: + + SPI driver spidev has no spi_device_id for rohm,bh2228fv + +Fix module autoloading and shut up the warning by adding the missing +entry. + +Fixes: fc28d1c1fe3b3e2f ("spi: spidev: add correct compatible for Rohm BH2228FV") +Signed-off-by: Geert Uytterhoeven +Link: https://patch.msgid.link/cb571d4128f41175f31319cd9febc829417ea167.1722346539.git.geert+renesas@glider.be +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + drivers/spi/spidev.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c +index 99bdbc040d1ae..0b97e5b97a018 100644 +--- a/drivers/spi/spidev.c ++++ b/drivers/spi/spidev.c +@@ -682,6 +682,7 @@ static const struct file_operations spidev_fops = { + static struct class *spidev_class; + + static const struct spi_device_id spidev_spi_ids[] = { ++ { .name = "bh2228fv" }, + { .name = "dh2228fv" }, + { .name = "ltc2488" }, + { .name = "sx1301" }, +-- +2.43.0 +