From: Geert Uytterhoeven Date: Wed, 13 Aug 2025 13:37:04 +0000 (+0200) Subject: arm64: dts: renesas: rzg2: Increase CANFD clock rates X-Git-Tag: v6.18-rc1~147^2~50^2~11 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=57875e1526987524efe5001ad6d198a4b145f54f;p=thirdparty%2Fkernel%2Flinux.git arm64: dts: renesas: rzg2: Increase CANFD clock rates Currently, all RZ/G2 .dtsi files configure the CANFD core clocks to 40 MHz, which limits CAN-FD data transfer rates to 4 Mbps. However, all RZ/G2 SoCs support CANFD clock rates up to 80 MHz. Now the R-Car CAN-FD driver has gained support for Transceiver Delay Compensation, increase all appropriate CANFD clock rates to the documented maximum, to support data rates up to 8 Mbps. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/0dd1c17135707587e9e9d6d68b2eaa1921fbcb7a.1755090456.git.geert+renesas@glider.be --- diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index c8b87aed92a36..6b737d91b320f 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -1186,7 +1186,7 @@ <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index f2fc2a2035a1d..3f15d656215e1 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -1070,7 +1070,7 @@ <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 530ffd29cf13d..55df063cb3232 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1029,7 +1029,7 @@ <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index e4dbda8c34d9e..5d730b488d46f 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1298,7 +1298,7 @@ <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled";