From: Zhenqiang Chen <zhenqiang.chen@linaro.org>
Date: Fri, 19 Oct 2012 09:24:39 +0000 (+0000)
Subject: re PR target/54892 (, ICE in extract_insn, at recog.c:2123)
X-Git-Tag: misc/gccgo-go1_1_2~90
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=57fc62cb326ab913d7eef6d0ac0cd7788edd1797;p=thirdparty%2Fgcc.git

re PR target/54892 (, ICE in extract_insn, at recog.c:2123)

	gcc/ChangeLog
	PR target/54892
	* config/arm/arm.c (arm_expand_compare_and_swap): Use SImode to make
	sure the mode is correct when falling through from above cases.

	gcc/testsuite/ChangeLog
	PR target/54892
	* gcc.target/arm/pr54892.c: New.

From-SVN: r192609
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9b09aaa638af..cdba3366b009 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2012-10-19  Zhenqiang Chen <zhenqiang.chen@linaro.org>
+
+	PR target/54892
+	* config/arm/arm.c (arm_expand_compare_and_swap): Use SImode to make
+	sure the mode is correct when falling through from above cases.
+
 2012-10-19  Bin Cheng  <bin.cheng@arm.com>
 
 	* common.opt (flag_ira_hoist_pressure): New.
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 327ef223e4e6..11f793d5d777 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -25447,8 +25447,8 @@ arm_expand_compare_and_swap (rtx operands[])
     case SImode:
       /* Force the value into a register if needed.  We waited until after
 	 the zero-extension above to do this properly.  */
-      if (!arm_add_operand (oldval, mode))
-	oldval = force_reg (mode, oldval);
+      if (!arm_add_operand (oldval, SImode))
+	oldval = force_reg (SImode, oldval);
       break;
 
     case DImode:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 57d4383f1746..4af8265d80d3 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2012-10-19  Zhenqiang Chen <zhenqiang.chen@linaro.org>
+
+	PR target/54892
+	* gcc.target/arm/pr54892.c: New.
+
 2012-10-19  Bin Cheng  <bin.cheng@arm.com>
 
 	* testsuite/gcc.dg/hoist-register-pressure.c: New test.
diff --git a/gcc/testsuite/gcc.target/arm/pr54892.c b/gcc/testsuite/gcc.target/arm/pr54892.c
new file mode 100644
index 000000000000..a7fe1bc66761
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr54892.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+
+int set_role(unsigned char role_id, short m_role)
+{
+  return __sync_bool_compare_and_swap(&m_role, -1, role_id);
+}
+