From: Felix Fietkau <nbd@nbd.name>
Date: Tue, 5 Apr 2022 19:57:44 +0000 (+0200)
Subject: arm64: dts: mediatek: mt7622: add support for coherent DMA
X-Git-Tag: v5.10.216~63
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=57ff09043fa1e5ed53c7bb33da595a84a1b7d4c5;p=thirdparty%2Fkernel%2Fstable.git

arm64: dts: mediatek: mt7622: add support for coherent DMA

[ Upstream commit 3abd063019b6a01762f9fccc39505f29d029360a ]

It improves performance by eliminating the need for a cache flush on rx and tx

Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: David S. Miller <davem@davemloft.net>
Stable-dep-of: 3ba5a6159434 ("arm64: dts: mediatek: mt7622: fix clock controllers")
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index 884930a5849a2..07b4d3ba55612 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -357,7 +357,7 @@
 		};
 
 		cci_control2: slave-if@5000 {
-			compatible = "arm,cci-400-ctrl-if";
+			compatible = "arm,cci-400-ctrl-if", "syscon";
 			interface-type = "ace";
 			reg = <0x5000 0x1000>;
 		};
@@ -937,6 +937,8 @@
 		power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
 		mediatek,ethsys = <&ethsys>;
 		mediatek,sgmiisys = <&sgmiisys>;
+		mediatek,cci-control = <&cci_control2>;
+		dma-coherent;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";