From: Rosen Penev Date: Thu, 28 May 2026 04:10:31 +0000 (-0700) Subject: gpio: realtek-otto: fix kernel-doc warnings X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=5974454ab26a5351abe4897f7110a68120d170fa;p=thirdparty%2Fkernel%2Flinux.git gpio: realtek-otto: fix kernel-doc warnings Add the missing 'struct' keyword in the kernel-doc comment for realtek_gpio_ctrl, and document the @cpumask_base and @cpu_irq_maskable members that were added later but never described. Also fix the mismatch between documented @imr_line_pos and the actual member name line_imr_pos. Fixes W=1 warning: Warning: drivers/gpio/gpio-realtek-otto.c:66 cannot understand function prototype: 'struct realtek_gpio_ctrl' Assisted-by: Opencode:BigPickle Signed-off-by: Rosen Penev Link: https://patch.msgid.link/20260528041031.728557-1-rosenp@gmail.com Signed-off-by: Bartosz Golaszewski --- diff --git a/drivers/gpio/gpio-realtek-otto.c b/drivers/gpio/gpio-realtek-otto.c index 5e3152c2e51a8..37ef56f453187 100644 --- a/drivers/gpio/gpio-realtek-otto.c +++ b/drivers/gpio/gpio-realtek-otto.c @@ -40,16 +40,18 @@ #define REALTEK_GPIO_PORTS_PER_BANK 4 /** - * realtek_gpio_ctrl - Realtek Otto GPIO driver data + * struct realtek_gpio_ctrl - Realtek Otto GPIO driver data * * @chip: Associated gpio_generic_chip instance * @base: Base address of the register block for a GPIO bank + * @cpumask_base: Base address of the per-CPU interrupt mask registers + * @cpu_irq_maskable: CPUs that can receive GPIO interrupts * @lock: Lock for accessing the IRQ registers and values * @intr_mask: Mask for interrupts lines * @intr_type: Interrupt type selection * @bank_read: Read a bank setting as a single 32-bit value * @bank_write: Write a bank setting as a single 32-bit value - * @imr_line_pos: Bit shift of an IRQ line's IMR value. + * @line_imr_pos: Bit shift of an IRQ line's IMR value. * * The DIR, DATA, and ISR registers consist of four 8-bit port values, packed * into a single 32-bit register. Use @bank_read (@bank_write) to get (assign)