From: Sascha Bischoff Date: Thu, 19 Mar 2026 15:56:28 +0000 (+0000) Subject: KVM: arm64: gic-v5: Implement direct injection of PPIs X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=5a98d0e17e59210b400734f2359c4453aab3af21;p=thirdparty%2Fkernel%2Flinux.git KVM: arm64: gic-v5: Implement direct injection of PPIs GICv5 is able to directly inject PPI pending state into a guest using a mechanism called DVI whereby the pending bit for a paticular PPI is driven directly by the physically-connected hardware. This mechanism itself doesn't allow for any ID translation, so the host interrupt is directly mapped into a guest with the same interrupt ID. When mapping a virtual interrupt to a physical interrupt via kvm_vgic_map_irq for a GICv5 guest, check if the interrupt itself is a PPI or not. If it is, and the host's interrupt ID matches that used for the guest DVI is enabled, and the interrupt itself is marked as directly_injected. When the interrupt is unmapped again, this process is reversed, and DVI is disabled for the interrupt again. Note: the expectation is that a directly injected PPI is disabled on the host while the guest state is loaded. The reason is that although DVI is enabled to drive the guest's pending state directly, the host pending state also remains driven. In order to avoid the same PPI firing on both the host and the guest, the host's interrupt must be disabled (masked). This is left up to the code that owns the device generating the PPI as this needs to be handled on a per-VM basis. One VM might use DVI, while another might not, in which case the physical PPI should be enabled for the latter. Co-authored-by: Timothy Hayes Signed-off-by: Timothy Hayes Signed-off-by: Sascha Bischoff Reviewed-by: Jonathan Cameron Link: https://patch.msgid.link/20260319154937.3619520-27-sascha.bischoff@arm.com Signed-off-by: Marc Zyngier --- diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c index f0600be619b14..b84324f0a3114 100644 --- a/arch/arm64/kvm/vgic/vgic-v5.c +++ b/arch/arm64/kvm/vgic/vgic-v5.c @@ -188,8 +188,24 @@ out_unlock_fail: return false; } +/* + * Sets/clears the corresponding bit in the ICH_PPI_DVIR register. + */ +static void vgic_v5_set_ppi_dvi(struct kvm_vcpu *vcpu, struct vgic_irq *irq, + bool dvi) +{ + struct vgic_v5_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v5; + u32 ppi; + + lockdep_assert_held(&irq->irq_lock); + + ppi = vgic_v5_get_hwirq_id(irq->intid); + __assign_bit(ppi, cpu_if->vgic_ppi_dvir, dvi); +} + static struct irq_ops vgic_v5_ppi_irq_ops = { .queue_irq_unlock = vgic_v5_ppi_queue_irq_unlock, + .set_direct_injection = vgic_v5_set_ppi_dvi, }; void vgic_v5_set_ppi_ops(struct kvm_vcpu *vcpu, u32 vintid)