From: Heiner Kallweit Date: Fri, 22 Mar 2019 19:00:20 +0000 (+0100) Subject: net: phy: don't clear BMCR in genphy_soft_reset X-Git-Tag: v4.19.99~361 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=5aeaa36b6823dcc743d858de237e3bc5b7d3e1e2;p=thirdparty%2Fkernel%2Fstable.git net: phy: don't clear BMCR in genphy_soft_reset [ Upstream commit d29f5aa0bc0c321e1b9e4658a2a7e08e885da52a ] So far we effectively clear the BMCR register. Some PHY's can deal with this (e.g. because they reset BMCR to a default as part of a soft-reset) whilst on others this causes issues because e.g. the autoneg bit is cleared. Marvell is an example, see also thread [0]. So let's be a little bit more gentle and leave all bits we're not interested in as-is. This change is needed for PHY drivers to properly deal with the original patch. [0] https://marc.info/?t=155264050700001&r=1&w=2 Fixes: 6e2d85ec0559 ("net: phy: Stop with excessive soft reset") Tested-by: Phil Reid Tested-by: liweihang Signed-off-by: Heiner Kallweit Reviewed-by: Florian Fainelli Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 9c7e51443f6b6..ae40d8137fd20 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -1657,7 +1657,7 @@ int genphy_soft_reset(struct phy_device *phydev) { int ret; - ret = phy_write(phydev, MII_BMCR, BMCR_RESET); + ret = phy_set_bits(phydev, MII_BMCR, BMCR_RESET); if (ret < 0) return ret;