From: Manikanta Maddireddy Date: Tue, 24 Mar 2026 08:08:55 +0000 (+0530) Subject: PCI: tegra194: Make BAR0 programmable and remove 1MB size limit X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=5aec1f18b326ddc455ae9d9d0f5394efc20eee9b;p=thirdparty%2Fkernel%2Fstable.git PCI: tegra194: Make BAR0 programmable and remove 1MB size limit The Tegra194/234 Endpoint does not support the Resizable BAR capability, but BAR0 can be programmed to different sizes via the DBI2 BAR registers in dw_pcie_ep_set_bar_programmable(). The BAR0 size is set once during initialization. Remove the fixed 1MB limit from pci_epc_features so Endpoint function drivers can configure the BAR0 size they need. Signed-off-by: Manikanta Maddireddy Signed-off-by: Manivannan Sadhasivam Reviewed-by: Niklas Cassel Link: https://patch.msgid.link/20260324080857.916263-3-mmaddireddy@nvidia.com --- diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 6881f0b94c73..c5381ffdf1eb 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1978,12 +1978,12 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, return 0; } +/* Tegra EP: BAR0 = 64-bit programmable BAR */ static const struct pci_epc_features tegra_pcie_epc_features = { DWC_EPC_COMMON_FEATURES, .linkup_notifier = true, .msi_capable = true, - .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, - .only_64bit = true, }, + .bar[BAR_0] = { .only_64bit = true, }, .bar[BAR_2] = { .type = BAR_DISABLED, }, .bar[BAR_3] = { .type = BAR_DISABLED, }, .bar[BAR_4] = { .type = BAR_DISABLED, },