From: Greg Kroah-Hartman Date: Thu, 6 Feb 2020 16:49:38 +0000 (+0100) Subject: 4.19-stable patches X-Git-Tag: v4.19.103~126 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=5b0faa454c09fbf20af11673272647963324a17e;p=thirdparty%2Fkernel%2Fstable-queue.git 4.19-stable patches added patches: alsa-hda-add-clevo-w65_67sb-the-power_save-blacklist.patch kvm-arm-arm64-correct-aarch32-spsr-on-exception-entry.patch kvm-arm-arm64-correct-cpsr-on-exception-entry.patch kvm-arm64-correct-pstate-on-exception-entry.patch kvm-arm64-only-sign-extend-mmio-up-to-register-width.patch mips-boot-fix-typo-in-vmlinux.lzma.its-target.patch mips-fix-indentation-of-the-relocs-message.patch powerpc-pseries-advance-pfn-if-section-is-not-present-in-lmb_is_removable.patch powerpc-xmon-don-t-access-asdr-in-vms.patch s390-mm-fix-dynamic-pagetable-upgrade-for-hugetlbfs.patch --- diff --git a/queue-4.19/alsa-hda-add-clevo-w65_67sb-the-power_save-blacklist.patch b/queue-4.19/alsa-hda-add-clevo-w65_67sb-the-power_save-blacklist.patch new file mode 100644 index 00000000000..82512378639 --- /dev/null +++ b/queue-4.19/alsa-hda-add-clevo-w65_67sb-the-power_save-blacklist.patch @@ -0,0 +1,37 @@ +From d8feb6080bb0c9f4d799a423d9453048fdd06990 Mon Sep 17 00:00:00 2001 +From: Hans de Goede +Date: Sat, 25 Jan 2020 19:10:21 +0100 +Subject: ALSA: hda: Add Clevo W65_67SB the power_save blacklist + +From: Hans de Goede + +commit d8feb6080bb0c9f4d799a423d9453048fdd06990 upstream. + +Using HDA power-saving on the Clevo W65_67SB causes the first 0.5 +seconds of audio to be missing every time audio starts playing. + +This commit adds the Clevo W65_67SB the power_save blacklist to avoid +this issue. + +Cc: stable@vger.kernel.org +BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1525104 +Signed-off-by: Hans de Goede +Link: https://lore.kernel.org/r/20200125181021.70446-1-hdegoede@redhat.com +Signed-off-by: Takashi Iwai +Signed-off-by: Greg Kroah-Hartman + +--- + sound/pci/hda/hda_intel.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/sound/pci/hda/hda_intel.c ++++ b/sound/pci/hda/hda_intel.c +@@ -2324,6 +2324,8 @@ static struct snd_pci_quirk power_save_b + /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */ + SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0), + /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ ++ SND_PCI_QUIRK(0x1558, 0x6504, "Clevo W65_67SB", 0), ++ /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ + SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), + /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ + /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ diff --git a/queue-4.19/kvm-arm-arm64-correct-aarch32-spsr-on-exception-entry.patch b/queue-4.19/kvm-arm-arm64-correct-aarch32-spsr-on-exception-entry.patch new file mode 100644 index 00000000000..e7bfa0cfb87 --- /dev/null +++ b/queue-4.19/kvm-arm-arm64-correct-aarch32-spsr-on-exception-entry.patch @@ -0,0 +1,125 @@ +From 1cfbb484de158e378e8971ac40f3082e53ecca55 Mon Sep 17 00:00:00 2001 +From: Mark Rutland +Date: Wed, 8 Jan 2020 13:43:24 +0000 +Subject: KVM: arm/arm64: Correct AArch32 SPSR on exception entry + +From: Mark Rutland + +commit 1cfbb484de158e378e8971ac40f3082e53ecca55 upstream. + +Confusingly, there are three SPSR layouts that a kernel may need to deal +with: + +(1) An AArch64 SPSR_ELx view of an AArch64 pstate +(2) An AArch64 SPSR_ELx view of an AArch32 pstate +(3) An AArch32 SPSR_* view of an AArch32 pstate + +When the KVM AArch32 support code deals with SPSR_{EL2,HYP}, it's either +dealing with #2 or #3 consistently. On arm64 the PSR_AA32_* definitions +match the AArch64 SPSR_ELx view, and on arm the PSR_AA32_* definitions +match the AArch32 SPSR_* view. + +However, when we inject an exception into an AArch32 guest, we have to +synthesize the AArch32 SPSR_* that the guest will see. Thus, an AArch64 +host needs to synthesize layout #3 from layout #2. + +This patch adds a new host_spsr_to_spsr32() helper for this, and makes +use of it in the KVM AArch32 support code. For arm64 we need to shuffle +the DIT bit around, and remove the SS bit, while for arm we can use the +value as-is. + +I've open-coded the bit manipulation for now to avoid having to rework +the existing PSR_* definitions into PSR64_AA32_* and PSR32_AA32_* +definitions. I hope to perform a more thorough refactoring in future so +that we can handle pstate view manipulation more consistently across the +kernel tree. + +Signed-off-by: Mark Rutland +Signed-off-by: Marc Zyngier +Reviewed-by: Alexandru Elisei +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20200108134324.46500-4-mark.rutland@arm.com +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/include/asm/kvm_emulate.h | 5 +++++ + arch/arm64/include/asm/kvm_emulate.h | 32 ++++++++++++++++++++++++++++++++ + virt/kvm/arm/aarch32.c | 6 +++--- + 3 files changed, 40 insertions(+), 3 deletions(-) + +--- a/arch/arm/include/asm/kvm_emulate.h ++++ b/arch/arm/include/asm/kvm_emulate.h +@@ -65,6 +65,11 @@ static inline void vcpu_write_spsr(struc + *__vcpu_spsr(vcpu) = v; + } + ++static inline unsigned long host_spsr_to_spsr32(unsigned long spsr) ++{ ++ return spsr; ++} ++ + static inline unsigned long vcpu_get_reg(struct kvm_vcpu *vcpu, + u8 reg_num) + { +--- a/arch/arm64/include/asm/kvm_emulate.h ++++ b/arch/arm64/include/asm/kvm_emulate.h +@@ -202,6 +202,38 @@ static inline void vcpu_write_spsr(struc + vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1] = v; + } + ++/* ++ * The layout of SPSR for an AArch32 state is different when observed from an ++ * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32 ++ * view given an AArch64 view. ++ * ++ * In ARM DDI 0487E.a see: ++ * ++ * - The AArch64 view (SPSR_EL2) in section C5.2.18, page C5-426 ++ * - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256 ++ * - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280 ++ * ++ * Which show the following differences: ++ * ++ * | Bit | AA64 | AA32 | Notes | ++ * +-----+------+------+-----------------------------| ++ * | 24 | DIT | J | J is RES0 in ARMv8 | ++ * | 21 | SS | DIT | SS doesn't exist in AArch32 | ++ * ++ * ... and all other bits are (currently) common. ++ */ ++static inline unsigned long host_spsr_to_spsr32(unsigned long spsr) ++{ ++ const unsigned long overlap = BIT(24) | BIT(21); ++ unsigned long dit = !!(spsr & PSR_AA32_DIT_BIT); ++ ++ spsr &= ~overlap; ++ ++ spsr |= dit << 21; ++ ++ return spsr; ++} ++ + static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu) + { + u32 mode; +--- a/virt/kvm/arm/aarch32.c ++++ b/virt/kvm/arm/aarch32.c +@@ -140,15 +140,15 @@ static unsigned long get_except32_cpsr(s + + static void prepare_fault32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset) + { +- unsigned long new_spsr_value = *vcpu_cpsr(vcpu); +- bool is_thumb = (new_spsr_value & PSR_AA32_T_BIT); ++ unsigned long spsr = *vcpu_cpsr(vcpu); ++ bool is_thumb = (spsr & PSR_AA32_T_BIT); + u32 return_offset = return_offsets[vect_offset >> 2][is_thumb]; + u32 sctlr = vcpu_cp15(vcpu, c1_SCTLR); + + *vcpu_cpsr(vcpu) = get_except32_cpsr(vcpu, mode); + + /* Note: These now point to the banked copies */ +- vcpu_write_spsr(vcpu, new_spsr_value); ++ vcpu_write_spsr(vcpu, host_spsr_to_spsr32(spsr)); + *vcpu_reg32(vcpu, 14) = *vcpu_pc(vcpu) + return_offset; + + /* Branch to exception vector */ diff --git a/queue-4.19/kvm-arm-arm64-correct-cpsr-on-exception-entry.patch b/queue-4.19/kvm-arm-arm64-correct-cpsr-on-exception-entry.patch new file mode 100644 index 00000000000..3809054b2df --- /dev/null +++ b/queue-4.19/kvm-arm-arm64-correct-cpsr-on-exception-entry.patch @@ -0,0 +1,217 @@ +From 3c2483f15499b877ccb53250d88addb8c91da147 Mon Sep 17 00:00:00 2001 +From: Mark Rutland +Date: Wed, 8 Jan 2020 13:43:23 +0000 +Subject: KVM: arm/arm64: Correct CPSR on exception entry + +From: Mark Rutland + +commit 3c2483f15499b877ccb53250d88addb8c91da147 upstream. + +When KVM injects an exception into a guest, it generates the CPSR value +from scratch, configuring CPSR.{M,A,I,T,E}, and setting all other +bits to zero. + +This isn't correct, as the architecture specifies that some CPSR bits +are (conditionally) cleared or set upon an exception, and others are +unchanged from the original context. + +This patch adds logic to match the architectural behaviour. To make this +simple to follow/audit/extend, documentation references are provided, +and bits are configured in order of their layout in SPSR_EL2. This +layout can be seen in the diagram on ARM DDI 0487E.a page C5-426. + +Note that this code is used by both arm and arm64, and is intended to +fuction with the SPSR_EL2 and SPSR_HYP layouts. + +Signed-off-by: Mark Rutland +Signed-off-by: Marc Zyngier +Reviewed-by: Alexandru Elisei +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20200108134324.46500-3-mark.rutland@arm.com +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/include/asm/kvm_emulate.h | 12 ++++ + arch/arm64/include/asm/ptrace.h | 1 + virt/kvm/arm/aarch32.c | 111 +++++++++++++++++++++++++++++++++---- + 3 files changed, 114 insertions(+), 10 deletions(-) + +--- a/arch/arm/include/asm/kvm_emulate.h ++++ b/arch/arm/include/asm/kvm_emulate.h +@@ -26,13 +26,25 @@ + #include + + /* arm64 compatibility macros */ ++#define PSR_AA32_MODE_FIQ FIQ_MODE ++#define PSR_AA32_MODE_SVC SVC_MODE + #define PSR_AA32_MODE_ABT ABT_MODE + #define PSR_AA32_MODE_UND UND_MODE + #define PSR_AA32_T_BIT PSR_T_BIT ++#define PSR_AA32_F_BIT PSR_F_BIT + #define PSR_AA32_I_BIT PSR_I_BIT + #define PSR_AA32_A_BIT PSR_A_BIT + #define PSR_AA32_E_BIT PSR_E_BIT + #define PSR_AA32_IT_MASK PSR_IT_MASK ++#define PSR_AA32_GE_MASK 0x000f0000 ++#define PSR_AA32_DIT_BIT 0x00200000 ++#define PSR_AA32_PAN_BIT 0x00400000 ++#define PSR_AA32_SSBS_BIT 0x00800000 ++#define PSR_AA32_Q_BIT PSR_Q_BIT ++#define PSR_AA32_V_BIT PSR_V_BIT ++#define PSR_AA32_C_BIT PSR_C_BIT ++#define PSR_AA32_Z_BIT PSR_Z_BIT ++#define PSR_AA32_N_BIT PSR_N_BIT + + unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num); + +--- a/arch/arm64/include/asm/ptrace.h ++++ b/arch/arm64/include/asm/ptrace.h +@@ -50,6 +50,7 @@ + #define PSR_AA32_I_BIT 0x00000080 + #define PSR_AA32_A_BIT 0x00000100 + #define PSR_AA32_E_BIT 0x00000200 ++#define PSR_AA32_PAN_BIT 0x00400000 + #define PSR_AA32_SSBS_BIT 0x00800000 + #define PSR_AA32_DIT_BIT 0x01000000 + #define PSR_AA32_Q_BIT 0x08000000 +--- a/virt/kvm/arm/aarch32.c ++++ b/virt/kvm/arm/aarch32.c +@@ -21,6 +21,7 @@ + * along with this program. If not, see . + */ + ++#include + #include + #include + #include +@@ -39,22 +40,112 @@ static const u8 return_offsets[8][2] = { + [7] = { 4, 4 }, /* FIQ, unused */ + }; + ++/* ++ * When an exception is taken, most CPSR fields are left unchanged in the ++ * handler. However, some are explicitly overridden (e.g. M[4:0]). ++ * ++ * The SPSR/SPSR_ELx layouts differ, and the below is intended to work with ++ * either format. Note: SPSR.J bit doesn't exist in SPSR_ELx, but this bit was ++ * obsoleted by the ARMv7 virtualization extensions and is RES0. ++ * ++ * For the SPSR layout seen from AArch32, see: ++ * - ARM DDI 0406C.d, page B1-1148 ++ * - ARM DDI 0487E.a, page G8-6264 ++ * ++ * For the SPSR_ELx layout for AArch32 seen from AArch64, see: ++ * - ARM DDI 0487E.a, page C5-426 ++ * ++ * Here we manipulate the fields in order of the AArch32 SPSR_ELx layout, from ++ * MSB to LSB. ++ */ ++static unsigned long get_except32_cpsr(struct kvm_vcpu *vcpu, u32 mode) ++{ ++ u32 sctlr = vcpu_cp15(vcpu, c1_SCTLR); ++ unsigned long old, new; ++ ++ old = *vcpu_cpsr(vcpu); ++ new = 0; ++ ++ new |= (old & PSR_AA32_N_BIT); ++ new |= (old & PSR_AA32_Z_BIT); ++ new |= (old & PSR_AA32_C_BIT); ++ new |= (old & PSR_AA32_V_BIT); ++ new |= (old & PSR_AA32_Q_BIT); ++ ++ // CPSR.IT[7:0] are set to zero upon any exception ++ // See ARM DDI 0487E.a, section G1.12.3 ++ // See ARM DDI 0406C.d, section B1.8.3 ++ ++ new |= (old & PSR_AA32_DIT_BIT); ++ ++ // CPSR.SSBS is set to SCTLR.DSSBS upon any exception ++ // See ARM DDI 0487E.a, page G8-6244 ++ if (sctlr & BIT(31)) ++ new |= PSR_AA32_SSBS_BIT; ++ ++ // CPSR.PAN is unchanged unless SCTLR.SPAN == 0b0 ++ // SCTLR.SPAN is RES1 when ARMv8.1-PAN is not implemented ++ // See ARM DDI 0487E.a, page G8-6246 ++ new |= (old & PSR_AA32_PAN_BIT); ++ if (!(sctlr & BIT(23))) ++ new |= PSR_AA32_PAN_BIT; ++ ++ // SS does not exist in AArch32, so ignore ++ ++ // CPSR.IL is set to zero upon any exception ++ // See ARM DDI 0487E.a, page G1-5527 ++ ++ new |= (old & PSR_AA32_GE_MASK); ++ ++ // CPSR.IT[7:0] are set to zero upon any exception ++ // See prior comment above ++ ++ // CPSR.E is set to SCTLR.EE upon any exception ++ // See ARM DDI 0487E.a, page G8-6245 ++ // See ARM DDI 0406C.d, page B4-1701 ++ if (sctlr & BIT(25)) ++ new |= PSR_AA32_E_BIT; ++ ++ // CPSR.A is unchanged upon an exception to Undefined, Supervisor ++ // CPSR.A is set upon an exception to other modes ++ // See ARM DDI 0487E.a, pages G1-5515 to G1-5516 ++ // See ARM DDI 0406C.d, page B1-1182 ++ new |= (old & PSR_AA32_A_BIT); ++ if (mode != PSR_AA32_MODE_UND && mode != PSR_AA32_MODE_SVC) ++ new |= PSR_AA32_A_BIT; ++ ++ // CPSR.I is set upon any exception ++ // See ARM DDI 0487E.a, pages G1-5515 to G1-5516 ++ // See ARM DDI 0406C.d, page B1-1182 ++ new |= PSR_AA32_I_BIT; ++ ++ // CPSR.F is set upon an exception to FIQ ++ // CPSR.F is unchanged upon an exception to other modes ++ // See ARM DDI 0487E.a, pages G1-5515 to G1-5516 ++ // See ARM DDI 0406C.d, page B1-1182 ++ new |= (old & PSR_AA32_F_BIT); ++ if (mode == PSR_AA32_MODE_FIQ) ++ new |= PSR_AA32_F_BIT; ++ ++ // CPSR.T is set to SCTLR.TE upon any exception ++ // See ARM DDI 0487E.a, page G8-5514 ++ // See ARM DDI 0406C.d, page B1-1181 ++ if (sctlr & BIT(30)) ++ new |= PSR_AA32_T_BIT; ++ ++ new |= mode; ++ ++ return new; ++} ++ + static void prepare_fault32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset) + { +- unsigned long cpsr; + unsigned long new_spsr_value = *vcpu_cpsr(vcpu); + bool is_thumb = (new_spsr_value & PSR_AA32_T_BIT); + u32 return_offset = return_offsets[vect_offset >> 2][is_thumb]; + u32 sctlr = vcpu_cp15(vcpu, c1_SCTLR); + +- cpsr = mode | PSR_AA32_I_BIT; +- +- if (sctlr & (1 << 30)) +- cpsr |= PSR_AA32_T_BIT; +- if (sctlr & (1 << 25)) +- cpsr |= PSR_AA32_E_BIT; +- +- *vcpu_cpsr(vcpu) = cpsr; ++ *vcpu_cpsr(vcpu) = get_except32_cpsr(vcpu, mode); + + /* Note: These now point to the banked copies */ + vcpu_write_spsr(vcpu, new_spsr_value); +@@ -95,7 +186,7 @@ static void inject_abt32(struct kvm_vcpu + fsr = &vcpu_cp15(vcpu, c5_DFSR); + } + +- prepare_fault32(vcpu, PSR_AA32_MODE_ABT | PSR_AA32_A_BIT, vect_offset); ++ prepare_fault32(vcpu, PSR_AA32_MODE_ABT, vect_offset); + + *far = addr; + diff --git a/queue-4.19/kvm-arm64-correct-pstate-on-exception-entry.patch b/queue-4.19/kvm-arm64-correct-pstate-on-exception-entry.patch new file mode 100644 index 00000000000..88c83d9cdd6 --- /dev/null +++ b/queue-4.19/kvm-arm64-correct-pstate-on-exception-entry.patch @@ -0,0 +1,144 @@ +From a425372e733177eb0779748956bc16c85167af48 Mon Sep 17 00:00:00 2001 +From: Mark Rutland +Date: Wed, 8 Jan 2020 13:43:22 +0000 +Subject: KVM: arm64: Correct PSTATE on exception entry + +From: Mark Rutland + +commit a425372e733177eb0779748956bc16c85167af48 upstream. + +When KVM injects an exception into a guest, it generates the PSTATE +value from scratch, configuring PSTATE.{M[4:0],DAIF}, and setting all +other bits to zero. + +This isn't correct, as the architecture specifies that some PSTATE bits +are (conditionally) cleared or set upon an exception, and others are +unchanged from the original context. + +This patch adds logic to match the architectural behaviour. To make this +simple to follow/audit/extend, documentation references are provided, +and bits are configured in order of their layout in SPSR_EL2. This +layout can be seen in the diagram on ARM DDI 0487E.a page C5-429. + +Signed-off-by: Mark Rutland +Signed-off-by: Marc Zyngier +Reviewed-by: Alexandru Elisei +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20200108134324.46500-2-mark.rutland@arm.com +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm64/include/uapi/asm/ptrace.h | 1 + arch/arm64/kvm/inject_fault.c | 70 ++++++++++++++++++++++++++++++++--- + 2 files changed, 66 insertions(+), 5 deletions(-) + +--- a/arch/arm64/include/uapi/asm/ptrace.h ++++ b/arch/arm64/include/uapi/asm/ptrace.h +@@ -49,6 +49,7 @@ + #define PSR_SSBS_BIT 0x00001000 + #define PSR_PAN_BIT 0x00400000 + #define PSR_UAO_BIT 0x00800000 ++#define PSR_DIT_BIT 0x01000000 + #define PSR_V_BIT 0x10000000 + #define PSR_C_BIT 0x20000000 + #define PSR_Z_BIT 0x40000000 +--- a/arch/arm64/kvm/inject_fault.c ++++ b/arch/arm64/kvm/inject_fault.c +@@ -25,9 +25,6 @@ + #include + #include + +-#define PSTATE_FAULT_BITS_64 (PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | \ +- PSR_I_BIT | PSR_D_BIT) +- + #define CURRENT_EL_SP_EL0_VECTOR 0x0 + #define CURRENT_EL_SP_ELx_VECTOR 0x200 + #define LOWER_EL_AArch64_VECTOR 0x400 +@@ -61,6 +58,69 @@ static u64 get_except_vector(struct kvm_ + return vcpu_read_sys_reg(vcpu, VBAR_EL1) + exc_offset + type; + } + ++/* ++ * When an exception is taken, most PSTATE fields are left unchanged in the ++ * handler. However, some are explicitly overridden (e.g. M[4:0]). Luckily all ++ * of the inherited bits have the same position in the AArch64/AArch32 SPSR_ELx ++ * layouts, so we don't need to shuffle these for exceptions from AArch32 EL0. ++ * ++ * For the SPSR_ELx layout for AArch64, see ARM DDI 0487E.a page C5-429. ++ * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426. ++ * ++ * Here we manipulate the fields in order of the AArch64 SPSR_ELx layout, from ++ * MSB to LSB. ++ */ ++static unsigned long get_except64_pstate(struct kvm_vcpu *vcpu) ++{ ++ unsigned long sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1); ++ unsigned long old, new; ++ ++ old = *vcpu_cpsr(vcpu); ++ new = 0; ++ ++ new |= (old & PSR_N_BIT); ++ new |= (old & PSR_Z_BIT); ++ new |= (old & PSR_C_BIT); ++ new |= (old & PSR_V_BIT); ++ ++ // TODO: TCO (if/when ARMv8.5-MemTag is exposed to guests) ++ ++ new |= (old & PSR_DIT_BIT); ++ ++ // PSTATE.UAO is set to zero upon any exception to AArch64 ++ // See ARM DDI 0487E.a, page D5-2579. ++ ++ // PSTATE.PAN is unchanged unless SCTLR_ELx.SPAN == 0b0 ++ // SCTLR_ELx.SPAN is RES1 when ARMv8.1-PAN is not implemented ++ // See ARM DDI 0487E.a, page D5-2578. ++ new |= (old & PSR_PAN_BIT); ++ if (!(sctlr & SCTLR_EL1_SPAN)) ++ new |= PSR_PAN_BIT; ++ ++ // PSTATE.SS is set to zero upon any exception to AArch64 ++ // See ARM DDI 0487E.a, page D2-2452. ++ ++ // PSTATE.IL is set to zero upon any exception to AArch64 ++ // See ARM DDI 0487E.a, page D1-2306. ++ ++ // PSTATE.SSBS is set to SCTLR_ELx.DSSBS upon any exception to AArch64 ++ // See ARM DDI 0487E.a, page D13-3258 ++ if (sctlr & SCTLR_ELx_DSSBS) ++ new |= PSR_SSBS_BIT; ++ ++ // PSTATE.BTYPE is set to zero upon any exception to AArch64 ++ // See ARM DDI 0487E.a, pages D1-2293 to D1-2294. ++ ++ new |= PSR_D_BIT; ++ new |= PSR_A_BIT; ++ new |= PSR_I_BIT; ++ new |= PSR_F_BIT; ++ ++ new |= PSR_MODE_EL1h; ++ ++ return new; ++} ++ + static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr) + { + unsigned long cpsr = *vcpu_cpsr(vcpu); +@@ -70,7 +130,7 @@ static void inject_abt64(struct kvm_vcpu + vcpu_write_elr_el1(vcpu, *vcpu_pc(vcpu)); + *vcpu_pc(vcpu) = get_except_vector(vcpu, except_type_sync); + +- *vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64; ++ *vcpu_cpsr(vcpu) = get_except64_pstate(vcpu); + vcpu_write_spsr(vcpu, cpsr); + + vcpu_write_sys_reg(vcpu, addr, FAR_EL1); +@@ -105,7 +165,7 @@ static void inject_undef64(struct kvm_vc + vcpu_write_elr_el1(vcpu, *vcpu_pc(vcpu)); + *vcpu_pc(vcpu) = get_except_vector(vcpu, except_type_sync); + +- *vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64; ++ *vcpu_cpsr(vcpu) = get_except64_pstate(vcpu); + vcpu_write_spsr(vcpu, cpsr); + + /* diff --git a/queue-4.19/kvm-arm64-only-sign-extend-mmio-up-to-register-width.patch b/queue-4.19/kvm-arm64-only-sign-extend-mmio-up-to-register-width.patch new file mode 100644 index 00000000000..9afcf28b27b --- /dev/null +++ b/queue-4.19/kvm-arm64-only-sign-extend-mmio-up-to-register-width.patch @@ -0,0 +1,125 @@ +From b6ae256afd32f96bec0117175b329d0dd617655e Mon Sep 17 00:00:00 2001 +From: Christoffer Dall +Date: Thu, 12 Dec 2019 20:50:55 +0100 +Subject: KVM: arm64: Only sign-extend MMIO up to register width + +From: Christoffer Dall + +commit b6ae256afd32f96bec0117175b329d0dd617655e upstream. + +On AArch64 you can do a sign-extended load to either a 32-bit or 64-bit +register, and we should only sign extend the register up to the width of +the register as specified in the operation (by using the 32-bit Wn or +64-bit Xn register specifier). + +As it turns out, the architecture provides this decoding information in +the SF ("Sixty-Four" -- how cute...) bit. + +Let's take advantage of this with the usual 32-bit/64-bit header file +dance and do the right thing on AArch64 hosts. + +Signed-off-by: Christoffer Dall +Signed-off-by: Marc Zyngier +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20191212195055.5541-1-christoffer.dall@arm.com +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/include/asm/kvm_emulate.h | 5 +++++ + arch/arm/include/asm/kvm_mmio.h | 2 ++ + arch/arm64/include/asm/kvm_emulate.h | 5 +++++ + arch/arm64/include/asm/kvm_mmio.h | 6 ++---- + virt/kvm/arm/mmio.c | 6 ++++++ + 5 files changed, 20 insertions(+), 4 deletions(-) + +--- a/arch/arm/include/asm/kvm_emulate.h ++++ b/arch/arm/include/asm/kvm_emulate.h +@@ -206,6 +206,11 @@ static inline bool kvm_vcpu_dabt_issext( + return kvm_vcpu_get_hsr(vcpu) & HSR_SSE; + } + ++static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu) ++{ ++ return false; ++} ++ + static inline int kvm_vcpu_dabt_get_rd(struct kvm_vcpu *vcpu) + { + return (kvm_vcpu_get_hsr(vcpu) & HSR_SRT_MASK) >> HSR_SRT_SHIFT; +--- a/arch/arm/include/asm/kvm_mmio.h ++++ b/arch/arm/include/asm/kvm_mmio.h +@@ -26,6 +26,8 @@ + struct kvm_decode { + unsigned long rt; + bool sign_extend; ++ /* Not used on 32-bit arm */ ++ bool sixty_four; + }; + + void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); +--- a/arch/arm64/include/asm/kvm_emulate.h ++++ b/arch/arm64/include/asm/kvm_emulate.h +@@ -293,6 +293,11 @@ static inline bool kvm_vcpu_dabt_issext( + return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SSE); + } + ++static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu) ++{ ++ return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SF); ++} ++ + static inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu) + { + return (kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT; +--- a/arch/arm64/include/asm/kvm_mmio.h ++++ b/arch/arm64/include/asm/kvm_mmio.h +@@ -21,13 +21,11 @@ + #include + #include + +-/* +- * This is annoying. The mmio code requires this, even if we don't +- * need any decoding. To be fixed. +- */ + struct kvm_decode { + unsigned long rt; + bool sign_extend; ++ /* Witdth of the register accessed by the faulting instruction is 64-bits */ ++ bool sixty_four; + }; + + void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); +--- a/virt/kvm/arm/mmio.c ++++ b/virt/kvm/arm/mmio.c +@@ -117,6 +117,9 @@ int kvm_handle_mmio_return(struct kvm_vc + data = (data ^ mask) - mask; + } + ++ if (!vcpu->arch.mmio_decode.sixty_four) ++ data = data & 0xffffffff; ++ + trace_kvm_mmio(KVM_TRACE_MMIO_READ, len, run->mmio.phys_addr, + &data); + data = vcpu_data_host_to_guest(vcpu, data, len); +@@ -137,6 +140,7 @@ static int decode_hsr(struct kvm_vcpu *v + unsigned long rt; + int access_size; + bool sign_extend; ++ bool sixty_four; + + if (kvm_vcpu_dabt_iss1tw(vcpu)) { + /* page table accesses IO mem: tell guest to fix its TTBR */ +@@ -150,11 +154,13 @@ static int decode_hsr(struct kvm_vcpu *v + + *is_write = kvm_vcpu_dabt_iswrite(vcpu); + sign_extend = kvm_vcpu_dabt_issext(vcpu); ++ sixty_four = kvm_vcpu_dabt_issf(vcpu); + rt = kvm_vcpu_dabt_get_rd(vcpu); + + *len = access_size; + vcpu->arch.mmio_decode.sign_extend = sign_extend; + vcpu->arch.mmio_decode.rt = rt; ++ vcpu->arch.mmio_decode.sixty_four = sixty_four; + + return 0; + } diff --git a/queue-4.19/mips-boot-fix-typo-in-vmlinux.lzma.its-target.patch b/queue-4.19/mips-boot-fix-typo-in-vmlinux.lzma.its-target.patch new file mode 100644 index 00000000000..978c97d450c --- /dev/null +++ b/queue-4.19/mips-boot-fix-typo-in-vmlinux.lzma.its-target.patch @@ -0,0 +1,41 @@ +From 16202c09577f3d0c533274c0410b7de05fb0d458 Mon Sep 17 00:00:00 2001 +From: Alexander Lobakin +Date: Fri, 17 Jan 2020 17:02:08 +0300 +Subject: MIPS: boot: fix typo in 'vmlinux.lzma.its' target + +From: Alexander Lobakin + +commit 16202c09577f3d0c533274c0410b7de05fb0d458 upstream. + +Commit 92b34a976348 ("MIPS: boot: add missing targets for vmlinux.*.its") +fixed constant rebuild of *.its files on every make invocation, but due +to typo ("lzmo") it made no sense for vmlinux.lzma.its. + +Fixes: 92b34a976348 ("MIPS: boot: add missing targets for vmlinux.*.its") +Cc: # v4.19+ +Signed-off-by: Alexander Lobakin +[paulburton@kernel.org: s/invokation/invocation/] +Signed-off-by: Paul Burton +Cc: Ralf Baechle +Cc: James Hogan +Cc: Masahiro Yamada +Cc: Rob Herring +Cc: linux-mips@vger.kernel.org +Cc: linux-kernel@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/boot/Makefile | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/mips/boot/Makefile ++++ b/arch/mips/boot/Makefile +@@ -123,7 +123,7 @@ $(obj)/vmlinux.its.S: $(addprefix $(srct + targets += vmlinux.its + targets += vmlinux.gz.its + targets += vmlinux.bz2.its +-targets += vmlinux.lzmo.its ++targets += vmlinux.lzma.its + targets += vmlinux.lzo.its + + quiet_cmd_cpp_its_S = ITS $@ diff --git a/queue-4.19/mips-fix-indentation-of-the-relocs-message.patch b/queue-4.19/mips-fix-indentation-of-the-relocs-message.patch new file mode 100644 index 00000000000..98cafed30c5 --- /dev/null +++ b/queue-4.19/mips-fix-indentation-of-the-relocs-message.patch @@ -0,0 +1,61 @@ +From a53998802e178451701d59d38e36f551422977ba Mon Sep 17 00:00:00 2001 +From: Alexander Lobakin +Date: Fri, 17 Jan 2020 17:02:07 +0300 +Subject: MIPS: fix indentation of the 'RELOCS' message + +From: Alexander Lobakin + +commit a53998802e178451701d59d38e36f551422977ba upstream. + +quiet_cmd_relocs lacks a whitespace which results in: + + LD vmlinux + SORTEX vmlinux + SYSMAP System.map + RELOCS vmlinux + Building modules, stage 2. + MODPOST 64 modules + +After this patch: + + LD vmlinux + SORTEX vmlinux + SYSMAP System.map + RELOCS vmlinux + Building modules, stage 2. + MODPOST 64 modules + +Typo is present in kernel tree since the introduction of relocatable +kernel support in commit e818fac595ab ("MIPS: Generate relocation table +when CONFIG_RELOCATABLE"), but the relocation scripts were moved to +Makefile.postlink later with commit 44079d3509ae ("MIPS: Use +Makefile.postlink to insert relocations into vmlinux"). + +Fixes: 44079d3509ae ("MIPS: Use Makefile.postlink to insert relocations into vmlinux") +Cc: # v4.11+ +Signed-off-by: Alexander Lobakin +[paulburton@kernel.org: Fixup commit references in commit message.] +Signed-off-by: Paul Burton +Cc: Ralf Baechle +Cc: James Hogan +Cc: Masahiro Yamada +Cc: Rob Herring +Cc: linux-mips@vger.kernel.org +Cc: linux-kernel@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/Makefile.postlink | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/mips/Makefile.postlink ++++ b/arch/mips/Makefile.postlink +@@ -12,7 +12,7 @@ __archpost: + include scripts/Kbuild.include + + CMD_RELOCS = arch/mips/boot/tools/relocs +-quiet_cmd_relocs = RELOCS $@ ++quiet_cmd_relocs = RELOCS $@ + cmd_relocs = $(CMD_RELOCS) $@ + + # `@true` prevents complaint when there is nothing to be done diff --git a/queue-4.19/powerpc-pseries-advance-pfn-if-section-is-not-present-in-lmb_is_removable.patch b/queue-4.19/powerpc-pseries-advance-pfn-if-section-is-not-present-in-lmb_is_removable.patch new file mode 100644 index 00000000000..6a712f91c8a --- /dev/null +++ b/queue-4.19/powerpc-pseries-advance-pfn-if-section-is-not-present-in-lmb_is_removable.patch @@ -0,0 +1,38 @@ +From fbee6ba2dca30d302efe6bddb3a886f5e964a257 Mon Sep 17 00:00:00 2001 +From: Pingfan Liu +Date: Fri, 10 Jan 2020 12:54:02 +0800 +Subject: powerpc/pseries: Advance pfn if section is not present in lmb_is_removable() + +From: Pingfan Liu + +commit fbee6ba2dca30d302efe6bddb3a886f5e964a257 upstream. + +In lmb_is_removable(), if a section is not present, it should continue +to test the rest of the sections in the block. But the current code +fails to do so. + +Fixes: 51925fb3c5c9 ("powerpc/pseries: Implement memory hotplug remove in the kernel") +Cc: stable@vger.kernel.org # v4.1+ +Signed-off-by: Pingfan Liu +Signed-off-by: Michael Ellerman +Link: https://lore.kernel.org/r/1578632042-12415-1-git-send-email-kernelfans@gmail.com +Signed-off-by: Greg Kroah-Hartman + +--- + arch/powerpc/platforms/pseries/hotplug-memory.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/arch/powerpc/platforms/pseries/hotplug-memory.c ++++ b/arch/powerpc/platforms/pseries/hotplug-memory.c +@@ -366,8 +366,10 @@ static bool lmb_is_removable(struct drme + + for (i = 0; i < scns_per_block; i++) { + pfn = PFN_DOWN(phys_addr); +- if (!pfn_present(pfn)) ++ if (!pfn_present(pfn)) { ++ phys_addr += MIN_MEMORY_BLOCK_SIZE; + continue; ++ } + + rc &= is_mem_section_removable(pfn, PAGES_PER_SECTION); + phys_addr += MIN_MEMORY_BLOCK_SIZE; diff --git a/queue-4.19/powerpc-xmon-don-t-access-asdr-in-vms.patch b/queue-4.19/powerpc-xmon-don-t-access-asdr-in-vms.patch new file mode 100644 index 00000000000..f4e812eb6b9 --- /dev/null +++ b/queue-4.19/powerpc-xmon-don-t-access-asdr-in-vms.patch @@ -0,0 +1,46 @@ +From c2a20711fc181e7f22ee5c16c28cb9578af84729 Mon Sep 17 00:00:00 2001 +From: Sukadev Bhattiprolu +Date: Mon, 6 Jan 2020 13:50:02 -0600 +Subject: powerpc/xmon: don't access ASDR in VMs + +From: Sukadev Bhattiprolu + +commit c2a20711fc181e7f22ee5c16c28cb9578af84729 upstream. + +ASDR is HV-privileged and must only be accessed in HV-mode. +Fixes a Program Check (0x700) when xmon in a VM dumps SPRs. + +Fixes: d1e1b351f50f ("powerpc/xmon: Add ISA v3.0 SPRs to SPR dump") +Cc: stable@vger.kernel.org # v4.14+ +Signed-off-by: Sukadev Bhattiprolu +Reviewed-by: Andrew Donnellan +Signed-off-by: Michael Ellerman +Link: https://lore.kernel.org/r/20200107021633.GB29843@us.ibm.com +Signed-off-by: Greg Kroah-Hartman + +--- + arch/powerpc/xmon/xmon.c | 9 ++++----- + 1 file changed, 4 insertions(+), 5 deletions(-) + +--- a/arch/powerpc/xmon/xmon.c ++++ b/arch/powerpc/xmon/xmon.c +@@ -1878,15 +1878,14 @@ static void dump_300_sprs(void) + + printf("pidr = %.16lx tidr = %.16lx\n", + mfspr(SPRN_PID), mfspr(SPRN_TIDR)); +- printf("asdr = %.16lx psscr = %.16lx\n", +- mfspr(SPRN_ASDR), hv ? mfspr(SPRN_PSSCR) +- : mfspr(SPRN_PSSCR_PR)); ++ printf("psscr = %.16lx\n", ++ hv ? mfspr(SPRN_PSSCR) : mfspr(SPRN_PSSCR_PR)); + + if (!hv) + return; + +- printf("ptcr = %.16lx\n", +- mfspr(SPRN_PTCR)); ++ printf("ptcr = %.16lx asdr = %.16lx\n", ++ mfspr(SPRN_PTCR), mfspr(SPRN_ASDR)); + #endif + } + diff --git a/queue-4.19/s390-mm-fix-dynamic-pagetable-upgrade-for-hugetlbfs.patch b/queue-4.19/s390-mm-fix-dynamic-pagetable-upgrade-for-hugetlbfs.patch new file mode 100644 index 00000000000..dcacc55b113 --- /dev/null +++ b/queue-4.19/s390-mm-fix-dynamic-pagetable-upgrade-for-hugetlbfs.patch @@ -0,0 +1,181 @@ +From 5f490a520bcb393389a4d44bec90afcb332eb112 Mon Sep 17 00:00:00 2001 +From: Gerald Schaefer +Date: Thu, 16 Jan 2020 19:59:04 +0100 +Subject: s390/mm: fix dynamic pagetable upgrade for hugetlbfs + +From: Gerald Schaefer + +commit 5f490a520bcb393389a4d44bec90afcb332eb112 upstream. + +Commit ee71d16d22bb ("s390/mm: make TASK_SIZE independent from the number +of page table levels") changed the logic of TASK_SIZE and also removed the +arch_mmap_check() implementation for s390. This combination has a subtle +effect on how get_unmapped_area() for hugetlbfs pages works. It is now +possible that a user process establishes a hugetlbfs mapping at an address +above 4 TB, without triggering a dynamic pagetable upgrade from 3 to 4 +levels. + +This is because hugetlbfs mappings will not use mm->get_unmapped_area, but +rather file->f_op->get_unmapped_area, which currently is the generic +implementation of hugetlb_get_unmapped_area() that does not know about s390 +dynamic pagetable upgrades, but with the new definition of TASK_SIZE, it +will now allow mappings above 4 TB. + +Subsequent access to such a mapped address above 4 TB will result in a page +fault loop, because the CPU cannot translate such a large address with 3 +pagetable levels. The fault handler will try to map in a hugepage at the +address, but due to the folded pagetable logic it will end up with creating +entries in the 3 level pagetable, possibly overwriting existing mappings, +and then it all repeats when the access is retried. + +Apart from the page fault loop, this can have various nasty effects, e.g. +kernel panic from one of the BUG_ON() checks in memory management code, +or even data loss if an existing mapping gets overwritten. + +Fix this by implementing HAVE_ARCH_HUGETLB_UNMAPPED_AREA support for s390, +providing an s390 version for hugetlb_get_unmapped_area() with pagetable +upgrade support similar to arch_get_unmapped_area(), which will then be +used instead of the generic version. + +Fixes: ee71d16d22bb ("s390/mm: make TASK_SIZE independent from the number of page table levels") +Cc: # 4.12+ +Signed-off-by: Gerald Schaefer +Signed-off-by: Vasily Gorbik +Signed-off-by: Greg Kroah-Hartman + +--- + arch/s390/include/asm/page.h | 2 + arch/s390/mm/hugetlbpage.c | 100 ++++++++++++++++++++++++++++++++++++++++++- + 2 files changed, 101 insertions(+), 1 deletion(-) + +--- a/arch/s390/include/asm/page.h ++++ b/arch/s390/include/asm/page.h +@@ -33,6 +33,8 @@ + #define ARCH_HAS_PREPARE_HUGEPAGE + #define ARCH_HAS_HUGEPAGE_CLEAR_FLUSH + ++#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA ++ + #include + #ifndef __ASSEMBLY__ + +--- a/arch/s390/mm/hugetlbpage.c ++++ b/arch/s390/mm/hugetlbpage.c +@@ -2,7 +2,7 @@ + /* + * IBM System z Huge TLB Page Support for Kernel. + * +- * Copyright IBM Corp. 2007,2016 ++ * Copyright IBM Corp. 2007,2020 + * Author(s): Gerald Schaefer + */ + +@@ -11,6 +11,9 @@ + + #include + #include ++#include ++#include ++#include + + /* + * If the bit selected by single-bit bitmask "a" is set within "x", move +@@ -267,3 +270,98 @@ static __init int setup_hugepagesz(char + return 1; + } + __setup("hugepagesz=", setup_hugepagesz); ++ ++static unsigned long hugetlb_get_unmapped_area_bottomup(struct file *file, ++ unsigned long addr, unsigned long len, ++ unsigned long pgoff, unsigned long flags) ++{ ++ struct hstate *h = hstate_file(file); ++ struct vm_unmapped_area_info info; ++ ++ info.flags = 0; ++ info.length = len; ++ info.low_limit = current->mm->mmap_base; ++ info.high_limit = TASK_SIZE; ++ info.align_mask = PAGE_MASK & ~huge_page_mask(h); ++ info.align_offset = 0; ++ return vm_unmapped_area(&info); ++} ++ ++static unsigned long hugetlb_get_unmapped_area_topdown(struct file *file, ++ unsigned long addr0, unsigned long len, ++ unsigned long pgoff, unsigned long flags) ++{ ++ struct hstate *h = hstate_file(file); ++ struct vm_unmapped_area_info info; ++ unsigned long addr; ++ ++ info.flags = VM_UNMAPPED_AREA_TOPDOWN; ++ info.length = len; ++ info.low_limit = max(PAGE_SIZE, mmap_min_addr); ++ info.high_limit = current->mm->mmap_base; ++ info.align_mask = PAGE_MASK & ~huge_page_mask(h); ++ info.align_offset = 0; ++ addr = vm_unmapped_area(&info); ++ ++ /* ++ * A failed mmap() very likely causes application failure, ++ * so fall back to the bottom-up function here. This scenario ++ * can happen with large stack limits and large mmap() ++ * allocations. ++ */ ++ if (addr & ~PAGE_MASK) { ++ VM_BUG_ON(addr != -ENOMEM); ++ info.flags = 0; ++ info.low_limit = TASK_UNMAPPED_BASE; ++ info.high_limit = TASK_SIZE; ++ addr = vm_unmapped_area(&info); ++ } ++ ++ return addr; ++} ++ ++unsigned long hugetlb_get_unmapped_area(struct file *file, unsigned long addr, ++ unsigned long len, unsigned long pgoff, unsigned long flags) ++{ ++ struct hstate *h = hstate_file(file); ++ struct mm_struct *mm = current->mm; ++ struct vm_area_struct *vma; ++ int rc; ++ ++ if (len & ~huge_page_mask(h)) ++ return -EINVAL; ++ if (len > TASK_SIZE - mmap_min_addr) ++ return -ENOMEM; ++ ++ if (flags & MAP_FIXED) { ++ if (prepare_hugepage_range(file, addr, len)) ++ return -EINVAL; ++ goto check_asce_limit; ++ } ++ ++ if (addr) { ++ addr = ALIGN(addr, huge_page_size(h)); ++ vma = find_vma(mm, addr); ++ if (TASK_SIZE - len >= addr && addr >= mmap_min_addr && ++ (!vma || addr + len <= vm_start_gap(vma))) ++ goto check_asce_limit; ++ } ++ ++ if (mm->get_unmapped_area == arch_get_unmapped_area) ++ addr = hugetlb_get_unmapped_area_bottomup(file, addr, len, ++ pgoff, flags); ++ else ++ addr = hugetlb_get_unmapped_area_topdown(file, addr, len, ++ pgoff, flags); ++ if (addr & ~PAGE_MASK) ++ return addr; ++ ++check_asce_limit: ++ if (addr + len > current->mm->context.asce_limit && ++ addr + len <= TASK_SIZE) { ++ rc = crst_table_upgrade(mm, addr + len); ++ if (rc) ++ return (unsigned long) rc; ++ } ++ return addr; ++} diff --git a/queue-4.19/series b/queue-4.19/series index 8ac719bc014..3320b398606 100644 --- a/queue-4.19/series +++ b/queue-4.19/series @@ -43,3 +43,13 @@ media-v4l2-rect.h-fix-v4l2_rect_map_inside-top-left-adjustments.patch lib-test_kasan.c-fix-memory-leak-in-kmalloc_oob_krealloc_more.patch irqdomain-fix-a-memory-leak-in-irq_domain_push_irq.patch platform-x86-intel_scu_ipc-fix-interrupt-support.patch +alsa-hda-add-clevo-w65_67sb-the-power_save-blacklist.patch +kvm-arm64-correct-pstate-on-exception-entry.patch +kvm-arm-arm64-correct-cpsr-on-exception-entry.patch +kvm-arm-arm64-correct-aarch32-spsr-on-exception-entry.patch +kvm-arm64-only-sign-extend-mmio-up-to-register-width.patch +mips-fix-indentation-of-the-relocs-message.patch +mips-boot-fix-typo-in-vmlinux.lzma.its-target.patch +s390-mm-fix-dynamic-pagetable-upgrade-for-hugetlbfs.patch +powerpc-xmon-don-t-access-asdr-in-vms.patch +powerpc-pseries-advance-pfn-if-section-is-not-present-in-lmb_is_removable.patch