From: Jagannadha Sutradharudu Teki <jagannadha.sutradharudu-teki@xilinx.com>
Date: Wed, 6 Mar 2013 17:42:04 +0000 (+0530)
Subject: zynq: Use standard readl/writel io routines
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=5b6ab085dfb532c9ad48d96b752223a037100626;p=thirdparty%2Fu-boot.git

zynq: Use standard readl/writel io routines

Use the standard io routines writel and readl instead
of Xil_Out32 and Xil_In32 respectively.
Implemented zynq_slcr_get_boot_mode on slcr driver.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---

diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index f91f663682d..a940067c3f1 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -113,3 +113,9 @@ void zynq_slcr_devcfg_enable(void)
 
 	zynq_slcr_lock();
 }
+
+u32 zynq_slcr_get_boot_mode(void)
+{
+	/* Get the bootmode register value */
+	return readl(&slcr_base->boot_mode);
+}
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
index 2e9e5c6c3ab..2e3f034381c 100644
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -29,5 +29,6 @@ extern void zynq_slcr_cpu_reset(void);
 extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk);
 extern void zynq_slcr_devcfg_disable(void);
 extern void zynq_slcr_devcfg_enable(void);
+extern u32 zynq_slcr_get_boot_mode(void);
 
 #endif /* _SYS_PROTO_H_ */
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index c4983c8ab18..4df6e4831e9 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -21,13 +21,13 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/nand.h>
 #include <netdev.h>
 #include <zynqpl.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
 
-#define BOOT_MODE_REG     (XPSS_SYS_CTRL_BASEADDR + 0x25C)
 #define BOOT_MODES_MASK    0x0000000F
 #define QSPI_MODE         (0x00000001)            /**< QSPI */
 #define NOR_FLASH_MODE    (0x00000002)            /**< NOR  */
@@ -37,21 +37,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define dmbp() __asm__ __volatile__ ("dmb" : : : "memory")
-
-void XIo_Out32(u32 OutAddress, u32 Value)
-{
-    *(volatile u32 *) OutAddress = Value;
-    dmbp();
-}
-
-u32 XIo_In32(u32 InAddress)
-{
-    volatile u32 temp = *(volatile u32 *)InAddress;
-    dmbp();
-    return temp;
-}
-
 #ifdef CONFIG_FPGA
 Xilinx_desc fpga = XILINX_XC7Z020_DESC(0);
 #endif
@@ -61,16 +46,16 @@ int board_init(void)
 	/* temporary hack to clear pending irqs before Linux as it
 	   will hang Linux */
 
-	XIo_Out32(0xe0001014, 0x26d);
+	writel(0x26d, 0xe0001014);
 
 	/* temporary hack to take USB out of reset til the is fixed
 	   in Linux */
 
-	XIo_Out32(0xe000a204, 0x80);
-	XIo_Out32(0xe000a208, 0x80);
-	XIo_Out32(0xe000a040, 0x80);
-	XIo_Out32(0xe000a040, 0x00);
-	XIo_Out32(0xe000a040, 0x80);
+	writel(0x80, 0xe000a204);
+	writel(0x80, 0xe000a208);
+	writel(0x80, 0xe000a040);
+	writel(0x00, 0xe000a040);
+	writel(0x80, 0xe000a040);
 
 	icache_enable();
 
@@ -84,10 +69,7 @@ int board_init(void)
 
 int board_late_init (void)
 {
-	u32 boot_mode;
-
-	boot_mode = (XIo_In32(BOOT_MODE_REG) & BOOT_MODES_MASK);
-	switch(boot_mode) {
+	switch ((zynq_slcr_get_boot_mode()) & BOOT_MODES_MASK) {
 	case QSPI_MODE:
 		setenv("modeboot", "qspiboot");
 		break;