From: Miquel Raynal (Schneider Electric) Date: Thu, 5 Feb 2026 18:09:51 +0000 (+0100) Subject: ARM: dts: renesas: r9a06g032: Describe the QSPI controller X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=5be0b48a3b23d961891db72a85092fe185106177;p=thirdparty%2Fkernel%2Flinux.git ARM: dts: renesas: r9a06g032: Describe the QSPI controller Add a node describing the QSPI controller. There are 2 clocks feeding this controller: - one for the reference clock - one that feeds both the ahb and the apb interfaces As the binding expect either the ref clock, or all three (ref, ahb and apb) clocks, it makes sense to provide the same clock twice. Reviewed-by: Geert Uytterhoeven Tested-by: Wolfram Sang Signed-off-by: Miquel Raynal (Schneider Electric) Link: https://patch.msgid.link/20260205-schneider-6-19-rc1-qspi-v5-4-843632b3c674@bootlin.com Signed-off-by: Geert Uytterhoeven --- diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index 0c6d6d8343954..daa7d5de575de 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -101,6 +101,18 @@ #size-cells = <1>; ranges; + qspi0: spi@40005000 { + compatible = "renesas,r9a06g032-qspi", "renesas,rzn1-qspi"; + reg = <0x40005000 0x1000>, <0x10000000 0x10000000>; + interrupts = ; + clocks = <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSPI0>, + <&sysctrl R9A06G032_HCLK_QSPI0>; + clock-names = "ref", "ahb", "apb"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + rtc0: rtc@40006000 { compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; reg = <0x40006000 0x1000>;