From: Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
Date: Sun, 26 Oct 2025 21:32:09 +0000 (+0900)
Subject: xtensa: Revert "xtensa: Make one_cmplsi2 optimizer-friendly"
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=5c1f506d4515864bd38f95f82dff624318327788;p=thirdparty%2Fgcc.git

xtensa: Revert "xtensa: Make one_cmplsi2 optimizer-friendly"

This patch effectively revert the past commit 9777d446e2148ef9a6e9f35db3f4eab99ee8812c.

Almost the only reason we committed that was because some optimizers in the
RTL ifcvt pass needed '(set (reg) (not (reg)))' RTX, however, in recent
versions of gcc, the equivalent optimizations are performed before RTL
passes, so the need for that commit has all but disappeared.

     /* example 1 */
     int test0(int a) {
       return a < 0 ? ~a : a;
     }

     ;; result 1
     test0:
     	entry	sp, 32
     	srai	a8, a2, 31	;; If-conversion before RTL expansion
     	xor	a2, a8, a2
     	retw.n

Instead, expanding it to an XOR with a pseudo whose value of -1 early in
the RTL passes will take advantage of CSE, forward propagation, or loop-
invariant hoisting.

     /* example 2 */
     long long test1(long long a) {
       return ~a;
     }
     void test2(int a[]) {
       int i;
       for (i = 0; i < 16; ++i)
         a[i] = ~a[i];
     }

     ;; result 2
     test1:
     	entry	sp, 32
     	movi.n	a8, -1		;; consolidated by CSE
     	xor	a2, a2, a8
     	xor	a3, a3, a8
     	retw.n
     test2:
     	entry	sp, 32
     	movi.n	a10, -1		;; hoisted out
     	movi.n	a9, 0x10
     	loop	a9, .L5_LEND
     .L5:
     	l32i.n	a8, a2, 0
     	xor	a8, a8, a10
     	s32i.n	a8, a2, 0
     	addi.n	a2, a2, 4
     	.L5_LEND:
     	retw.n

Another concern with reverting that commit is the impact on complex insns
that have '(not)' as part of them, but also nothing to worry about; because
the RTL insn combiner can correctly recognize an XOR with a register value
of -1 as a one's complement operation even without such RTX, and apply the
result to subsequent combine operations.

gcc/ChangeLog:

	* config/xtensa/xtensa.md (one_cmplsi2):
	Rearrange back as an expand pattern.

gcc/testsuite/ChangeLog:

	* gcc.target/xtensa/one_cmpl_abs.c: Remove.
---

diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 374288df708..4ba7f54c940 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -680,26 +680,15 @@
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
 
-(define_insn_and_split "one_cmplsi2"
-  [(set (match_operand:SI 0 "register_operand" "=a")
-	(not:SI (match_operand:SI 1 "register_operand" "r")))]
+(define_expand "one_cmplsi2"
+  [(set (match_operand:SI 0 "register_operand")
+	(not:SI (match_operand:SI 1 "register_operand")))]
   ""
-  "#"
-  "&& can_create_pseudo_p ()"
-  [(set (match_dup 2)
-	(const_int -1))
-   (set (match_dup 0)
-	(xor:SI (match_dup 1)
-		(match_dup 2)))]
 {
-  operands[2] = gen_reg_rtx (SImode);
-}
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set (attr "length")
-	(if_then_else (match_test "TARGET_DENSITY")
-		      (const_int 5)
-		      (const_int 6)))])
+  emit_insn (gen_xorsi3 (operands[0], operands[1],
+			 force_reg (SImode, constm1_rtx)));
+  DONE;
+})
 
 (define_insn "negsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
diff --git a/gcc/testsuite/gcc.target/xtensa/one_cmpl_abs.c b/gcc/testsuite/gcc.target/xtensa/one_cmpl_abs.c
deleted file mode 100644
index 608f65fd777..00000000000
--- a/gcc/testsuite/gcc.target/xtensa/one_cmpl_abs.c
+++ /dev/null
@@ -1,9 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O1" } */
-
-int one_cmpl_abs(int a)
-{
-  return a < 0 ? ~a : a;
-}
-
-/* { dg-final { scan-assembler-not "bgez" } } */