From: Sasha Levin Date: Mon, 12 May 2025 11:15:17 +0000 (-0400) Subject: Fixes for 6.1 X-Git-Tag: v5.15.183~28 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=5c75ee5218c1a704c145aee579996141744e7962;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 6.1 Signed-off-by: Sasha Levin --- diff --git a/queue-6.1/do_umount-add-missing-barrier-before-refcount-checks.patch b/queue-6.1/do_umount-add-missing-barrier-before-refcount-checks.patch new file mode 100644 index 0000000000..c2504fae5e --- /dev/null +++ b/queue-6.1/do_umount-add-missing-barrier-before-refcount-checks.patch @@ -0,0 +1,50 @@ +From 42f12bf5d8e1fa9f237d8ff2cdb77da26a13cd3d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 28 Apr 2025 23:56:14 -0400 +Subject: do_umount(): add missing barrier before refcount checks in sync case + +From: Al Viro + +[ Upstream commit 65781e19dcfcb4aed1167d87a3ffcc2a0c071d47 ] + +do_umount() analogue of the race fixed in 119e1ef80ecf "fix +__legitimize_mnt()/mntput() race". Here we want to make sure that +if __legitimize_mnt() doesn't notice our lock_mount_hash(), we will +notice their refcount increment. Harder to hit than mntput_no_expire() +one, fortunately, and consequences are milder (sync umount acting +like umount -l on a rare race with RCU pathwalk hitting at just the +wrong time instead of use-after-free galore mntput_no_expire() +counterpart used to be hit). Still a bug... + +Fixes: 48a066e72d97 ("RCU'd vfsmounts") +Reviewed-by: Christian Brauner +Signed-off-by: Al Viro +Signed-off-by: Sasha Levin +--- + fs/namespace.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/fs/namespace.c b/fs/namespace.c +index 57166cc7e5117..0dcd57a75ad49 100644 +--- a/fs/namespace.c ++++ b/fs/namespace.c +@@ -629,7 +629,7 @@ int __legitimize_mnt(struct vfsmount *bastard, unsigned seq) + return 0; + mnt = real_mount(bastard); + mnt_add_count(mnt, 1); +- smp_mb(); // see mntput_no_expire() ++ smp_mb(); // see mntput_no_expire() and do_umount() + if (likely(!read_seqretry(&mount_lock, seq))) + return 0; + if (bastard->mnt_flags & MNT_SYNC_UMOUNT) { +@@ -1707,6 +1707,7 @@ static int do_umount(struct mount *mnt, int flags) + umount_tree(mnt, UMOUNT_PROPAGATE); + retval = 0; + } else { ++ smp_mb(); // paired with __legitimize_mnt() + shrink_submounts(mnt); + retval = -EBUSY; + if (!propagate_mount_busy(mnt, 2)) { +-- +2.39.5 + diff --git a/queue-6.1/drm-panel-simple-update-timings-for-auo-g101evn010.patch b/queue-6.1/drm-panel-simple-update-timings-for-auo-g101evn010.patch new file mode 100644 index 0000000000..cd8fd106eb --- /dev/null +++ b/queue-6.1/drm-panel-simple-update-timings-for-auo-g101evn010.patch @@ -0,0 +1,73 @@ +From c93e3cc4b410efaa0cae569ac81b5f53fcae9393 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 5 May 2025 12:02:56 -0500 +Subject: drm/panel: simple: Update timings for AUO G101EVN010 + +From: Kevin Baker + +[ Upstream commit 7c6fa1797a725732981f2d77711c867166737719 ] + +Switch to panel timings based on datasheet for the AUO G101EVN01.0 +LVDS panel. Default timings were tested on the panel. + +Previous mode-based timings resulted in horizontal display shift. + +Signed-off-by: Kevin Baker +Fixes: 4fb86404a977 ("drm/panel: simple: Add AUO G101EVN010 panel support") +Reviewed-by: Neil Armstrong +Link: https://lore.kernel.org/r/20250505170256.1385113-1-kevinb@ventureresearch.com +Signed-off-by: Neil Armstrong +Link: https://lore.kernel.org/r/20250505170256.1385113-1-kevinb@ventureresearch.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/panel/panel-simple.c | 25 +++++++++++++------------ + 1 file changed, 13 insertions(+), 12 deletions(-) + +diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c +index a35e94e2ffd06..8a86f5d5c708d 100644 +--- a/drivers/gpu/drm/panel/panel-simple.c ++++ b/drivers/gpu/drm/panel/panel-simple.c +@@ -921,27 +921,28 @@ static const struct panel_desc auo_g070vvn01 = { + }, + }; + +-static const struct drm_display_mode auo_g101evn010_mode = { +- .clock = 68930, +- .hdisplay = 1280, +- .hsync_start = 1280 + 82, +- .hsync_end = 1280 + 82 + 2, +- .htotal = 1280 + 82 + 2 + 84, +- .vdisplay = 800, +- .vsync_start = 800 + 8, +- .vsync_end = 800 + 8 + 2, +- .vtotal = 800 + 8 + 2 + 6, ++static const struct display_timing auo_g101evn010_timing = { ++ .pixelclock = { 64000000, 68930000, 85000000 }, ++ .hactive = { 1280, 1280, 1280 }, ++ .hfront_porch = { 8, 64, 256 }, ++ .hback_porch = { 8, 64, 256 }, ++ .hsync_len = { 40, 168, 767 }, ++ .vactive = { 800, 800, 800 }, ++ .vfront_porch = { 4, 8, 100 }, ++ .vback_porch = { 4, 8, 100 }, ++ .vsync_len = { 8, 16, 223 }, + }; + + static const struct panel_desc auo_g101evn010 = { +- .modes = &auo_g101evn010_mode, +- .num_modes = 1, ++ .timings = &auo_g101evn010_timing, ++ .num_timings = 1, + .bpc = 6, + .size = { + .width = 216, + .height = 135, + }, + .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, ++ .bus_flags = DRM_BUS_FLAG_DE_HIGH, + .connector_type = DRM_MODE_CONNECTOR_LVDS, + }; + +-- +2.39.5 + diff --git a/queue-6.1/iio-accel-adxl355-make-timestamp-64-bit-aligned-usin.patch b/queue-6.1/iio-accel-adxl355-make-timestamp-64-bit-aligned-usin.patch new file mode 100644 index 0000000000..3567b67aa0 --- /dev/null +++ b/queue-6.1/iio-accel-adxl355-make-timestamp-64-bit-aligned-usin.patch @@ -0,0 +1,43 @@ +From 3118c881e301b4e32cf696d902e04df4dadc8f3c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 13 Apr 2025 11:34:27 +0100 +Subject: iio: accel: adxl355: Make timestamp 64-bit aligned using aligned_s64 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Jonathan Cameron + +[ Upstream commit 1bb942287e05dc4c304a003ea85e6dd9a5e7db39 ] + +The IIO ABI requires 64-bit aligned timestamps. In this case insufficient +padding would have been added on architectures where an s64 is only 32-bit +aligned. Use aligned_s64 to enforce the correct alignment. + +Fixes: 327a0eaf19d5 ("iio: accel: adxl355: Add triggered buffer support") +Reported-by: David Lechner +Reviewed-by: Nuno Sá +Reviewed-by: David Lechner +Link: https://patch.msgid.link/20250413103443.2420727-5-jic23@kernel.org +Signed-off-by: Jonathan Cameron +Signed-off-by: Sasha Levin +--- + drivers/iio/accel/adxl355_core.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/iio/accel/adxl355_core.c b/drivers/iio/accel/adxl355_core.c +index 4bc648eac8b29..e73573cd773a4 100644 +--- a/drivers/iio/accel/adxl355_core.c ++++ b/drivers/iio/accel/adxl355_core.c +@@ -175,7 +175,7 @@ struct adxl355_data { + u8 transf_buf[3]; + struct { + u8 buf[14]; +- s64 ts; ++ aligned_s64 ts; + } buffer; + } __aligned(IIO_DMA_MINALIGN); + }; +-- +2.39.5 + diff --git a/queue-6.1/iio-accel-adxl367-fix-setting-odr-for-activity-time-.patch b/queue-6.1/iio-accel-adxl367-fix-setting-odr-for-activity-time-.patch new file mode 100644 index 0000000000..63888535a7 --- /dev/null +++ b/queue-6.1/iio-accel-adxl367-fix-setting-odr-for-activity-time-.patch @@ -0,0 +1,68 @@ +From 51e91fbacbbed1da168a6a83ea3ed6ad74e8ab9c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 9 Mar 2025 19:35:15 +0000 +Subject: iio: accel: adxl367: fix setting odr for activity time update + +From: Lothar Rubusch + +[ Upstream commit 38f67d0264929762e54ae5948703a21f841fe706 ] + +Fix setting the odr value to update activity time based on frequency +derrived by recent odr, and not by obsolete odr value. + +The [small] bug: When _adxl367_set_odr() is called with a new odr value, +it first writes the new odr value to the hardware register +ADXL367_REG_FILTER_CTL. +Second, it calls _adxl367_set_act_time_ms(), which calls +adxl367_time_ms_to_samples(). Here st->odr still holds the old odr value. +This st->odr member is used to derrive a frequency value, which is +applied to update ADXL367_REG_TIME_ACT. Hence, the idea is to update +activity time, based on possibilities and power consumption by the +current ODR rate. +Finally, when the function calls return, again in _adxl367_set_odr() the +new ODR is assigned to st->odr. + +The fix: When setting a new ODR value is set to ADXL367_REG_FILTER_CTL, +also ADXL367_REG_TIME_ACT should probably be updated with a frequency +based on the recent ODR value and not the old one. Changing the location +of the assignment to st->odr fixes this. + +Fixes: cbab791c5e2a5 ("iio: accel: add ADXL367 driver") +Signed-off-by: Lothar Rubusch +Reviewed-by: Marcelo Schmitt +Link: https://patch.msgid.link/20250309193515.2974-1-l.rubusch@gmail.com +Signed-off-by: Jonathan Cameron +Signed-off-by: Sasha Levin +--- + drivers/iio/accel/adxl367.c | 10 +++------- + 1 file changed, 3 insertions(+), 7 deletions(-) + +diff --git a/drivers/iio/accel/adxl367.c b/drivers/iio/accel/adxl367.c +index f1a41b92543af..af0ad4e5e4a58 100644 +--- a/drivers/iio/accel/adxl367.c ++++ b/drivers/iio/accel/adxl367.c +@@ -622,18 +622,14 @@ static int _adxl367_set_odr(struct adxl367_state *st, enum adxl367_odr odr) + if (ret) + return ret; + ++ st->odr = odr; ++ + /* Activity timers depend on ODR */ + ret = _adxl367_set_act_time_ms(st, st->act_time_ms); + if (ret) + return ret; + +- ret = _adxl367_set_inact_time_ms(st, st->inact_time_ms); +- if (ret) +- return ret; +- +- st->odr = odr; +- +- return 0; ++ return _adxl367_set_inact_time_ms(st, st->inact_time_ms); + } + + static int adxl367_set_odr(struct iio_dev *indio_dev, enum adxl367_odr odr) +-- +2.39.5 + diff --git a/queue-6.1/iio-adc-dln2-use-aligned_s64-for-timestamp.patch b/queue-6.1/iio-adc-dln2-use-aligned_s64-for-timestamp.patch new file mode 100644 index 0000000000..dddd4933a4 --- /dev/null +++ b/queue-6.1/iio-adc-dln2-use-aligned_s64-for-timestamp.patch @@ -0,0 +1,45 @@ +From d53441cd4160b658927bb8aaaeda84b0b684189b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 13 Apr 2025 11:34:26 +0100 +Subject: iio: adc: dln2: Use aligned_s64 for timestamp +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Jonathan Cameron + +[ Upstream commit 5097eaae98e53f9ab9d35801c70da819b92ca907 ] + +Here the lack of marking allows the overall structure to not be +sufficiently aligned resulting in misplacement of the timestamp +in iio_push_to_buffers_with_timestamp(). Use aligned_s64 to +force the alignment on all architectures. + +Fixes: 7c0299e879dd ("iio: adc: Add support for DLN2 ADC") +Reported-by: David Lechner +Reviewed-by: Andy Shevchenko +Reviewed-by: Nuno Sá +Reviewed-by: David Lechner +Link: https://patch.msgid.link/20250413103443.2420727-4-jic23@kernel.org +Signed-off-by: Jonathan Cameron +Signed-off-by: Sasha Levin +--- + drivers/iio/adc/dln2-adc.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/iio/adc/dln2-adc.c b/drivers/iio/adc/dln2-adc.c +index 97d162a3cba4e..49a2588e7431e 100644 +--- a/drivers/iio/adc/dln2-adc.c ++++ b/drivers/iio/adc/dln2-adc.c +@@ -483,7 +483,7 @@ static irqreturn_t dln2_adc_trigger_h(int irq, void *p) + struct iio_dev *indio_dev = pf->indio_dev; + struct { + __le16 values[DLN2_ADC_MAX_CHANNELS]; +- int64_t timestamp_space; ++ aligned_s64 timestamp_space; + } data; + struct dln2_adc_get_all_vals dev_data; + struct dln2_adc *dln2 = iio_priv(indio_dev); +-- +2.39.5 + diff --git a/queue-6.1/iio-temp-maxim-thermocouple-fix-potential-lack-of-dm.patch b/queue-6.1/iio-temp-maxim-thermocouple-fix-potential-lack-of-dm.patch new file mode 100644 index 0000000000..728ba5ea67 --- /dev/null +++ b/queue-6.1/iio-temp-maxim-thermocouple-fix-potential-lack-of-dm.patch @@ -0,0 +1,42 @@ +From 87cd9567cfab1fa484adec835d37bb4be7544f57 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 13 Apr 2025 11:34:36 +0100 +Subject: iio: temp: maxim-thermocouple: Fix potential lack of DMA safe buffer. + +From: Jonathan Cameron + +[ Upstream commit f79aeb6c631b57395f37acbfbe59727e355a714c ] + +The trick of using __aligned(IIO_DMA_MINALIGN) ensures that there is +no overlap between buffers used for DMA and those used for driver +state storage that are before the marking. It doesn't ensure +anything above state variables found after the marking. Hence +move this particular bit of state earlier in the structure. + +Fixes: 10897f34309b ("iio: temp: maxim_thermocouple: Fix alignment for DMA safety") +Reviewed-by: David Lechner +Link: https://patch.msgid.link/20250413103443.2420727-14-jic23@kernel.org +Signed-off-by: Jonathan Cameron +Signed-off-by: Sasha Levin +--- + drivers/iio/temperature/maxim_thermocouple.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/iio/temperature/maxim_thermocouple.c b/drivers/iio/temperature/maxim_thermocouple.c +index c28a7a6dea5f1..555a61e2f3fdd 100644 +--- a/drivers/iio/temperature/maxim_thermocouple.c ++++ b/drivers/iio/temperature/maxim_thermocouple.c +@@ -121,9 +121,9 @@ static const struct maxim_thermocouple_chip maxim_thermocouple_chips[] = { + struct maxim_thermocouple_data { + struct spi_device *spi; + const struct maxim_thermocouple_chip *chip; ++ char tc_type; + + u8 buffer[16] __aligned(IIO_DMA_MINALIGN); +- char tc_type; + }; + + static int maxim_thermocouple_read(struct maxim_thermocouple_data *data, +-- +2.39.5 + diff --git a/queue-6.1/mips-fix-max_reg_offset.patch b/queue-6.1/mips-fix-max_reg_offset.patch new file mode 100644 index 0000000000..3d8bb927f9 --- /dev/null +++ b/queue-6.1/mips-fix-max_reg_offset.patch @@ -0,0 +1,39 @@ +From 7b0381df29dcdd5b8e9caab70a66e9135025dc01 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 27 Apr 2025 13:34:24 +0200 +Subject: MIPS: Fix MAX_REG_OFFSET + +From: Thorsten Blum + +[ Upstream commit c44572e0cc13c9afff83fd333135a0aa9b27ba26 ] + +Fix MAX_REG_OFFSET to point to the last register in 'pt_regs' and not to +the marker itself, which could allow regs_get_register() to return an +invalid offset. + +Fixes: 40e084a506eb ("MIPS: Add uprobes support.") +Suggested-by: Maciej W. Rozycki +Signed-off-by: Thorsten Blum +Signed-off-by: Thomas Bogendoerfer +Signed-off-by: Sasha Levin +--- + arch/mips/include/asm/ptrace.h | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h +index 4a2b40ce39e09..841612913f0d1 100644 +--- a/arch/mips/include/asm/ptrace.h ++++ b/arch/mips/include/asm/ptrace.h +@@ -65,7 +65,8 @@ static inline void instruction_pointer_set(struct pt_regs *regs, + + /* Query offset/name of register from its name/offset */ + extern int regs_query_register_offset(const char *name); +-#define MAX_REG_OFFSET (offsetof(struct pt_regs, __last)) ++#define MAX_REG_OFFSET \ ++ (offsetof(struct pt_regs, __last) - sizeof(unsigned long)) + + /** + * regs_get_register() - get register value from its offset +-- +2.39.5 + diff --git a/queue-6.1/nvme-unblock-ctrl-state-transition-for-firmware-upda.patch b/queue-6.1/nvme-unblock-ctrl-state-transition-for-firmware-upda.patch new file mode 100644 index 0000000000..88fcb7ed2b --- /dev/null +++ b/queue-6.1/nvme-unblock-ctrl-state-transition-for-firmware-upda.patch @@ -0,0 +1,53 @@ +From 99b5c3d9ecb41a3f66d90cb33daef3e096ccf359 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 2 May 2025 10:58:00 +0200 +Subject: nvme: unblock ctrl state transition for firmware update + +From: Daniel Wagner + +[ Upstream commit 650415fca0a97472fdd79725e35152614d1aad76 ] + +The original nvme subsystem design didn't have a CONNECTING state; the +state machine allowed transitions from RESETTING to LIVE directly. + +With the introduction of nvme fabrics the CONNECTING state was +introduce. Over time the nvme-pci started to use the CONNECTING state as +well. + +Eventually, a bug fix for the nvme-fc started to depend that the only +valid transition to LIVE was from CONNECTING. Though this change didn't +update the firmware update handler which was still depending on +RESETTING to LIVE transition. + +The simplest way to address it for the time being is to switch into +CONNECTING state before going to LIVE state. + +Fixes: d2fe192348f9 ("nvme: only allow entering LIVE from CONNECTING state") +Reported-by: Guenter Roeck +Signed-off-by: Daniel Wagner +Closes: https://lore.kernel.org/all/0134ea15-8d5f-41f7-9e9a-d7e6d82accaa@roeck-us.net +Reviewed-by: Keith Busch +Reviewed-by: Sagi Grimberg +Reviewed-by: Guenter Roeck +Signed-off-by: Sasha Levin +--- + drivers/nvme/host/core.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c +index 4c40ebb9503d3..fbe3fb4fbe95f 100644 +--- a/drivers/nvme/host/core.c ++++ b/drivers/nvme/host/core.c +@@ -4881,7 +4881,8 @@ static void nvme_fw_act_work(struct work_struct *work) + msleep(100); + } + +- if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_LIVE)) ++ if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_CONNECTING) || ++ !nvme_change_ctrl_state(ctrl, NVME_CTRL_LIVE)) + return; + + nvme_start_queues(ctrl); +-- +2.39.5 + diff --git a/queue-6.1/series b/queue-6.1/series index 8ba93e41ce..3c0e867555 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -57,3 +57,12 @@ usb-usbtmc-use-interruptible-sleep-in-usbtmc_read.patch usb-usbtmc-fix-erroneous-get_stb-ioctl-error-returns.patch usb-usbtmc-fix-erroneous-wait_srq-ioctl-return.patch usb-usbtmc-fix-erroneous-generic_read-ioctl-return.patch +iio-accel-adxl367-fix-setting-odr-for-activity-time-.patch +iio-temp-maxim-thermocouple-fix-potential-lack-of-dm.patch +types-complement-the-aligned-types-with-signed-64-bi.patch +iio-accel-adxl355-make-timestamp-64-bit-aligned-usin.patch +iio-adc-dln2-use-aligned_s64-for-timestamp.patch +mips-fix-max_reg_offset.patch +drm-panel-simple-update-timings-for-auo-g101evn010.patch +nvme-unblock-ctrl-state-transition-for-firmware-upda.patch +do_umount-add-missing-barrier-before-refcount-checks.patch diff --git a/queue-6.1/types-complement-the-aligned-types-with-signed-64-bi.patch b/queue-6.1/types-complement-the-aligned-types-with-signed-64-bi.patch new file mode 100644 index 0000000000..7582a1fa25 --- /dev/null +++ b/queue-6.1/types-complement-the-aligned-types-with-signed-64-bi.patch @@ -0,0 +1,52 @@ +From 77a0db8f5c7572c52f9f1957cec629d54cb4fc19 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 3 Sep 2024 20:59:04 +0300 +Subject: types: Complement the aligned types with signed 64-bit one + +From: Andy Shevchenko + +[ Upstream commit e4ca0e59c39442546866f3dd514a3a5956577daf ] + +Some user may want to use aligned signed 64-bit type. +Provide it for them. + +Signed-off-by: Andy Shevchenko +Link: https://patch.msgid.link/20240903180218.3640501-2-andriy.shevchenko@linux.intel.com +Signed-off-by: Jonathan Cameron +Stable-dep-of: 1bb942287e05 ("iio: accel: adxl355: Make timestamp 64-bit aligned using aligned_s64") +Signed-off-by: Sasha Levin +--- + include/linux/types.h | 3 ++- + include/uapi/linux/types.h | 1 + + 2 files changed, 3 insertions(+), 1 deletion(-) + +diff --git a/include/linux/types.h b/include/linux/types.h +index ea8cf60a8a795..f1df5d8df2ef9 100644 +--- a/include/linux/types.h ++++ b/include/linux/types.h +@@ -109,8 +109,9 @@ typedef u64 u_int64_t; + typedef s64 int64_t; + #endif + +-/* this is a special 64bit data type that is 8-byte aligned */ ++/* These are the special 64-bit data types that are 8-byte aligned */ + #define aligned_u64 __aligned_u64 ++#define aligned_s64 __aligned_s64 + #define aligned_be64 __aligned_be64 + #define aligned_le64 __aligned_le64 + +diff --git a/include/uapi/linux/types.h b/include/uapi/linux/types.h +index 308433be33c26..c39147653094f 100644 +--- a/include/uapi/linux/types.h ++++ b/include/uapi/linux/types.h +@@ -49,6 +49,7 @@ typedef __u32 __bitwise __wsum; + * No conversions are necessary between 32-bit user-space and a 64-bit kernel. + */ + #define __aligned_u64 __u64 __attribute__((aligned(8))) ++#define __aligned_s64 __s64 __attribute__((aligned(8))) + #define __aligned_be64 __be64 __attribute__((aligned(8))) + #define __aligned_le64 __le64 __attribute__((aligned(8))) + +-- +2.39.5 +