From: uros Date: Sun, 26 Jun 2016 20:56:34 +0000 (+0000) Subject: PR target/70902 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=5d7a493a558f249ecec72abd73cb1fd4d007e027;p=thirdparty%2Fgcc.git PR target/70902 PR target/71453 PR target/71555 PR target/71596 PR target/71657 * config/i386/i386.c (TARGET_SPILL_CLASS): #if 0 out the definition. (ix86_spill_class): Disable to always return NO_REGS. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@237792 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e153a890e1db..70b771999a33 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2016-06-26 Uros Bizjak + + PR target/70902 + PR target/71453 + PR target/71555 + PR target/71596 + PR target/71657 + * config/i386/i386.c (TARGET_SPILL_CLASS): #if 0 out the definition. + (ix86_spill_class): Disable to always return NO_REGS. + 2016-06-26 Jan Hubicka * predict.c: Include gimple-pretty-print.h diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index f7944f994ebc..c9595fa308d1 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -54583,10 +54583,13 @@ ix86_get_mask_mode (unsigned nunits, unsigned vector_size) /* Return class of registers which could be used for pseudo of MODE and of class RCLASS for spilling instead of memory. Return NO_REGS if it is not possible or non-profitable. */ + +/* Disabled due to PRs 70902, 71453, 71555, 71596 and 71657. */ + static reg_class_t ix86_spill_class (reg_class_t rclass, machine_mode mode) { - if (TARGET_GENERAL_REGS_SSE_SPILL + if (0 && TARGET_GENERAL_REGS_SSE_SPILL && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC && TARGET_INTER_UNIT_MOVES_FROM_VEC @@ -55700,8 +55703,11 @@ ix86_addr_space_zero_address_valid (addr_space_t as) #undef TARGET_LOOP_UNROLL_ADJUST #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust +#if 0 +/* Disabled due to PRs 70902, 71453, 71555, 71596 and 71657. */ #undef TARGET_SPILL_CLASS #define TARGET_SPILL_CLASS ix86_spill_class +#endif #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \