From: Yash Shinde <Yash.Shinde@windriver.com>
Date: Mon, 3 Feb 2025 09:15:19 +0000 (-0800)
Subject: qemuriscv: Enable Sv39 memory address scheme by default
X-Git-Tag: yocto-5.2~579
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=5e749a2576698e390392b5d522a2dc5fdc9556cd;p=thirdparty%2Fopenembedded%2Fopenembedded-core-contrib.git

qemuriscv: Enable Sv39 memory address scheme by default

Currently, GCC Asan supports only Sv39 on RISC-V 64 due to custom allocator configurations optimized for large allocations.
These configurations are incompatible with larger address spaces like Sv48/Sv57.
This fix enables RISC-V 64 configuration for RVA22S64 profile(which has sv39 mode and other extensions) by default when running `runqemu nographic`,
eliminating the need for manual configuration via command line flags (`qemuparams="-cpu rv64, sv39=true"`).

Fixes [YOCTO #15691]
https://bugzilla.yoctoproject.org/show_bug.cgi?id=15691

Reference:

https://github.com/qemu/qemu/commit/af651969eb23ecf018bcaa8e0761b58425de550c
https://git.openembedded.org/openembedded-core/commit/?id=4b4450ff695ef73bf7a2437e142d2e0730d6a547

Signed-off-by: Yash Shinde <Yash.Shinde@windriver.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
---

diff --git a/meta/conf/machine/include/riscv/qemuriscv.inc b/meta/conf/machine/include/riscv/qemuriscv.inc
index d01d988eeee..65cbfd66ee4 100644
--- a/meta/conf/machine/include/riscv/qemuriscv.inc
+++ b/meta/conf/machine/include/riscv/qemuriscv.inc
@@ -27,6 +27,7 @@ UBOOT_ENTRYPOINT:riscv64 = "0x80200000"
 # qemuboot options
 QB_SMP ?= "-smp 4"
 QB_KERNEL_CMDLINE_APPEND = "earlycon=sbi"
+QB_CPU:riscv64 ?= "-cpu rva22s64"
 QB_MACHINE = "-machine virt"
 QB_DEFAULT_BIOS = "fw_jump.elf"
 QB_TAP_OPT = "-netdev tap,id=net0,ifname=@TAP@,script=no,downscript=no"