From: Klaus Rubenstein Date: Wed, 1 Apr 2026 06:59:53 +0000 (+0200) Subject: realtek: extract shared GS1900-48 dtsi X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=5eca03fa07c7ba21b2089240dfbfffbe3c54d53a;p=thirdparty%2Fopenwrt.git realtek: extract shared GS1900-48 dtsi Move the shared hardware description from rtl8393_zyxel_gs1900-48-a1.dts into a common rtl8393_zyxel_gs1900-48.dtsi include file. This allows other GS1900-48 variants to reuse the shared definitions. Signed-off-by: Klaus Rubenstein Tested-by: Sander Vanheule Signed-off-by: Sander Vanheule --- diff --git a/target/linux/realtek/dts/rtl8393_zyxel_gs1900-48-a1.dts b/target/linux/realtek/dts/rtl8393_zyxel_gs1900-48-a1.dts index 20f9328fe72..43449ed725b 100644 --- a/target/linux/realtek/dts/rtl8393_zyxel_gs1900-48-a1.dts +++ b/target/linux/realtek/dts/rtl8393_zyxel_gs1900-48-a1.dts @@ -1,391 +1,10 @@ -/dts-v1/; +// SPDX-License-Identifier: GPL-2.0-or-later -#include "rtl839x.dtsi" +/dts-v1/; -#include -#include -#include +#include "rtl8393_zyxel_gs1900-48.dtsi" / { compatible = "zyxel,gs1900-48-a1", "realtek,rtl8393-soc"; model = "Zyxel GS1900-48 A1"; - - aliases { - led-boot = &led_sys; - led-failsafe = &led_sys; - led-running = &led_sys; - led-upgrade = &led_sys; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_disable_sys_led>; - compatible = "gpio-leds"; - - led_sys: sys { - label = "green:sys"; - gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <100>; - }; - }; - - /* i2c of the left SFP cage: port 49 */ - i2c0: i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp0: sfp-p49 { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; - }; - - /* i2c of the right SFP cage: port 50 */ - i2c1: i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp1: sfp-p50 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; - }; -}; - -#define PORT_LED(lan, p, l) \ - led@p,l { \ - reg =

; \ - color = ; \ - function = LED_FUNCTION_LAN; \ - function-enumerator = ; \ - } - -&mdio_aux { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&port_led_offload>; - - port_leds: expander@0 { - compatible = "realtek,rtl8231"; - reg = <0>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&port_leds 0 0 37>; - - led_matrix: led-scan-single { - pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", - "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", - "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", - "gpio18", "gpio19"; - function = "led"; - }; - - led-controller { - compatible = "realtek,rtl8231-leds"; - #address-cells = <2>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&led_matrix>; - - realtek,led-scan-mode = "single-color"; - - // RJ45 ports - PORT_LED(1, 0, 0); - PORT_LED(2, 0, 1); - PORT_LED(3, 0, 2); - PORT_LED(4, 1, 0); - PORT_LED(5, 1, 1); - PORT_LED(6, 1, 2); - PORT_LED(7, 2, 0); - PORT_LED(8, 2, 1); - PORT_LED(9, 2, 2); - PORT_LED(10, 3, 0); - PORT_LED(11, 3, 1); - PORT_LED(12, 3, 2); - PORT_LED(13, 4, 0); - PORT_LED(14, 4, 1); - PORT_LED(15, 4, 2); - PORT_LED(16, 5, 0); - PORT_LED(17, 5, 1); - PORT_LED(18, 5, 2); - PORT_LED(19, 6, 0); - PORT_LED(20, 6, 1); - PORT_LED(21, 6, 2); - PORT_LED(22, 7, 0); - PORT_LED(23, 7, 1); - PORT_LED(24, 7, 2); - PORT_LED(25, 8, 0); - PORT_LED(26, 8, 1); - PORT_LED(27, 8, 2); - PORT_LED(28, 9, 0); - PORT_LED(29, 9, 1); - PORT_LED(30, 9, 2); - PORT_LED(31, 10, 0); - PORT_LED(32, 10, 1); - PORT_LED(33, 10, 2); - PORT_LED(34, 11, 0); - PORT_LED(35, 11, 1); - PORT_LED(36, 11, 2); - PORT_LED(37, 12, 0); - PORT_LED(38, 12, 1); - PORT_LED(39, 12, 2); - PORT_LED(40, 13, 0); - PORT_LED(41, 13, 1); - PORT_LED(42, 13, 2); - PORT_LED(43, 14, 0); - PORT_LED(44, 14, 1); - PORT_LED(45, 14, 2); - PORT_LED(46, 15, 0); - PORT_LED(47, 15, 1); - PORT_LED(48, 15, 2); - // SFP ports - PORT_LED(49, 16, 0); - PORT_LED(50, 16, 1); - }; - }; - - gpio1: expander@3 { - compatible = "realtek,rtl8231"; - reg = <3>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&gpio1 0 0 37>; - - led-controller { - compatible = "realtek,rtl8231-leds"; - status = "disabled"; - }; - }; -}; - -&spi0 { - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x40000>; - read-only; - }; - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x10000>; - }; - partition@50000 { - label = "u-boot-env2"; - reg = <0x50000 0x10000>; - }; - partition@60000 { - label = "jffs"; - reg = <0x60000 0x100000>; - }; - partition@160000 { - label = "jffs2"; - reg = <0x160000 0x100000>; - }; - partition@260000 { - label = "firmware"; - reg = <0x260000 0xda0000>; - compatible = "openwrt,uimage", "denx,uimage"; - openwrt,ih-magic = <0x83800000>; - }; - }; - }; -}; - -&mdio_bus0 { - /* External phy RTL8218B #1 */ - PHY_C22(0, 0) - PHY_C22(1, 1) - PHY_C22(2, 2) - PHY_C22(3, 3) - PHY_C22(4, 4) - PHY_C22(5, 5) - PHY_C22(6, 6) - PHY_C22(7, 7) - - /* External phy RTL8218B #2 */ - PHY_C22(8, 8) - PHY_C22(9, 9) - PHY_C22(10, 10) - PHY_C22(11, 11) - PHY_C22(12, 12) - PHY_C22(13, 13) - PHY_C22(14, 14) - PHY_C22(15, 15) - - /* External phy RTL8218B #3 */ - PHY_C22(16, 16) - PHY_C22(17, 17) - PHY_C22(18, 18) - PHY_C22(19, 19) - PHY_C22(20, 20) - PHY_C22(21, 21) - PHY_C22(22, 22) - PHY_C22(23, 23) - - /* External phy RTL8218B #4 */ - PHY_C22(24, 24) - PHY_C22(25, 25) - PHY_C22(26, 26) - PHY_C22(27, 27) - PHY_C22(28, 28) - PHY_C22(29, 29) - PHY_C22(30, 30) - PHY_C22(31, 31) - - /* External phy RTL8218B #5 */ - PHY_C22(32, 32) - PHY_C22(33, 33) - PHY_C22(34, 34) - PHY_C22(35, 35) - PHY_C22(36, 36) - PHY_C22(37, 37) - PHY_C22(38, 38) - PHY_C22(39, 39) - - /* External phy RTL8218B #6 */ - PHY_C22(40, 40) - PHY_C22(41, 41) - PHY_C22(42, 42) - PHY_C22(43, 43) - PHY_C22(44, 44) - PHY_C22(45, 45) - PHY_C22(46, 46) - PHY_C22(47, 47) -}; - -&switch0 { - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT_SDS(0, 1, 0, qsgmii) - SWITCH_PORT_SDS(1, 2, 0, qsgmii) - SWITCH_PORT_SDS(2, 3, 0, qsgmii) - SWITCH_PORT_SDS(3, 4, 0, qsgmii) - SWITCH_PORT_SDS(4, 5, 1, qsgmii) - SWITCH_PORT_SDS(5, 6, 1, qsgmii) - SWITCH_PORT_SDS(6, 7, 1, qsgmii) - SWITCH_PORT_SDS(7, 8, 1, qsgmii) - - SWITCH_PORT_SDS(8, 9, 2, qsgmii) - SWITCH_PORT_SDS(9, 10, 2, qsgmii) - SWITCH_PORT_SDS(10, 11, 2, qsgmii) - SWITCH_PORT_SDS(11, 12, 2, qsgmii) - SWITCH_PORT_SDS(12, 13, 3, qsgmii) - SWITCH_PORT_SDS(13, 14, 3, qsgmii) - SWITCH_PORT_SDS(14, 15, 3, qsgmii) - SWITCH_PORT_SDS(15, 16, 3, qsgmii) - - SWITCH_PORT_SDS(16, 17, 4, qsgmii) - SWITCH_PORT_SDS(17, 18, 4, qsgmii) - SWITCH_PORT_SDS(18, 19, 4, qsgmii) - SWITCH_PORT_SDS(19, 20, 4, qsgmii) - SWITCH_PORT_SDS(20, 21, 5, qsgmii) - SWITCH_PORT_SDS(21, 22, 5, qsgmii) - SWITCH_PORT_SDS(22, 23, 5, qsgmii) - SWITCH_PORT_SDS(23, 24, 5, qsgmii) - - SWITCH_PORT_SDS(24, 25, 6, qsgmii) - SWITCH_PORT_SDS(25, 26, 6, qsgmii) - SWITCH_PORT_SDS(26, 27, 6, qsgmii) - SWITCH_PORT_SDS(27, 28, 6, qsgmii) - SWITCH_PORT_SDS(28, 29, 7, qsgmii) - SWITCH_PORT_SDS(29, 30, 7, qsgmii) - SWITCH_PORT_SDS(30, 31, 7, qsgmii) - SWITCH_PORT_SDS(31, 32, 7, qsgmii) - - SWITCH_PORT_SDS(32, 33, 8, qsgmii) - SWITCH_PORT_SDS(33, 34, 8, qsgmii) - SWITCH_PORT_SDS(34, 35, 8, qsgmii) - SWITCH_PORT_SDS(35, 36, 8, qsgmii) - SWITCH_PORT_SDS(36, 37, 9, qsgmii) - SWITCH_PORT_SDS(37, 38, 9, qsgmii) - SWITCH_PORT_SDS(38, 39, 9, qsgmii) - SWITCH_PORT_SDS(39, 40, 9, qsgmii) - - SWITCH_PORT_SDS(40, 41, 10, qsgmii) - SWITCH_PORT_SDS(41, 42, 10, qsgmii) - SWITCH_PORT_SDS(42, 43, 10, qsgmii) - SWITCH_PORT_SDS(43, 44, 10, qsgmii) - SWITCH_PORT_SDS(44, 45, 11, qsgmii) - SWITCH_PORT_SDS(45, 46, 11, qsgmii) - SWITCH_PORT_SDS(46, 47, 11, qsgmii) - SWITCH_PORT_SDS(47, 48, 11, qsgmii) - - /* SFP cages */ - port@48 { - reg = <48>; - label = "lan49"; - pcs-handle = <&serdes12>; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sfp0>; - }; - - port@49 { - reg = <49>; - label = "lan50"; - pcs-handle = <&serdes13>; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sfp1>; - }; - - /* CPU-Port */ - port@52 { - ethernet = <ðernet0>; - reg = <52>; - phy-mode = "internal"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; }; diff --git a/target/linux/realtek/dts/rtl8393_zyxel_gs1900-48.dtsi b/target/linux/realtek/dts/rtl8393_zyxel_gs1900-48.dtsi new file mode 100644 index 00000000000..edbba5a4088 --- /dev/null +++ b/target/linux/realtek/dts/rtl8393_zyxel_gs1900-48.dtsi @@ -0,0 +1,388 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "rtl839x.dtsi" + +#include +#include +#include + +/ { + aliases { + led-boot = &led_sys; + led-failsafe = &led_sys; + led-running = &led_sys; + led-upgrade = &led_sys; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_disable_sys_led>; + compatible = "gpio-leds"; + + led_sys: sys { + label = "green:sys"; + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <20>; + + reset { + label = "reset"; + gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <100>; + }; + }; + + /* i2c of the left SFP cage: port 49 */ + i2c0: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp0: sfp-p49 { + compatible = "sff,sfp"; + i2c-bus = <&i2c0>; + los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; + }; + + /* i2c of the right SFP cage: port 50 */ + i2c1: i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp1: sfp-p50 { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; + }; +}; + +#define PORT_LED(lan, p, l) \ + led@p,l { \ + reg =

; \ + color = ; \ + function = LED_FUNCTION_LAN; \ + function-enumerator = ; \ + } + +&mdio_aux { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&port_led_offload>; + + port_leds: expander@0 { + compatible = "realtek,rtl8231"; + reg = <0>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&port_leds 0 0 37>; + + led_matrix: led-scan-single { + pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "led"; + }; + + led-controller { + compatible = "realtek,rtl8231-leds"; + #address-cells = <2>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&led_matrix>; + + realtek,led-scan-mode = "single-color"; + + // RJ45 ports + PORT_LED(1, 0, 0); + PORT_LED(2, 0, 1); + PORT_LED(3, 0, 2); + PORT_LED(4, 1, 0); + PORT_LED(5, 1, 1); + PORT_LED(6, 1, 2); + PORT_LED(7, 2, 0); + PORT_LED(8, 2, 1); + PORT_LED(9, 2, 2); + PORT_LED(10, 3, 0); + PORT_LED(11, 3, 1); + PORT_LED(12, 3, 2); + PORT_LED(13, 4, 0); + PORT_LED(14, 4, 1); + PORT_LED(15, 4, 2); + PORT_LED(16, 5, 0); + PORT_LED(17, 5, 1); + PORT_LED(18, 5, 2); + PORT_LED(19, 6, 0); + PORT_LED(20, 6, 1); + PORT_LED(21, 6, 2); + PORT_LED(22, 7, 0); + PORT_LED(23, 7, 1); + PORT_LED(24, 7, 2); + PORT_LED(25, 8, 0); + PORT_LED(26, 8, 1); + PORT_LED(27, 8, 2); + PORT_LED(28, 9, 0); + PORT_LED(29, 9, 1); + PORT_LED(30, 9, 2); + PORT_LED(31, 10, 0); + PORT_LED(32, 10, 1); + PORT_LED(33, 10, 2); + PORT_LED(34, 11, 0); + PORT_LED(35, 11, 1); + PORT_LED(36, 11, 2); + PORT_LED(37, 12, 0); + PORT_LED(38, 12, 1); + PORT_LED(39, 12, 2); + PORT_LED(40, 13, 0); + PORT_LED(41, 13, 1); + PORT_LED(42, 13, 2); + PORT_LED(43, 14, 0); + PORT_LED(44, 14, 1); + PORT_LED(45, 14, 2); + PORT_LED(46, 15, 0); + PORT_LED(47, 15, 1); + PORT_LED(48, 15, 2); + // SFP ports + PORT_LED(49, 16, 0); + PORT_LED(50, 16, 1); + }; + }; + + gpio1: expander@3 { + compatible = "realtek,rtl8231"; + reg = <3>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio1 0 0 37>; + + led-controller { + compatible = "realtek,rtl8231-leds"; + status = "disabled"; + }; + }; +}; + +&spi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x40000>; + read-only; + }; + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x10000>; + }; + partition@50000 { + label = "u-boot-env2"; + reg = <0x50000 0x10000>; + }; + partition@60000 { + label = "jffs"; + reg = <0x60000 0x100000>; + }; + partition@160000 { + label = "jffs2"; + reg = <0x160000 0x100000>; + }; + partition@260000 { + label = "firmware"; + reg = <0x260000 0xda0000>; + compatible = "openwrt,uimage", "denx,uimage"; + openwrt,ih-magic = <0x83800000>; + }; + }; + }; +}; + +&mdio_bus0 { + /* External phy RTL8218B #1 */ + PHY_C22(0, 0) + PHY_C22(1, 1) + PHY_C22(2, 2) + PHY_C22(3, 3) + PHY_C22(4, 4) + PHY_C22(5, 5) + PHY_C22(6, 6) + PHY_C22(7, 7) + + /* External phy RTL8218B #2 */ + PHY_C22(8, 8) + PHY_C22(9, 9) + PHY_C22(10, 10) + PHY_C22(11, 11) + PHY_C22(12, 12) + PHY_C22(13, 13) + PHY_C22(14, 14) + PHY_C22(15, 15) + + /* External phy RTL8218B #3 */ + PHY_C22(16, 16) + PHY_C22(17, 17) + PHY_C22(18, 18) + PHY_C22(19, 19) + PHY_C22(20, 20) + PHY_C22(21, 21) + PHY_C22(22, 22) + PHY_C22(23, 23) + + /* External phy RTL8218B #4 */ + PHY_C22(24, 24) + PHY_C22(25, 25) + PHY_C22(26, 26) + PHY_C22(27, 27) + PHY_C22(28, 28) + PHY_C22(29, 29) + PHY_C22(30, 30) + PHY_C22(31, 31) + + /* External phy RTL8218B #5 */ + PHY_C22(32, 32) + PHY_C22(33, 33) + PHY_C22(34, 34) + PHY_C22(35, 35) + PHY_C22(36, 36) + PHY_C22(37, 37) + PHY_C22(38, 38) + PHY_C22(39, 39) + + /* External phy RTL8218B #6 */ + PHY_C22(40, 40) + PHY_C22(41, 41) + PHY_C22(42, 42) + PHY_C22(43, 43) + PHY_C22(44, 44) + PHY_C22(45, 45) + PHY_C22(46, 46) + PHY_C22(47, 47) +}; + +&switch0 { + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + SWITCH_PORT_SDS(0, 1, 0, qsgmii) + SWITCH_PORT_SDS(1, 2, 0, qsgmii) + SWITCH_PORT_SDS(2, 3, 0, qsgmii) + SWITCH_PORT_SDS(3, 4, 0, qsgmii) + SWITCH_PORT_SDS(4, 5, 1, qsgmii) + SWITCH_PORT_SDS(5, 6, 1, qsgmii) + SWITCH_PORT_SDS(6, 7, 1, qsgmii) + SWITCH_PORT_SDS(7, 8, 1, qsgmii) + + SWITCH_PORT_SDS(8, 9, 2, qsgmii) + SWITCH_PORT_SDS(9, 10, 2, qsgmii) + SWITCH_PORT_SDS(10, 11, 2, qsgmii) + SWITCH_PORT_SDS(11, 12, 2, qsgmii) + SWITCH_PORT_SDS(12, 13, 3, qsgmii) + SWITCH_PORT_SDS(13, 14, 3, qsgmii) + SWITCH_PORT_SDS(14, 15, 3, qsgmii) + SWITCH_PORT_SDS(15, 16, 3, qsgmii) + + SWITCH_PORT_SDS(16, 17, 4, qsgmii) + SWITCH_PORT_SDS(17, 18, 4, qsgmii) + SWITCH_PORT_SDS(18, 19, 4, qsgmii) + SWITCH_PORT_SDS(19, 20, 4, qsgmii) + SWITCH_PORT_SDS(20, 21, 5, qsgmii) + SWITCH_PORT_SDS(21, 22, 5, qsgmii) + SWITCH_PORT_SDS(22, 23, 5, qsgmii) + SWITCH_PORT_SDS(23, 24, 5, qsgmii) + + SWITCH_PORT_SDS(24, 25, 6, qsgmii) + SWITCH_PORT_SDS(25, 26, 6, qsgmii) + SWITCH_PORT_SDS(26, 27, 6, qsgmii) + SWITCH_PORT_SDS(27, 28, 6, qsgmii) + SWITCH_PORT_SDS(28, 29, 7, qsgmii) + SWITCH_PORT_SDS(29, 30, 7, qsgmii) + SWITCH_PORT_SDS(30, 31, 7, qsgmii) + SWITCH_PORT_SDS(31, 32, 7, qsgmii) + + SWITCH_PORT_SDS(32, 33, 8, qsgmii) + SWITCH_PORT_SDS(33, 34, 8, qsgmii) + SWITCH_PORT_SDS(34, 35, 8, qsgmii) + SWITCH_PORT_SDS(35, 36, 8, qsgmii) + SWITCH_PORT_SDS(36, 37, 9, qsgmii) + SWITCH_PORT_SDS(37, 38, 9, qsgmii) + SWITCH_PORT_SDS(38, 39, 9, qsgmii) + SWITCH_PORT_SDS(39, 40, 9, qsgmii) + + SWITCH_PORT_SDS(40, 41, 10, qsgmii) + SWITCH_PORT_SDS(41, 42, 10, qsgmii) + SWITCH_PORT_SDS(42, 43, 10, qsgmii) + SWITCH_PORT_SDS(43, 44, 10, qsgmii) + SWITCH_PORT_SDS(44, 45, 11, qsgmii) + SWITCH_PORT_SDS(45, 46, 11, qsgmii) + SWITCH_PORT_SDS(46, 47, 11, qsgmii) + SWITCH_PORT_SDS(47, 48, 11, qsgmii) + + /* SFP cages */ + port@48 { + reg = <48>; + label = "lan49"; + pcs-handle = <&serdes12>; + phy-mode = "1000base-x"; + managed = "in-band-status"; + sfp = <&sfp0>; + }; + + port@49 { + reg = <49>; + label = "lan50"; + pcs-handle = <&serdes13>; + phy-mode = "1000base-x"; + managed = "in-band-status"; + sfp = <&sfp1>; + }; + + /* CPU-Port */ + port@52 { + ethernet = <ðernet0>; + reg = <52>; + phy-mode = "internal"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +};