From: Manikanta Maddireddy Date: Tue, 24 Mar 2026 08:08:54 +0000 (+0530) Subject: PCI: endpoint: Add reserved region type for MSI-X Table and PBA X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=5f352433ea39171e19fbb3a7e18d983510176854;p=thirdparty%2Fkernel%2Fstable.git PCI: endpoint: Add reserved region type for MSI-X Table and PBA Add PCI_EPC_BAR_RSVD_MSIX_TBL_RAM and PCI_EPC_BAR_RSVD_MSIX_PBA_RAM to enum pci_epc_bar_rsvd_region_type so that Endpoint controllers can describe hardware-owned MSI-X Table and PBA (Pending Bit Array) regions behind a BAR_RESERVED BAR. Signed-off-by: Manikanta Maddireddy Signed-off-by: Manivannan Sadhasivam Reviewed-by: Niklas Cassel Link: https://patch.msgid.link/20260324080857.916263-2-mmaddireddy@nvidia.com --- diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 334c2b7578d0..1eca1264815b 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -211,6 +211,8 @@ enum pci_epc_bar_type { /** * enum pci_epc_bar_rsvd_region_type - type of a fixed subregion behind a BAR * @PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO: Integrated DMA controller MMIO window + * @PCI_EPC_BAR_RSVD_MSIX_TBL_RAM: MSI-X table structure + * @PCI_EPC_BAR_RSVD_MSIX_PBA_RAM: MSI-X PBA structure * * BARs marked BAR_RESERVED are owned by the SoC/EPC hardware and must not be * reprogrammed by EPF drivers. Some of them still expose fixed subregions that @@ -218,6 +220,8 @@ enum pci_epc_bar_type { */ enum pci_epc_bar_rsvd_region_type { PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO = 0, + PCI_EPC_BAR_RSVD_MSIX_TBL_RAM, + PCI_EPC_BAR_RSVD_MSIX_PBA_RAM, }; /**