From: Andreas Krebbel Date: Thu, 20 Dec 2012 15:20:06 +0000 (+0000) Subject: re PR regression/55754 (FAIL: gcc.target/arm/unsigned-extend-2.c scan-assembler ands) X-Git-Tag: releases/gcc-4.8.0~1294 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=5ff3c4f398f344051ac0495ae9aecad7af83dd62;p=thirdparty%2Fgcc.git re PR regression/55754 (FAIL: gcc.target/arm/unsigned-extend-2.c scan-assembler ands) 2012-12-20 Andreas Krebbel PR target/55754 * config/arm/arm.c (arm_canonicalize_comparison): Remove op0_preserve_value check for zero_extend to and transformation. From-SVN: r194636 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ca9844f4b44d..5c51847eb153 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2012-12-20 Andreas Krebbel + + PR target/55754 + * config/arm/arm.c (arm_canonicalize_comparison): Remove + op0_preserve_value check for zero_extend to and transformation. + 2012-12-20 Teresa Johnson Jakub Jelinek diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index be4428b92068..4484bc92364f 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3619,8 +3619,7 @@ arm_canonicalize_comparison (int *code, rtx *op0, rtx *op1, /* If *op0 is (zero_extend:SI (subreg:QI (reg:SI) 0)) and comparing with const0_rtx, change it to (and:SI (reg:SI) (const_int 255)), to facilitate possible combining with a cmp into 'ands'. */ - if (!op0_preserve_value - && mode == SImode + if (mode == SImode && GET_CODE (*op0) == ZERO_EXTEND && GET_CODE (XEXP (*op0, 0)) == SUBREG && GET_MODE (XEXP (*op0, 0)) == QImode