From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 21 Jan 2014 12:30:43 +0000 (+0100)
Subject: Merge tag 'v2014.01' into xilinx/master-next
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=60513f2031793692e60e3b2fc1930243bb6bb991;p=thirdparty%2Fu-boot.git

Merge tag 'v2014.01' into xilinx/master-next

- Fix Makefiles new style
- Fix qspi driver because of subsystem changes in mainline
- Fix zynq configuration
- Enable new CONFIG_RSA
- Fix board boot selection

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

60513f2031793692e60e3b2fc1930243bb6bb991
diff --cc Makefile
index dc0417914e7,47a03e34e73..47a03e34e73
mode 100755,100644..100755
--- a/Makefile
+++ b/Makefile
diff --cc arch/arm/cpu/armv7/zynq/Makefile
index 242ca6bbc29,d382d49eb0f..49499e44670
--- a/arch/arm/cpu/armv7/zynq/Makefile
+++ b/arch/arm/cpu/armv7/zynq/Makefile
@@@ -8,35 -8,7 +8,9 @@@
  # SPDX-License-Identifier:	GPL-2.0+
  #
  
- include $(TOPDIR)/config.mk
- 
- LIB	= $(obj)lib$(SOC).o
- 
- COBJS-y	:= timer.o
- COBJS-y	+= cpu.o
- COBJS-y	+= ddrc.o
- COBJS-y	+= slcr.o
- COBJS-y	+= clk.o
- 
- SOBJS-y	+= lowlevel_init.o
- 
- COBJS	:= $(COBJS-y)
- 
- SOBJS	:= $(SOBJS-y)
- 
- SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
- OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
- 
- all:	$(obj).depend $(LIB)
- 
- $(LIB): $(OBJS)
- 	$(call cmd_link_o_target, $(OBJS))
- 
- #########################################################################
- 
- # defines $(obj).depend target
- include $(SRCTREE)/rules.mk
- 
- sinclude $(obj).depend
- 
- #########################################################################
+ obj-y	:= timer.o
+ obj-y	+= cpu.o
+ obj-y	+= ddrc.o
+ obj-y	+= slcr.o
++obj-y	+= clk.o
++obj-y	+= lowlevel_init.o
diff --cc arch/arm/cpu/armv7/zynq/timer.c
index aadc6586301,2be253c2c3d..174e5a18f67
--- a/arch/arm/cpu/armv7/zynq/timer.c
+++ b/arch/arm/cpu/armv7/zynq/timer.c
@@@ -110,8 -107,7 +110,7 @@@ void __udelay(unsigned long usec
  	if (usec == 0)
  		return;
  
- 	countticks = (u32)(((unsigned long long)gd->arch.timer_rate_hz * usec) /
- 								1000000);
 -	countticks = lldiv(TIMER_TICK_HZ * usec, 1000000);
++	countticks = lldiv(gd->arch.timer_rate_hz * usec, 1000000);
  
  	/* decrementing timer */
  	timeend = readl(&timer_base->counter) - countticks;
diff --cc arch/arm/include/asm/arch-zynq/hardware.h
index 6a7836c4d34,cd69677729c..f12617930ad
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@@ -21,19 -19,7 +21,19 @@@
  #define ZYNQ_I2C_BASEADDR1		0xE0005000
  #define ZYNQ_SPI_BASEADDR0		0xE0006000
  #define ZYNQ_SPI_BASEADDR1		0xE0007000
 +#define ZYNQ_QSPI_BASEADDR		0xE000D000
 +#define ZYNQ_SMC_BASEADDR		0xE000E000
 +#define ZYNQ_NAND_BASEADDR		0xE1000000
  #define ZYNQ_DDRC_BASEADDR		0xF8006000
 +#define ZYNQ_EFUSE_BASEADDR		0xF800D000
 +
 +/* Bootmode setting values */
- #define BOOT_MODES_MASK		0x0000000F
- #define QSPI_MODE		0x00000001
- #define NOR_FLASH_MODE		0x00000002
- #define NAND_FLASH_MODE		0x00000004
- #define SD_MODE			0x00000005
- #define JTAG_MODE		0x00000000
++#define ZYNQ_BM_MASK		0x0F
++#define ZYNQ_BM_QSPI		0x01
++#define ZYNQ_BM_NOR		0x02
++#define ZYNQ_BM_NAND		0x04
++#define ZYNQ_BM_SD		0x05
++#define ZYNQ_BM_JTAG		0x0
  
  /* Reflect slcr offsets */
  struct slcr_regs {
diff --cc board/xilinx/ppc440-generic/Makefile
index 10a6c3f23d9,0acd95d6e4e..eba71c75470
--- a/board/xilinx/ppc440-generic/Makefile
+++ b/board/xilinx/ppc440-generic/Makefile
@@@ -9,25 -9,5 +9,5 @@@
  # SPDX-License-Identifier:	GPL-2.0+
  #
  
- include $(TOPDIR)/config.mk
- 
- LIB	= $(obj)lib$(BOARD).o
- 
- COBJS	= ppc440-generic.o
- SOBJS   = init.o
- 
- SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
- OBJS	:= $(addprefix $(obj),$(COBJS))
- SOBJS	:= $(addprefix $(obj),$(SOBJS))
- 
- $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
- 	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
- 
- #########################################################################
- 
- # defines $(obj).depend target
- include $(SRCTREE)/rules.mk
- 
- sinclude $(obj).depend
- 
- #########################################################################
 -obj-y	+= ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o
 -extra-y 	+= ../../xilinx/ppc440-generic/init.o
++obj-y	+= ppc440-generic.o
++extra-y 	+= init.o
diff --cc board/xilinx/zynq/board.c
index 7fb71af641a,a5b9bdef46a..28d0ab01133
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@@ -64,20 -67,14 +64,20 @@@ int board_init(void
  
  int board_late_init(void)
  {
- 	switch ((zynq_slcr_get_boot_mode()) & BOOT_MODES_MASK) {
- 	case QSPI_MODE:
+ 	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
++	case ZYNQ_BM_QSPI:
 +		setenv("modeboot", "qspiboot");
 +		break;
- 	case NAND_FLASH_MODE:
++	case ZYNQ_BM_NAND:
 +		setenv("modeboot", "nandboot");
 +		break;
- 	case NOR_FLASH_MODE:
+ 	case ZYNQ_BM_NOR:
  		setenv("modeboot", "norboot");
  		break;
- 	case SD_MODE:
+ 	case ZYNQ_BM_SD:
  		setenv("modeboot", "sdboot");
  		break;
- 	case JTAG_MODE:
+ 	case ZYNQ_BM_JTAG:
  		setenv("modeboot", "jtagboot");
  		break;
  	default:
diff --cc boards.cfg
index 6766e9e2c51,a8336cc7a9a..bab89f27551
--- a/boards.cfg
+++ b/boards.cfg
@@@ -343,32 -356,17 +356,34 @@@ Active  arm         armv7          socf
  Active  arm         armv7          u8500       st-ericsson     snowball            snowball                             -                                                                                                                                 Mathieu Poirier <mathieu.poirier@linaro.org>
  Active  arm         armv7          u8500       st-ericsson     u8500               u8500_href                           -                                                                                                                                 -
  Active  arm         armv7          vf610       freescale       vf610twr            vf610twr                             vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg                                                                         Alison Wang <b18965@freescale.com>
- Active  arm         armv7          zynq        xilinx          zynq                zynq_zc770_XM010                     zynq_zc770:ZC770_XM010                                                                                                            Michal Simek <michal.simek@xilinx.com>
+ Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc70x				-                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+ Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zed				-                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+ Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_microzed			-                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
 -Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc770_xm010			zynq_zc770:ZC770_XM010                                                                                                            Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
 -Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc770_xm012			zynq_zc770:ZC770_XM012                                                                                                            Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
 -Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc770_xm013			zynq_zc770:ZC770_XM013                                                                                                            Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
++Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc770_XM010			zynq_zc770:ZC770_XM010                                                                                                            Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
++Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc770_XM012			zynq_zc770:ZC770_XM012                                                                                                            Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
++Active  arm	    armv7	   zynq	       xilinx	       zynq	   	   zynq_zc770_XM013			zynq_zc770:ZC770_XM013                                                                                                            Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
 +Active  arm         armv7          zynq        xilinx          zynq                zynq_zc770_XM011                     zynq_zc770:ZC770_XM011                                                                                                            Michal Simek <michal.simek@xilinx.com>
- Active  arm         armv7          zynq        xilinx          zynq                zynq_zc770_XM012                     zynq_zc770:ZC770_XM012                                                                                                            Michal Simek <michal.simek@xilinx.com>
- Active  arm         armv7          zynq        xilinx          zynq                zynq_zc770_XM013                     zynq_zc770:ZC770_XM013                                                                                                            Michal Simek <michal.simek@xilinx.com>
 +Active  arm         armv7          zynq        xilinx          zynq                zynq_afx_nor                         zynq_afx:AFX_NOR                                                                                                                  Michal Simek <michal.simek@xilinx.com>
 +Active  arm         armv7          zynq        xilinx          zynq                zynq_afx_qspi                        zynq_afx:AFX_QSPI                                                                                                                 Michal Simek <michal.simek@xilinx.com>
 +Active  arm         armv7          zynq        xilinx          zynq                zynq_afx_nand                        zynq_afx:AFX_NAND                                                                                                                 Michal Simek <michal.simek@xilinx.com>
- Active  arm         armv7          zynq        xilinx          zynq                zynq_zc70x                           -                                                                                                                                 Michal Simek <michal.simek@xilinx.com>
- Active  arm         armv7          zynq        xilinx          zynq                zynq_zed                             -                                                                                                                                 Michal Simek <michal.simek@xilinx.com>
 +Active  arm         armv7          zynq        xilinx          zynq                zynq_cse_nor                         zynq_cse:CSE_NOR                                                                                                                  Michal Simek <michal.simek@xilinx.com>
 +Active  arm         armv7          zynq        xilinx          zynq                zynq_cse_qspi                        zynq_cse:CSE_QSPI                                                                                                                 Michal Simek <michal.simek@xilinx.com>
 +Active  arm         armv7          zynq        xilinx          zynq                zynq_cse_nand                        zynq_cse:CSE_NAND                                                                                                                 Michal Simek <michal.simek@xilinx.com>
 +Active  arm         armv7          zynq        xilinx          zynq                zynq_cc108                           -                                                                                                                                 Michal Simek <michal.simek@xilinx.com>
 +Active  arm         armv7          zynq        xilinx          zynq                zynq_zc770_XM010_RSA                 zynq_zc770:ZC770_XM010,CMD_ZYNQ_RSA                                                                                                   Michal Simek <michal.simek@xilinx.com>
 +Active  arm         armv7          zynq        xilinx          zynq                zynq_zc770_XM011_RSA                 zynq_zc770:ZC770_XM011,CMD_ZYNQ_RSA                                                                                                   Michal Simek <michal.simek@xilinx.com>
 +Active  arm         armv7          zynq        xilinx          zynq                zynq_zc770_XM012_RSA                 zynq_zc770:ZC770_XM012,CMD_ZYNQ_RSA                                                                                                   Michal Simek <michal.simek@xilinx.com>
 +Active  arm         armv7          zynq        xilinx          zynq                zynq_zc770_XM013_RSA                 zynq_zc770:ZC770_XM013,CMD_ZYNQ_RSA                                                                                                   Michal Simek <michal.simek@xilinx.com>
 +Active  arm         armv7          zynq        xilinx          zynq                zynq_afx_nor_RSA                     zynq_afx:AFX_NOR,CMD_ZYNQ_RSA                                                                                                         Michal Simek <michal.simek@xilinx.com>
 +Active  arm         armv7          zynq        xilinx          zynq                zynq_afx_qspi_RSA                    zynq_afx:AFX_QSPI,CMD_ZYNQ_RSA                                                                                                        Michal Simek <michal.simek@xilinx.com>
 +Active  arm         armv7          zynq        xilinx          zynq                zynq_afx_nand_RSA                    zynq_afx:AFX_NAND,CMD_ZYNQ_RSA                                                                                                        Michal Simek <michal.simek@xilinx.com>
 +Active  arm         armv7          zynq        xilinx          zynq                zynq_zc70x_RSA                       zynq_zc70x:CMD_ZYNQ_RSA                                                                                                               Michal Simek <michal.simek@xilinx.com>
 +Active  arm         armv7          zynq        xilinx          zynq                zynq_zed_RSA                         zynq_zed:CMD_ZYNQ_RSA                                                                                                                 Michal Simek <michal.simek@xilinx.com>
  Active  arm         armv7:arm720t  tegra114    nvidia          dalmore             dalmore                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
- Active  arm         armv7:arm720t  tegra20     avionic-design  medcom-wide         medcom-wide                          -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
- Active  arm         armv7:arm720t  tegra20     avionic-design  plutux              plutux                               -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
- Active  arm         armv7:arm720t  tegra20     avionic-design  tec                 tec                                  -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
+ Active  arm         armv7:arm720t  tegra20     avionic-design  medcom-wide         medcom-wide                          -                                                                                                                                 Alban Bedel <alban.bedel@avionic-design.de>
+ Active  arm         armv7:arm720t  tegra20     avionic-design  plutux              plutux                               -                                                                                                                                 Alban Bedel <alban.bedel@avionic-design.de>
+ Active  arm         armv7:arm720t  tegra20     avionic-design  tec                 tec                                  -                                                                                                                                 Alban Bedel <alban.bedel@avionic-design.de>
+ Active  arm         armv7:arm720t  tegra30     avionic-design  tec-ng              tec-ng                               -                                                                                                                                 Alban Bedel <alban.bedel@avionic-design.de>
  Active  arm         armv7:arm720t  tegra20     compal          paz00               paz00                                -                                                                                                                                 Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
  Active  arm         armv7:arm720t  tegra20     compulab        trimslice           trimslice                            -                                                                                                                                 Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
  Active  arm         armv7:arm720t  tegra20     nvidia          harmony             harmony                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
diff --cc common/Makefile
index f1b4117fe18,d12cba5bf0d..780c697ab59
--- a/common/Makefile
+++ b/common/Makefile
@@@ -5,193 -5,188 +5,190 @@@
  # SPDX-License-Identifier:	GPL-2.0+
  #
  
- include $(TOPDIR)/config.mk
- 
- LIB	= $(obj)libcommon.o
- 
  # core
  ifndef CONFIG_SPL_BUILD
- COBJS-y += main.o
- COBJS-y += command.o
- COBJS-y += exports.o
- COBJS-y += hash.o
- COBJS-$(CONFIG_SYS_HUSH_PARSER) += hush.o
- COBJS-y += s_record.o
- COBJS-y += xyzModem.o
- COBJS-y += cmd_disk.o
+ obj-y += main.o
+ obj-y += command.o
+ obj-y += exports.o
+ obj-y += hash.o
+ obj-$(CONFIG_SYS_HUSH_PARSER) += hush.o
+ obj-y += s_record.o
+ obj-y += xyzModem.o
+ obj-y += cmd_disk.o
  
  # boards
- COBJS-$(CONFIG_SYS_GENERIC_BOARD) += board_f.o
- COBJS-$(CONFIG_SYS_GENERIC_BOARD) += board_r.o
+ obj-$(CONFIG_SYS_GENERIC_BOARD) += board_f.o
+ obj-$(CONFIG_SYS_GENERIC_BOARD) += board_r.o
  
  # core command
- COBJS-y += cmd_boot.o
- COBJS-$(CONFIG_CMD_BOOTM) += cmd_bootm.o
- COBJS-y += cmd_help.o
- COBJS-y += cmd_version.o
+ obj-y += cmd_boot.o
+ obj-$(CONFIG_CMD_BOOTM) += cmd_bootm.o
+ obj-y += cmd_help.o
+ obj-y += cmd_version.o
  
  # environment
- COBJS-y += env_attr.o
- COBJS-y += env_callback.o
- COBJS-y += env_flags.o
- COBJS-$(CONFIG_ENV_IS_IN_DATAFLASH) += env_dataflash.o
- COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += env_eeprom.o
- XCOBJS-$(CONFIG_ENV_IS_EMBEDDED) += env_embedded.o
- COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += env_embedded.o
- XCOBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_embedded.o
- COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_embedded.o
- COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
- COBJS-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
- COBJS-$(CONFIG_ENV_IS_IN_FAT) += env_fat.o
- COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
- COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o
- COBJS-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o
- COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
- COBJS-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o
- COBJS-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o
- COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
+ obj-y += env_attr.o
+ obj-y += env_callback.o
+ obj-y += env_flags.o
+ obj-$(CONFIG_ENV_IS_IN_DATAFLASH) += env_dataflash.o
+ obj-$(CONFIG_ENV_IS_IN_EEPROM) += env_eeprom.o
+ extra-$(CONFIG_ENV_IS_EMBEDDED) += env_embedded.o
+ obj-$(CONFIG_ENV_IS_IN_EEPROM) += env_embedded.o
+ extra-$(CONFIG_ENV_IS_IN_FLASH) += env_embedded.o
+ obj-$(CONFIG_ENV_IS_IN_NVRAM) += env_embedded.o
+ obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
+ obj-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
+ obj-$(CONFIG_ENV_IS_IN_FAT) += env_fat.o
+ obj-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
+ obj-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o
+ obj-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o
+ obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
+ obj-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o
+ obj-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o
+ obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
  
  # command
- COBJS-$(CONFIG_CMD_AMBAPP) += cmd_ambapp.o
- COBJS-$(CONFIG_SOURCE) += cmd_source.o
- COBJS-$(CONFIG_CMD_SOURCE) += cmd_source.o
- COBJS-$(CONFIG_CMD_BDI) += cmd_bdinfo.o
- COBJS-$(CONFIG_CMD_BEDBUG) += bedbug.o cmd_bedbug.o
- COBJS-$(CONFIG_CMD_BMP) += cmd_bmp.o
- COBJS-$(CONFIG_CMD_BOOTMENU) += cmd_bootmenu.o
- COBJS-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o
- COBJS-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o
- COBJS-$(CONFIG_CMD_CACHE) += cmd_cache.o
- COBJS-$(CONFIG_CMD_CBFS) += cmd_cbfs.o
- COBJS-$(CONFIG_CMD_CLK) += cmd_clk.o
- COBJS-$(CONFIG_CMD_CONSOLE) += cmd_console.o
- COBJS-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o
- COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o
- COBJS-$(CONFIG_CMD_DATE) += cmd_date.o
- COBJS-$(CONFIG_CMD_SOUND) += cmd_sound.o
+ obj-$(CONFIG_CMD_AMBAPP) += cmd_ambapp.o
+ obj-$(CONFIG_SOURCE) += cmd_source.o
+ obj-$(CONFIG_CMD_SOURCE) += cmd_source.o
+ obj-$(CONFIG_CMD_BDI) += cmd_bdinfo.o
+ obj-$(CONFIG_CMD_BEDBUG) += bedbug.o cmd_bedbug.o
+ obj-$(CONFIG_CMD_BMP) += cmd_bmp.o
+ obj-$(CONFIG_CMD_BOOTMENU) += cmd_bootmenu.o
+ obj-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o
+ obj-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o
+ obj-$(CONFIG_CMD_CACHE) += cmd_cache.o
+ obj-$(CONFIG_CMD_CBFS) += cmd_cbfs.o
++obj-$(CONFIG_CMD_CLK) += cmd_clk.o
+ obj-$(CONFIG_CMD_CONSOLE) += cmd_console.o
+ obj-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o
+ obj-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o
+ obj-$(CONFIG_CMD_DATE) += cmd_date.o
+ obj-$(CONFIG_CMD_SOUND) += cmd_sound.o
  ifdef CONFIG_4xx
- COBJS-$(CONFIG_CMD_SETGETDCR) += cmd_dcr.o
+ obj-$(CONFIG_CMD_SETGETDCR) += cmd_dcr.o
  endif
  ifdef CONFIG_POST
- COBJS-$(CONFIG_CMD_DIAG) += cmd_diag.o
+ obj-$(CONFIG_CMD_DIAG) += cmd_diag.o
  endif
- COBJS-$(CONFIG_CMD_DISPLAY) += cmd_display.o
- COBJS-$(CONFIG_CMD_DTT) += cmd_dtt.o
- COBJS-$(CONFIG_CMD_ECHO) += cmd_echo.o
- COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += cmd_eeprom.o
- COBJS-$(CONFIG_CMD_EEPROM) += cmd_eeprom.o
- COBJS-$(CONFIG_CMD_ELF) += cmd_elf.o
- COBJS-$(CONFIG_SYS_HUSH_PARSER) += cmd_exit.o
- COBJS-$(CONFIG_CMD_EXT4) += cmd_ext4.o
- COBJS-$(CONFIG_CMD_EXT2) += cmd_ext2.o
- COBJS-$(CONFIG_CMD_FAT) += cmd_fat.o
- COBJS-$(CONFIG_CMD_FDC)$(CONFIG_CMD_FDOS) += cmd_fdc.o
- COBJS-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o
- COBJS-$(CONFIG_CMD_FDOS) += cmd_fdos.o
- COBJS-$(CONFIG_CMD_FITUPD) += cmd_fitupd.o
- COBJS-$(CONFIG_CMD_FLASH) += cmd_flash.o
+ obj-$(CONFIG_CMD_DISPLAY) += cmd_display.o
+ obj-$(CONFIG_CMD_DTT) += cmd_dtt.o
+ obj-$(CONFIG_CMD_ECHO) += cmd_echo.o
+ obj-$(CONFIG_ENV_IS_IN_EEPROM) += cmd_eeprom.o
+ obj-$(CONFIG_CMD_EEPROM) += cmd_eeprom.o
+ obj-$(CONFIG_CMD_ELF) += cmd_elf.o
+ obj-$(CONFIG_SYS_HUSH_PARSER) += cmd_exit.o
+ obj-$(CONFIG_CMD_EXT4) += cmd_ext4.o
+ obj-$(CONFIG_CMD_EXT2) += cmd_ext2.o
+ obj-$(CONFIG_CMD_FAT) += cmd_fat.o
+ obj-$(CONFIG_CMD_FDC)$(CONFIG_CMD_FDOS) += cmd_fdc.o
+ obj-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o
+ obj-$(CONFIG_CMD_FDOS) += cmd_fdos.o
+ obj-$(CONFIG_CMD_FITUPD) += cmd_fitupd.o
+ obj-$(CONFIG_CMD_FLASH) += cmd_flash.o
  ifdef CONFIG_FPGA
- COBJS-$(CONFIG_CMD_FPGA) += cmd_fpga.o
+ obj-$(CONFIG_CMD_FPGA) += cmd_fpga.o
  endif
- COBJS-$(CONFIG_CMD_FPGAD) += cmd_fpgad.o
- COBJS-$(CONFIG_CMD_FS_GENERIC) += cmd_fs.o
- COBJS-$(CONFIG_CMD_FUSE) += cmd_fuse.o
- COBJS-$(CONFIG_CMD_GETTIME) += cmd_gettime.o
- COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o
- COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o
- COBJS-$(CONFIG_CMD_HASH) += cmd_hash.o
- COBJS-$(CONFIG_CMD_IDE) += cmd_ide.o
- COBJS-$(CONFIG_CMD_IMMAP) += cmd_immap.o
- COBJS-$(CONFIG_CMD_INI) += cmd_ini.o
- COBJS-$(CONFIG_CMD_IRQ) += cmd_irq.o
- COBJS-$(CONFIG_CMD_ITEST) += cmd_itest.o
- COBJS-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o
- COBJS-$(CONFIG_CMD_CRAMFS) += cmd_cramfs.o
- COBJS-$(CONFIG_CMD_LDRINFO) += cmd_ldrinfo.o
- COBJS-$(CONFIG_CMD_LED) += cmd_led.o
- COBJS-$(CONFIG_CMD_LICENSE) += cmd_license.o
- COBJS-y += cmd_load.o
- COBJS-$(CONFIG_LOGBUFFER) += cmd_log.o
- COBJS-$(CONFIG_ID_EEPROM) += cmd_mac.o
- COBJS-$(CONFIG_CMD_MD5SUM) += cmd_md5sum.o
- COBJS-$(CONFIG_CMD_MEMORY) += cmd_mem.o
- COBJS-$(CONFIG_CMD_IO) += cmd_io.o
- COBJS-$(CONFIG_CMD_MFSL) += cmd_mfsl.o
- COBJS-$(CONFIG_MII) += miiphyutil.o
- COBJS-$(CONFIG_CMD_MII) += miiphyutil.o
- COBJS-$(CONFIG_PHYLIB) += miiphyutil.o
- COBJS-$(CONFIG_CMD_MII) += cmd_mii.o
+ obj-$(CONFIG_CMD_FPGAD) += cmd_fpgad.o
+ obj-$(CONFIG_CMD_FS_GENERIC) += cmd_fs.o
+ obj-$(CONFIG_CMD_FUSE) += cmd_fuse.o
+ obj-$(CONFIG_CMD_GETTIME) += cmd_gettime.o
+ obj-$(CONFIG_CMD_GPIO) += cmd_gpio.o
+ obj-$(CONFIG_CMD_I2C) += cmd_i2c.o
+ obj-$(CONFIG_CMD_HASH) += cmd_hash.o
+ obj-$(CONFIG_CMD_IDE) += cmd_ide.o
+ obj-$(CONFIG_CMD_IMMAP) += cmd_immap.o
+ obj-$(CONFIG_CMD_INI) += cmd_ini.o
+ obj-$(CONFIG_CMD_IRQ) += cmd_irq.o
+ obj-$(CONFIG_CMD_ITEST) += cmd_itest.o
+ obj-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o
+ obj-$(CONFIG_CMD_CRAMFS) += cmd_cramfs.o
+ obj-$(CONFIG_CMD_LDRINFO) += cmd_ldrinfo.o
+ obj-$(CONFIG_CMD_LED) += cmd_led.o
+ obj-$(CONFIG_CMD_LICENSE) += cmd_license.o
+ obj-y += cmd_load.o
+ obj-$(CONFIG_LOGBUFFER) += cmd_log.o
+ obj-$(CONFIG_ID_EEPROM) += cmd_mac.o
+ obj-$(CONFIG_CMD_MD5SUM) += cmd_md5sum.o
+ obj-$(CONFIG_CMD_MEMORY) += cmd_mem.o
+ obj-$(CONFIG_CMD_IO) += cmd_io.o
+ obj-$(CONFIG_CMD_MFSL) += cmd_mfsl.o
+ obj-$(CONFIG_MII) += miiphyutil.o
+ obj-$(CONFIG_CMD_MII) += miiphyutil.o
+ obj-$(CONFIG_PHYLIB) += miiphyutil.o
+ obj-$(CONFIG_CMD_MII) += cmd_mii.o
  ifdef CONFIG_PHYLIB
- COBJS-$(CONFIG_CMD_MII) += cmd_mdio.o
+ obj-$(CONFIG_CMD_MII) += cmd_mdio.o
  endif
- COBJS-$(CONFIG_CMD_MISC) += cmd_misc.o
- COBJS-$(CONFIG_CMD_MMC) += cmd_mmc.o
- COBJS-$(CONFIG_CMD_MMC_SPI) += cmd_mmc_spi.o
- COBJS-$(CONFIG_MP) += cmd_mp.o
- COBJS-$(CONFIG_CMD_MTDPARTS) += cmd_mtdparts.o
- COBJS-$(CONFIG_CMD_NAND) += cmd_nand.o
- COBJS-$(CONFIG_CMD_NET) += cmd_net.o
- COBJS-$(CONFIG_CMD_ONENAND) += cmd_onenand.o
- COBJS-$(CONFIG_CMD_OTP) += cmd_otp.o
- COBJS-$(CONFIG_CMD_PART) += cmd_part.o
+ obj-$(CONFIG_CMD_MISC) += cmd_misc.o
+ obj-$(CONFIG_CMD_MMC) += cmd_mmc.o
+ obj-$(CONFIG_CMD_MMC_SPI) += cmd_mmc_spi.o
+ obj-$(CONFIG_MP) += cmd_mp.o
+ obj-$(CONFIG_CMD_MTDPARTS) += cmd_mtdparts.o
+ obj-$(CONFIG_CMD_NAND) += cmd_nand.o
+ obj-$(CONFIG_CMD_NET) += cmd_net.o
+ obj-$(CONFIG_CMD_ONENAND) += cmd_onenand.o
+ obj-$(CONFIG_CMD_OTP) += cmd_otp.o
+ obj-$(CONFIG_CMD_PART) += cmd_part.o
  ifdef CONFIG_PCI
- COBJS-$(CONFIG_CMD_PCI) += cmd_pci.o
+ obj-$(CONFIG_CMD_PCI) += cmd_pci.o
  endif
- COBJS-y += cmd_pcmcia.o
- COBJS-$(CONFIG_CMD_PORTIO) += cmd_portio.o
- COBJS-$(CONFIG_CMD_PXE) += cmd_pxe.o
- COBJS-$(CONFIG_CMD_READ) += cmd_read.o
- COBJS-$(CONFIG_CMD_REGINFO) += cmd_reginfo.o
- COBJS-$(CONFIG_CMD_REISER) += cmd_reiser.o
- COBJS-$(CONFIG_SANDBOX) += cmd_sandbox.o
- COBJS-$(CONFIG_CMD_SATA) += cmd_sata.o
- COBJS-$(CONFIG_CMD_SF) += cmd_sf.o
- COBJS-$(CONFIG_CMD_SCSI) += cmd_scsi.o
- COBJS-$(CONFIG_CMD_SHA1SUM) += cmd_sha1sum.o
- COBJS-$(CONFIG_CMD_SETEXPR) += cmd_setexpr.o
- COBJS-$(CONFIG_CMD_SOFTSWITCH) += cmd_softswitch.o
- COBJS-$(CONFIG_CMD_SPI) += cmd_spi.o
- COBJS-$(CONFIG_CMD_SPIBOOTLDR) += cmd_spibootldr.o
- COBJS-$(CONFIG_CMD_STRINGS) += cmd_strings.o
- COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o
- COBJS-$(CONFIG_CMD_TIME) += cmd_time.o
- COBJS-$(CONFIG_CMD_TRACE) += cmd_trace.o
- COBJS-$(CONFIG_SYS_HUSH_PARSER) += cmd_test.o
- COBJS-$(CONFIG_CMD_TPM) += cmd_tpm.o
- COBJS-$(CONFIG_CMD_TSI148) += cmd_tsi148.o
- COBJS-$(CONFIG_CMD_UBI) += cmd_ubi.o
- COBJS-$(CONFIG_CMD_UBIFS) += cmd_ubifs.o
- COBJS-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o
- COBJS-$(CONFIG_CMD_UNZIP) += cmd_unzip.o
+ obj-y += cmd_pcmcia.o
+ obj-$(CONFIG_CMD_PORTIO) += cmd_portio.o
+ obj-$(CONFIG_CMD_PXE) += cmd_pxe.o
+ obj-$(CONFIG_CMD_READ) += cmd_read.o
+ obj-$(CONFIG_CMD_REGINFO) += cmd_reginfo.o
+ obj-$(CONFIG_CMD_REISER) += cmd_reiser.o
+ obj-$(CONFIG_SANDBOX) += cmd_sandbox.o
+ obj-$(CONFIG_CMD_SATA) += cmd_sata.o
+ obj-$(CONFIG_CMD_SF) += cmd_sf.o
+ obj-$(CONFIG_CMD_SCSI) += cmd_scsi.o
+ obj-$(CONFIG_CMD_SHA1SUM) += cmd_sha1sum.o
+ obj-$(CONFIG_CMD_SETEXPR) += cmd_setexpr.o
+ obj-$(CONFIG_CMD_SOFTSWITCH) += cmd_softswitch.o
+ obj-$(CONFIG_CMD_SPI) += cmd_spi.o
+ obj-$(CONFIG_CMD_SPIBOOTLDR) += cmd_spibootldr.o
+ obj-$(CONFIG_CMD_STRINGS) += cmd_strings.o
+ obj-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o
+ obj-$(CONFIG_CMD_TIME) += cmd_time.o
+ obj-$(CONFIG_CMD_TRACE) += cmd_trace.o
+ obj-$(CONFIG_SYS_HUSH_PARSER) += cmd_test.o
+ obj-$(CONFIG_CMD_TPM) += cmd_tpm.o
+ obj-$(CONFIG_CMD_TSI148) += cmd_tsi148.o
+ obj-$(CONFIG_CMD_UBI) += cmd_ubi.o
+ obj-$(CONFIG_CMD_UBIFS) += cmd_ubifs.o
+ obj-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o
+ obj-$(CONFIG_CMD_UNZIP) += cmd_unzip.o
  ifdef CONFIG_CMD_USB
- COBJS-y += cmd_usb.o
- COBJS-y += usb.o usb_hub.o
- COBJS-$(CONFIG_USB_STORAGE) += usb_storage.o
+ obj-y += cmd_usb.o
+ obj-y += usb.o usb_hub.o
+ obj-$(CONFIG_USB_STORAGE) += usb_storage.o
  endif
- COBJS-$(CONFIG_CMD_USB_MASS_STORAGE) += cmd_usb_mass_storage.o
- COBJS-$(CONFIG_CMD_XIMG) += cmd_ximg.o
- COBJS-$(CONFIG_YAFFS2) += cmd_yaffs2.o
- COBJS-$(CONFIG_CMD_SPL) += cmd_spl.o
- COBJS-$(CONFIG_CMD_ZIP) += cmd_zip.o
- COBJS-$(CONFIG_CMD_ZFS) += cmd_zfs.o
- COBJS-$(CONFIG_CMD_ZYNQ_RSA) += cmd_zynq_rsa.o
+ obj-$(CONFIG_CMD_USB_MASS_STORAGE) += cmd_usb_mass_storage.o
+ obj-$(CONFIG_CMD_THOR_DOWNLOAD) += cmd_thordown.o
+ obj-$(CONFIG_CMD_XIMG) += cmd_ximg.o
+ obj-$(CONFIG_YAFFS2) += cmd_yaffs2.o
+ obj-$(CONFIG_CMD_SPL) += cmd_spl.o
+ obj-$(CONFIG_CMD_ZIP) += cmd_zip.o
+ obj-$(CONFIG_CMD_ZFS) += cmd_zfs.o
++obj-$(CONFIG_CMD_ZYNQ_RSA) += cmd_zynq_rsa.o
  
  # others
- COBJS-$(CONFIG_BOOTSTAGE) += bootstage.o
- COBJS-$(CONFIG_CONSOLE_MUX) += iomux.o
- COBJS-y += flash.o
- COBJS-$(CONFIG_CMD_KGDB) += kgdb.o kgdb_stubs.o
- COBJS-$(CONFIG_I2C_EDID) += edid.o
- COBJS-$(CONFIG_KALLSYMS) += kallsyms.o
- COBJS-y += splash.o
- COBJS-$(CONFIG_LCD) += lcd.o
- COBJS-$(CONFIG_LYNXKDI) += lynxkdi.o
- COBJS-$(CONFIG_MENU) += menu.o
- COBJS-$(CONFIG_MODEM_SUPPORT) += modem.o
- COBJS-$(CONFIG_UPDATE_TFTP) += update.o
- COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
- COBJS-$(CONFIG_CMD_DFU) += cmd_dfu.o
- COBJS-$(CONFIG_CMD_GPT) += cmd_gpt.o
+ obj-$(CONFIG_BOOTSTAGE) += bootstage.o
+ obj-$(CONFIG_CONSOLE_MUX) += iomux.o
+ obj-y += flash.o
+ obj-$(CONFIG_CMD_KGDB) += kgdb.o kgdb_stubs.o
+ obj-$(CONFIG_I2C_EDID) += edid.o
+ obj-$(CONFIG_KALLSYMS) += kallsyms.o
+ obj-y += splash.o
+ obj-$(CONFIG_LCD) += lcd.o
+ obj-$(CONFIG_LYNXKDI) += lynxkdi.o
+ obj-$(CONFIG_MENU) += menu.o
+ obj-$(CONFIG_MODEM_SUPPORT) += modem.o
+ obj-$(CONFIG_UPDATE_TFTP) += update.o
+ obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
+ obj-$(CONFIG_CMD_DFU) += cmd_dfu.o
+ obj-$(CONFIG_CMD_GPT) += cmd_gpt.o
  endif
  
  ifdef CONFIG_SPL_BUILD
diff --cc drivers/mtd/nand/Makefile
index 6b28bdcdf82,02b149cacca..abe9330d4d6
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@@ -40,31 -34,31 +34,32 @@@ endif # not sp
  
  ifdef NORMAL_DRIVERS
  
- COBJS-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
- 
- COBJS-$(CONFIG_NAND_ATMEL) += atmel_nand.o
- COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
- COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
- COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
- COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
- COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
- COBJS-$(CONFIG_NAND_FSMC) += fsmc_nand.o
- COBJS-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
- COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o
- COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
- COBJS-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
- COBJS-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
- COBJS-$(CONFIG_NAND_MXC) += mxc_nand.o
- COBJS-$(CONFIG_NAND_MXS) += mxs_nand.o
- COBJS-$(CONFIG_NAND_NDFC) += ndfc.o
- COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
- COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
- COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
- COBJS-$(CONFIG_TEGRA_NAND) += tegra_nand.o
- COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
- COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
- COBJS-$(CONFIG_NAND_DOCG4) += docg4.o
- COBJS-$(CONFIG_NAND_ZYNQ) += zynq_nand.o
+ obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
+ 
+ obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
+ obj-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
+ obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
+ obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
+ obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
+ obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
+ obj-$(CONFIG_NAND_FSMC) += fsmc_nand.o
+ obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
+ obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
+ obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
+ obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
+ obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
+ obj-$(CONFIG_NAND_MXC) += mxc_nand.o
+ obj-$(CONFIG_NAND_MXS) += mxs_nand.o
+ obj-$(CONFIG_NAND_NDFC) += ndfc.o
+ obj-$(CONFIG_NAND_NOMADIK) += nomadik.o
+ obj-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
+ obj-$(CONFIG_NAND_SPEAR) += spr_nand.o
+ obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
+ obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
+ obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
+ obj-$(CONFIG_NAND_PLAT) += nand_plat.o
+ obj-$(CONFIG_NAND_DOCG4) += docg4.o
++obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o
  
  else  # minimal SPL drivers
  
diff --cc drivers/net/Makefile
index de2b21ea928,7f9ce90a6d5..42a6ffa912a
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@@ -5,82 -5,61 +5,60 @@@
  # SPDX-License-Identifier:	GPL-2.0+
  #
  
- include $(TOPDIR)/config.mk
- 
- LIB	:= $(obj)libnet.o
- 
- COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
- COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o
- COBJS-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
- COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
- COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o
- COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o
- COBJS-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o
- COBJS-$(CONFIG_CS8900) += cs8900.o
- COBJS-$(CONFIG_TULIP) += dc2114x.o
- COBJS-$(CONFIG_DESIGNWARE_ETH) += designware.o
- COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
- COBJS-$(CONFIG_DNET) += dnet.o
- COBJS-$(CONFIG_E1000) += e1000.o
- COBJS-$(CONFIG_E1000_SPI) += e1000_spi.o
- COBJS-$(CONFIG_EEPRO100) += eepro100.o
- COBJS-$(CONFIG_ENC28J60) += enc28j60.o
- COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o
- COBJS-$(CONFIG_ETHOC) += ethoc.o
- COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o
- COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
- COBJS-$(CONFIG_FTGMAC100) += ftgmac100.o
- COBJS-$(CONFIG_FTMAC110) += ftmac110.o
- COBJS-$(CONFIG_FTMAC100) += ftmac100.o
- COBJS-$(CONFIG_GRETH) += greth.o
- COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
- COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
- COBJS-$(CONFIG_KS8851_MLL) += ks8851_mll.o
- COBJS-$(CONFIG_LAN91C96) += lan91c96.o
- COBJS-$(CONFIG_MACB) += macb.o
- COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
- COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
- COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
- COBJS-$(CONFIG_MVGBE) += mvgbe.o
- COBJS-$(CONFIG_NATSEMI) += natsemi.o
- COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
- COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
- COBJS-$(CONFIG_NETCONSOLE) += netconsole.o
- COBJS-$(CONFIG_NS8382X) += ns8382x.o
- COBJS-$(CONFIG_PCNET) += pcnet.o
- COBJS-$(CONFIG_PLB2800_ETHER) += plb2800_eth.o
- COBJS-$(CONFIG_RTL8139) += rtl8139.o
- COBJS-$(CONFIG_RTL8169) += rtl8169.o
- COBJS-$(CONFIG_SH_ETHER) += sh_eth.o
- COBJS-$(CONFIG_SMC91111) += smc91111.o
- COBJS-$(CONFIG_SMC911X) += smc911x.o
- COBJS-$(CONFIG_SUNXI_WEMAC) += sunxi_wemac.o
- COBJS-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
- COBJS-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
- COBJS-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
- COBJS-$(CONFIG_FMAN_ENET) += fsl_mdio.o
- COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o
- COBJS-$(CONFIG_ULI526X) += uli526x.o
- COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o
- COBJS-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
- COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
- COBJS-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o
- COBJS-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
- 
- COBJS	:= $(sort $(COBJS-y))
- SRCS	:= $(COBJS:.o=.c)
- OBJS	:= $(addprefix $(obj),$(COBJS))
- 
- all:	$(LIB)
- 
- $(LIB):	$(obj).depend $(OBJS)
- 	$(call cmd_link_o_target, $(OBJS))
- 
- #########################################################################
- 
- # defines $(obj).depend target
- include $(SRCTREE)/rules.mk
- 
- sinclude $(obj).depend
- 
- #########################################################################
+ obj-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
+ obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
+ obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
+ obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
+ obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
+ obj-$(CONFIG_BFIN_MAC) += bfin_mac.o
+ obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o
+ obj-$(CONFIG_CS8900) += cs8900.o
+ obj-$(CONFIG_TULIP) += dc2114x.o
+ obj-$(CONFIG_DESIGNWARE_ETH) += designware.o
+ obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
+ obj-$(CONFIG_DNET) += dnet.o
+ obj-$(CONFIG_E1000) += e1000.o
+ obj-$(CONFIG_E1000_SPI) += e1000_spi.o
+ obj-$(CONFIG_EEPRO100) += eepro100.o
+ obj-$(CONFIG_ENC28J60) += enc28j60.o
+ obj-$(CONFIG_EP93XX) += ep93xx_eth.o
+ obj-$(CONFIG_ETHOC) += ethoc.o
+ obj-$(CONFIG_FEC_MXC) += fec_mxc.o
+ obj-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
+ obj-$(CONFIG_FTGMAC100) += ftgmac100.o
+ obj-$(CONFIG_FTMAC110) += ftmac110.o
+ obj-$(CONFIG_FTMAC100) += ftmac100.o
+ obj-$(CONFIG_GRETH) += greth.o
+ obj-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
+ obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
+ obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
+ obj-$(CONFIG_LAN91C96) += lan91c96.o
+ obj-$(CONFIG_MACB) += macb.o
+ obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
+ obj-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
+ obj-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
+ obj-$(CONFIG_MVGBE) += mvgbe.o
+ obj-$(CONFIG_NATSEMI) += natsemi.o
+ obj-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
+ obj-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
+ obj-$(CONFIG_NETCONSOLE) += netconsole.o
+ obj-$(CONFIG_NS8382X) += ns8382x.o
+ obj-$(CONFIG_PCNET) += pcnet.o
+ obj-$(CONFIG_PLB2800_ETHER) += plb2800_eth.o
+ obj-$(CONFIG_RTL8139) += rtl8139.o
+ obj-$(CONFIG_RTL8169) += rtl8169.o
+ obj-$(CONFIG_SH_ETHER) += sh_eth.o
+ obj-$(CONFIG_SMC91111) += smc91111.o
+ obj-$(CONFIG_SMC911X) += smc911x.o
+ obj-$(CONFIG_SUNXI_WEMAC) += sunxi_wemac.o
+ obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
+ obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
+ obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
+ obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
+ obj-$(CONFIG_TSI108_ETH) += tsi108_eth.o
+ obj-$(CONFIG_ULI526X) += uli526x.o
+ obj-$(CONFIG_VSC7385_ENET) += vsc7385.o
+ obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
+ obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
 -obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \
 -		xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o
++obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o
+ obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
diff --cc drivers/spi/Makefile
index 37c3d04a58c,81b6af66949..3822245eb07
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@@ -5,58 -5,38 +5,39 @@@
  # SPDX-License-Identifier:	GPL-2.0+
  #
  
- include $(TOPDIR)/config.mk
- 
- LIB	:= $(obj)libspi.o
- 
  # There are many options which enable SPI, so make this library available
- COBJS-y += spi.o
- 
- COBJS-$(CONFIG_ALTERA_SPI) += altera_spi.o
- COBJS-$(CONFIG_ANDES_SPI) += andes_spi.o
- COBJS-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
- COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
- COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
- COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
- COBJS-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
- COBJS-$(CONFIG_CF_SPI) += cf_spi.o
- COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o
- COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
- COBJS-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
- COBJS-$(CONFIG_ICH_SPI) +=  ich.o
- COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
- COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
- COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
- COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
- COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o
- COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
- COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
- COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
- COBJS-$(CONFIG_SH_SPI) += sh_spi.o
- COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
- COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
- COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
- COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
- COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
- COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
- COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
- COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
- COBJS-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o
- 
- COBJS	:= $(COBJS-y)
- SRCS	:= $(COBJS:.o=.c)
- OBJS	:= $(addprefix $(obj),$(COBJS))
- 
- all:	$(LIB)
- 
- $(LIB):	$(obj).depend $(OBJS)
- 	$(call cmd_link_o_target, $(OBJS))
- 
- #########################################################################
- 
- # defines $(obj).depend target
- include $(SRCTREE)/rules.mk
- 
- sinclude $(obj).depend
- 
- #########################################################################
+ obj-y += spi.o
+ 
+ obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
+ obj-$(CONFIG_ANDES_SPI) += andes_spi.o
+ obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
+ obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
+ obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
+ obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
+ obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
+ obj-$(CONFIG_CF_SPI) += cf_spi.o
+ obj-$(CONFIG_CF_QSPI) += cf_qspi.o
+ obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
+ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
+ obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
+ obj-$(CONFIG_ICH_SPI) +=  ich.o
+ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
+ obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
+ obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
+ obj-$(CONFIG_MXC_SPI) += mxc_spi.o
+ obj-$(CONFIG_MXS_SPI) += mxs_spi.o
+ obj-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
+ obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+ obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
+ obj-$(CONFIG_SOFT_SPI) += soft_spi.o
+ obj-$(CONFIG_SH_SPI) += sh_spi.o
+ obj-$(CONFIG_SH_QSPI) += sh_qspi.o
+ obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
+ obj-$(CONFIG_FDT_SPI) += fdt_spi.o
+ obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
+ obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
+ obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+ obj-$(CONFIG_TI_QSPI) += ti_qspi.o
+ obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
+ obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
++obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o
diff --cc drivers/spi/zynq_qspi.c
index b9bf2b95fad,00000000000..5d09b56ca9c
mode 100644,000000..100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@@ -1,987 -1,0 +1,984 @@@
 +/*
 + * (C) Copyright 2011 - 2013 Xilinx
 + *
 + * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
 + *
 + * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#include <common.h>
 +#include <malloc.h>
 +#include <ubi_uboot.h>
 +#include <spi.h>
 +#include <spi_flash.h>
 +#include <asm/io.h>
 +#include <asm/arch/hardware.h>
 +#include <asm/arch/sys_proto.h>
 +#include <asm/arch/clk.h>
 +
 +/* QSPI Transmit Data Register */
 +#define ZYNQ_QSPI_TXD_00_00_OFFSET	0x1C /* Transmit 4-byte inst, WO */
 +#define ZYNQ_QSPI_TXD_00_01_OFFSET	0x80 /* Transmit 1-byte inst, WO */
 +#define ZYNQ_QSPI_TXD_00_10_OFFSET	0x84 /* Transmit 2-byte inst, WO */
 +#define ZYNQ_QSPI_TXD_00_11_OFFSET	0x88 /* Transmit 3-byte inst, WO */
 +
 +/*
 + * QSPI Configuration Register bit Masks
 + *
 + * This register contains various control bits that effect the operation
 + * of the QSPI controller
 + */
 +#define ZYNQ_QSPI_CONFIG_IFMODE_MASK	(1 << 31)  /* Flash intrface mode*/
 +#define ZYNQ_QSPI_CONFIG_HOLDB_MASK	(1 << 19)  /* Holdb Mask */
 +#define ZYNQ_QSPI_CONFIG_MSA_MASK	(1 << 15)  /* Manual start enb */
 +#define ZYNQ_QSPI_CONFIG_MCS_MASK	(1 << 14)  /* Manual chip select */
 +#define ZYNQ_QSPI_CONFIG_PCS_MASK	(1 << 10)  /* Peri chip select */
 +#define ZYNQ_QSPI_CONFIG_REFCLK_MASK	(1 << 8)   /* Ref Clock Mask */
 +#define ZYNQ_QSPI_CONFIG_FW_MASK	(0x3 << 6) /* FIFO width */
 +#define ZYNQ_QSPI_CONFIG_BAUDRATE_MASK	(0x7 << 3) /* Baudrate Divisor Mask */
 +#define ZYNQ_QSPI_CONFIG_MSTREN_MASK	(1 << 0)   /* Mode select */
 +#define ZYNQ_QSPI_CONFIG_MANSRT_MASK	0x00010000 /* Manual TX Start */
 +#define ZYNQ_QSPI_CONFIG_CPHA_MASK	0x00000004 /* Clock Phase Control */
 +#define ZYNQ_QSPI_CONFIG_CPOL_MASK	0x00000002 /* Clock Polarity Control */
 +#define ZYNQ_QSPI_CONFIG_SSCTRL_MASK	0x00003C00 /* Slave Select Mask */
 +#define ZYNQ_QSPI_CONFIG_CLR_ALL_MASK	(ZYNQ_QSPI_CONFIG_IFMODE_MASK | \
 +					ZYNQ_QSPI_CONFIG_HOLDB_MASK | \
 +					ZYNQ_QSPI_CONFIG_MANSRT_MASK | \
 +					ZYNQ_QSPI_CONFIG_MSA_MASK | \
 +					ZYNQ_QSPI_CONFIG_MCS_MASK | \
 +					ZYNQ_QSPI_CONFIG_PCS_MASK | \
 +					ZYNQ_QSPI_CONFIG_REFCLK_MASK | \
 +					ZYNQ_QSPI_CONFIG_FW_MASK | \
 +					ZYNQ_QSPI_CONFIG_BAUDRATE_MASK | \
 +					ZYNQ_QSPI_CONFIG_CPHA_MASK | \
 +					ZYNQ_QSPI_CONFIG_CPOL_MASK | \
 +					ZYNQ_QSPI_CONFIG_MSTREN_MASK)
 +
 +/*
 + * QSPI Interrupt Registers bit Masks
 + *
 + * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
 + * bit definitions.
 + */
 +#define ZYNQ_QSPI_IXR_TXNFULL_MASK	0x00000004 /* QSPI TX FIFO Overflow */
 +#define ZYNQ_QSPI_IXR_TXFULL_MASK	0x00000008 /* QSPI TX FIFO is full */
 +#define ZYNQ_QSPI_IXR_RXNEMTY_MASK	0x00000010 /* QSPI RX FIFO Not Empty */
 +#define ZYNQ_QSPI_IXR_ALL_MASK		(ZYNQ_QSPI_IXR_TXNFULL_MASK | \
 +					ZYNQ_QSPI_IXR_RXNEMTY_MASK)
 +
 +/*
 + * QSPI Enable Register bit Masks
 + *
 + * This register is used to enable or disable the QSPI controller
 + */
 +#define ZYNQ_QSPI_ENABLE_ENABLE_MASK	0x00000001 /* QSPI Enable Bit Mask */
 +
 +/*
 + * QSPI Linear Configuration Register
 + *
 + * It is named Linear Configuration but it controls other modes when not in
 + * linear mode also.
 + */
 +#define ZYNQ_QSPI_LCFG_TWO_MEM_MASK	0x40000000 /* QSPI Enable Bit Mask */
 +#define ZYNQ_QSPI_LCFG_SEP_BUS_MASK	0x20000000 /* QSPI Enable Bit Mask */
 +#define ZYNQ_QSPI_LCFG_U_PAGE		0x10000000 /* QSPI Upper memory set */
 +
 +#define ZYNQ_QSPI_LCFG_DUMMY_SHIFT	8
 +
 +#define ZYNQ_QSPI_FR_QOUT_CODE	0x6B	/* read instruction code */
 +
 +/*
 + * The modebits configurable by the driver to make the SPI support different
 + * data formats
 + */
 +#define MODEBITS			(SPI_CPOL | SPI_CPHA)
 +
 +/* Definitions for the status of queue */
 +#define ZYNQ_QSPI_QUEUE_STOPPED		0
 +#define ZYNQ_QSPI_QUEUE_RUNNING		1
 +#define ZYNQ_QSPI_RXFIFO_THRESHOLD	32
 +#define ZYNQ_QSPI_FIFO_DEPTH		63
 +
 +/* QSPI MIO's count for different connection topologies */
 +#define ZYNQ_QSPI_MIO_NUM_QSPI0		6
 +#define ZYNQ_QSPI_MIO_NUM_QSPI1		5
 +#define ZYNQ_QSPI_MIO_NUM_QSPI1_CS	1
 +
 +/* Definitions of the flash commands - Flash opcodes in ascending order */
 +#define ZYNQ_QSPI_FLASH_OPCODE_WRSR	0x01	/* Write status register */
 +#define ZYNQ_QSPI_FLASH_OPCODE_PP	0x02	/* Page program */
 +#define ZYNQ_QSPI_FLASH_OPCODE_NR	0x03	/* Normal read data bytes */
 +#define ZYNQ_QSPI_FLASH_OPCODE_WRDS	0x04	/* Write disable */
 +#define ZYNQ_QSPI_FLASH_OPCODE_RDSR1	0x05	/* Read status register 1 */
 +#define ZYNQ_QSPI_FLASH_OPCODE_WREN	0x06	/* Write enable */
 +#define ZYNQ_QSPI_FLASH_OPCODE_FR	0x0B	/* Fast read data bytes */
 +#define ZYNQ_QSPI_FLASH_OPCODE_BRRD	0x16	/* Bank address reg read */
 +#define ZYNQ_QSPI_FLASH_OPCODE_BRWR	0x17	/* Bank address reg write */
 +#define ZYNQ_QSPI_FLASH_OPCODE_BE_4K	0x20	/* Erase 4KiB block */
 +#define ZYNQ_QSPI_FLASH_OPCODE_QPP	0x32	/* Quad Page Program */
 +#define ZYNQ_QSPI_FLASH_OPCODE_RDSR2	0x35	/* Read status register 2 */
 +#define ZYNQ_QSPI_FLASH_OPCODE_DR	0x3B	/* Dual read data bytes */
 +#define ZYNQ_QSPI_FLASH_OPCODE_BE_32K	0x52	/* Erase 32KiB block */
 +#define ZYNQ_QSPI_FLASH_OPCODE_QR	0x6B	/* Quad read data bytes */
 +#define ZYNQ_QSPI_FLASH_OPCODE_ES	0x75	/* Erase suspend */
 +#define ZYNQ_QSPI_FLASH_OPCODE_ER	0x7A	/* Erase resume */
 +#define ZYNQ_QSPI_FLASH_OPCODE_RDID	0x9F	/* Read JEDEC ID */
 +#define ZYNQ_QSPI_FLASH_OPCODE_DIOR	0xBB	/* Dual IO high perf read */
 +#define ZYNQ_QSPI_FLASH_OPCODE_WREAR	0xC5	/* Extended address reg write */
 +#define ZYNQ_QSPI_FLASH_OPCODE_RDEAR	0xC8	/* Extended address reg read */
 +#define ZYNQ_QSPI_FLASH_OPCODE_BE	0xC7	/* Erase whole flash block */
 +#define ZYNQ_QSPI_FLASH_OPCODE_SE	0xD8	/* Sector erase (usually 64KB)*/
 +
 +/* QSPI register offsets */
 +struct zynq_qspi_regs {
 +	u32 confr;	/* 0x00 */
 +	u32 isr;	/* 0x04 */
 +	u32 ier;	/* 0x08 */
 +	u32 idisr;	/* 0x0C */
 +	u32 imaskr;	/* 0x10 */
 +	u32 enbr;	/* 0x14 */
 +	u32 dr;		/* 0x18 */
 +	u32 txd0r;	/* 0x1C */
 +	u32 drxr;	/* 0x20 */
 +	u32 sicr;	/* 0x24 */
 +	u32 txftr;	/* 0x28 */
 +	u32 rxftr;	/* 0x2C */
 +	u32 gpior;	/* 0x30 */
 +	u32 reserved0[19];
 +	u32 txd1r;	/* 0x80 */
 +	u32 txd2r;	/* 0x84 */
 +	u32 txd3r;	/* 0x88 */
 +	u32 reserved1[5];
 +	u32 lcr;	/* 0xA0 */
 +	u32 reserved2[22];
 +	u32 midr;	/* 0xFC */
 +};
 +
 +#define zynq_qspi_base ((struct zynq_qspi_regs *)ZYNQ_QSPI_BASEADDR)
 +
 +struct zynq_qspi {
 +	u32 input_clk_hz;
 +	u32 speed_hz;
 +	const void *txbuf;
 +	void *rxbuf;
 +	int bytes_to_transfer;
 +	int bytes_to_receive;
 +	struct zynq_qspi_inst_format *curr_inst;
 +	u8 inst_response;
 +	unsigned int is_inst;
 +	unsigned int is_dual;
 +	unsigned int u_page;
 +};
 +
 +struct spi_device {
 +	struct zynq_qspi master;
 +	u32 max_speed_hz;
 +	u8 chip_select;
 +	u8 mode;
 +	u8 bits_per_word;
 +};
 +
 +struct spi_transfer {
 +	const void *tx_buf;
 +	void *rx_buf;
 +	unsigned len;
 +	unsigned cs_change:1;
 +	u8 bits_per_word;
 +	u16 delay_usecs;
 +	u32 speed_hz;
 +};
 +
 +struct zynq_qspi_slave {
 +	struct spi_slave slave;
 +	struct spi_device qspi;
 +};
 +#define to_zynq_qspi_slave(s) container_of(s, struct zynq_qspi_slave, slave)
 +
 +/*
 + * struct zynq_qspi_inst_format - Defines qspi flash instruction format
 + * @opcode:		Operational code of instruction
 + * @inst_size:		Size of the instruction including address bytes
 + * @offset:		Register address where instruction has to be written
 + */
 +struct zynq_qspi_inst_format {
 +	u8 opcode;
 +	u8 inst_size;
 +	u8 offset;
 +};
 +
 +/* List of all the QSPI instructions and its format */
 +static struct zynq_qspi_inst_format flash_inst[] = {
 +	{ ZYNQ_QSPI_FLASH_OPCODE_WREN, 1, ZYNQ_QSPI_TXD_00_01_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_WRDS, 1, ZYNQ_QSPI_TXD_00_01_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_RDSR1, 1, ZYNQ_QSPI_TXD_00_01_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_RDSR2, 1, ZYNQ_QSPI_TXD_00_01_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_WRSR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_PP, 4, ZYNQ_QSPI_TXD_00_00_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_SE, 4, ZYNQ_QSPI_TXD_00_00_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_BE_32K, 4, ZYNQ_QSPI_TXD_00_00_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_BE_4K, 4, ZYNQ_QSPI_TXD_00_00_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_BE, 1, ZYNQ_QSPI_TXD_00_01_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_ES, 1, ZYNQ_QSPI_TXD_00_01_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_ER, 1, ZYNQ_QSPI_TXD_00_01_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_RDID, 1, ZYNQ_QSPI_TXD_00_01_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_NR, 4, ZYNQ_QSPI_TXD_00_00_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_FR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_DR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_QR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_BRWR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_BRRD, 1, ZYNQ_QSPI_TXD_00_01_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_WREAR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_RDEAR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_QPP, 4, ZYNQ_QSPI_TXD_00_00_OFFSET },
 +	{ ZYNQ_QSPI_FLASH_OPCODE_DIOR, 4, ZYNQ_QSPI_TXD_00_00_OFFSET },
 +	/* Add all the instructions supported by the flash device */
 +};
 +
 +/*
 + * zynq_qspi_init_hw - Initialize the hardware
 + * @is_dual:		Indicates whether dual memories are used
 + * @cs:			Indicates which chip select is used in dual stacked
 + *
 + * The default settings of the QSPI controller's configurable parameters on
 + * reset are
 + *	- Master mode
 + *	- Baud rate divisor is set to 2
 + *	- Threshold value for TX FIFO not full interrupt is set to 1
 + *	- Flash memory interface mode enabled
 + *	- Size of the word to be transferred as 8 bit
 + * This function performs the following actions
 + *	- Disable and clear all the interrupts
 + *	- Enable manual slave select
 + *	- Enable manual start
 + *	- Deselect all the chip select lines
 + *	- Set the size of the word to be transferred as 32 bit
 + *	- Set the little endian mode of TX FIFO and
 + *	- Enable the QSPI controller
 + */
 +static void zynq_qspi_init_hw(int is_dual, unsigned int cs)
 +{
 +	u32 config_reg;
 +
 +	writel(~ZYNQ_QSPI_ENABLE_ENABLE_MASK, &zynq_qspi_base->enbr);
 +	writel(0x7F, &zynq_qspi_base->idisr);
 +
 +	/* Disable linear mode as the boot loader may have used it */
 +	writel(0x0, &zynq_qspi_base->lcr);
 +
 +	/* Clear the TX and RX threshold reg */
 +	writel(0x1, &zynq_qspi_base->txftr);
 +	writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, &zynq_qspi_base->rxftr);
 +
 +	/* Clear the RX FIFO */
 +	while (readl(&zynq_qspi_base->isr) & ZYNQ_QSPI_IXR_RXNEMTY_MASK)
 +		readl(&zynq_qspi_base->drxr);
 +
 +	writel(0x7F, &zynq_qspi_base->isr);
 +	config_reg = readl(&zynq_qspi_base->confr);
 +	/* Clear all the bits before setting required configuration */
 +	config_reg &= ~ZYNQ_QSPI_CONFIG_CLR_ALL_MASK;
 +	config_reg |= ZYNQ_QSPI_CONFIG_IFMODE_MASK |
 +		ZYNQ_QSPI_CONFIG_MCS_MASK | ZYNQ_QSPI_CONFIG_PCS_MASK |
 +		ZYNQ_QSPI_CONFIG_FW_MASK | ZYNQ_QSPI_CONFIG_MSTREN_MASK;
- 	if (is_dual == MODE_DUAL_STACKED)
++	if (is_dual == SF_DUAL_STACKED_FLASH)
 +		config_reg |= 0x10;
 +	writel(config_reg, &zynq_qspi_base->confr);
 +
- 	if (is_dual == MODE_DUAL_PARALLEL)
++	if (is_dual == SF_DUAL_PARALLEL_FLASH)
 +		/* Enable two memories on seperate buses */
 +		writel((ZYNQ_QSPI_LCFG_TWO_MEM_MASK |
 +			ZYNQ_QSPI_LCFG_SEP_BUS_MASK |
 +			(1 << ZYNQ_QSPI_LCFG_DUMMY_SHIFT) |
 +			ZYNQ_QSPI_FR_QOUT_CODE),
 +			&zynq_qspi_base->lcr);
- 	else if (is_dual == MODE_DUAL_STACKED)
++	else if (is_dual == SF_DUAL_STACKED_FLASH)
 +		/* Configure two memories on shared bus by enabling lower mem */
 +		writel((ZYNQ_QSPI_LCFG_TWO_MEM_MASK |
 +			(1 << ZYNQ_QSPI_LCFG_DUMMY_SHIFT) |
 +			ZYNQ_QSPI_FR_QOUT_CODE),
 +			&zynq_qspi_base->lcr);
 +
 +	writel(ZYNQ_QSPI_ENABLE_ENABLE_MASK, &zynq_qspi_base->enbr);
 +}
 +
 +/*
 + * zynq_qspi_copy_read_data - Copy data to RX buffer
 + * @zqspi:	Pointer to the zynq_qspi structure
 + * @data:	The 32 bit variable where data is stored
 + * @size:	Number of bytes to be copied from data to RX buffer
 + */
 +static void zynq_qspi_copy_read_data(struct zynq_qspi *zqspi, u32 data, u8 size)
 +{
 +	u8 byte3;
 +
 +	debug("%s: data 0x%04x rxbuf addr: 0x%08x size %d\n", __func__ ,
 +	      data, (unsigned)(zqspi->rxbuf), size);
 +
 +	if (zqspi->rxbuf) {
 +		switch (size) {
 +		case 1:
 +			*((u8 *)zqspi->rxbuf) = data;
 +			zqspi->rxbuf += 1;
 +			break;
 +		case 2:
 +			*((u16 *)zqspi->rxbuf) = data;
 +			zqspi->rxbuf += 2;
 +			break;
 +		case 3:
 +			*((u16 *)zqspi->rxbuf) = data;
 +			zqspi->rxbuf += 2;
 +			byte3 = (u8)(data >> 16);
 +			*((u8 *)zqspi->rxbuf) = byte3;
 +			zqspi->rxbuf += 1;
 +			break;
 +		case 4:
 +			/* Can not assume word aligned buffer */
 +			memcpy(zqspi->rxbuf, &data, size);
 +			zqspi->rxbuf += 4;
 +			break;
 +		default:
 +			/* This will never execute */
 +			break;
 +		}
 +	}
 +	zqspi->bytes_to_receive -= size;
 +	if (zqspi->bytes_to_receive < 0)
 +		zqspi->bytes_to_receive = 0;
 +}
 +
 +/*
 + * zynq_qspi_copy_write_data - Copy data from TX buffer
 + * @zqspi:	Pointer to the zynq_qspi structure
 + * @data:	Pointer to the 32 bit variable where data is to be copied
 + * @size:	Number of bytes to be copied from TX buffer to data
 + */
 +static void zynq_qspi_copy_write_data(struct zynq_qspi *zqspi,
 +		u32 *data, u8 size)
 +{
 +	if (zqspi->txbuf) {
 +		switch (size) {
 +		case 1:
 +			*data = *((u8 *)zqspi->txbuf);
 +			zqspi->txbuf += 1;
 +			*data |= 0xFFFFFF00;
 +			break;
 +		case 2:
 +			*data = *((u16 *)zqspi->txbuf);
 +			zqspi->txbuf += 2;
 +			*data |= 0xFFFF0000;
 +			break;
 +		case 3:
 +			*data = *((u16 *)zqspi->txbuf);
 +			zqspi->txbuf += 2;
 +			*data |= (*((u8 *)zqspi->txbuf) << 16);
 +			zqspi->txbuf += 1;
 +			*data |= 0xFF000000;
 +			break;
 +		case 4:
 +			/* Can not assume word aligned buffer */
 +			memcpy(data, zqspi->txbuf, size);
 +			zqspi->txbuf += 4;
 +			break;
 +		default:
 +			/* This will never execute */
 +			break;
 +		}
 +	} else {
 +		*data = 0;
 +	}
 +
 +	debug("%s: data 0x%08x txbuf addr: 0x%08x size %d\n", __func__,
 +	      *data, (u32)zqspi->txbuf, size);
 +
 +	zqspi->bytes_to_transfer -= size;
 +	if (zqspi->bytes_to_transfer < 0)
 +		zqspi->bytes_to_transfer = 0;
 +}
 +
 +/*
 + * zynq_qspi_chipselect - Select or deselect the chip select line
 + * @qspi:	Pointer to the spi_device structure
 + * @is_on:	Select(1) or deselect (0) the chip select line
 + */
 +static void zynq_qspi_chipselect(struct spi_device *qspi, int is_on)
 +{
 +	u32 config_reg;
 +
 +	debug("%s: is_on: %d\n", __func__, is_on);
 +
 +	config_reg = readl(&zynq_qspi_base->confr);
 +
 +	if (is_on) {
 +		/* Select the slave */
 +		config_reg &= ~ZYNQ_QSPI_CONFIG_SSCTRL_MASK;
 +		config_reg |= (((~(0x0001 << qspi->chip_select)) << 10) &
 +				ZYNQ_QSPI_CONFIG_SSCTRL_MASK);
 +	} else
 +		/* Deselect the slave */
 +		config_reg |= ZYNQ_QSPI_CONFIG_SSCTRL_MASK;
 +
 +	writel(config_reg, &zynq_qspi_base->confr);
 +}
 +
 +/*
 + * zynq_qspi_setup_transfer - Configure QSPI controller for specified transfer
 + * @qspi:	Pointer to the spi_device structure
 + * @transfer:	Pointer to the spi_transfer structure which provides information
 + *		about next transfer setup parameters
 + *
 + * Sets the operational mode of QSPI controller for the next QSPI transfer and
 + * sets the requested clock frequency.
 + *
 + * returns:	0 on success and -1 on invalid input parameter
 + *
 + * Note: If the requested frequency is not an exact match with what can be
 + * obtained using the prescalar value, the driver sets the clock frequency which
 + * is lower than the requested frequency (maximum lower) for the transfer. If
 + * the requested frequency is higher or lower than that is supported by the QSPI
 + * controller the driver will set the highest or lowest frequency supported by
 + * controller.
 + */
 +static int zynq_qspi_setup_transfer(struct spi_device *qspi,
 +		struct spi_transfer *transfer)
 +{
 +	struct zynq_qspi *zqspi = &qspi->master;
 +	u8 bits_per_word;
 +	u32 config_reg;
 +	u32 req_hz;
 +	u32 baud_rate_val = 0;
 +
 +	debug("%s: qspi: 0x%08x transfer: 0x%08x\n", __func__,
 +	      (u32)qspi, (u32)transfer);
 +
 +	bits_per_word = (transfer) ?
 +			transfer->bits_per_word : qspi->bits_per_word;
 +	req_hz = (transfer) ? transfer->speed_hz : qspi->max_speed_hz;
 +
 +	if (qspi->mode & ~MODEBITS) {
 +		printf("%s: Unsupported mode bits %x\n",
 +		       __func__, qspi->mode & ~MODEBITS);
 +		return -1;
 +	}
 +
 +	if (bits_per_word != 32)
 +		bits_per_word = 32;
 +
 +	config_reg = readl(&zynq_qspi_base->confr);
 +
 +	/* Set the QSPI clock phase and clock polarity */
 +	config_reg &= (~ZYNQ_QSPI_CONFIG_CPHA_MASK) &
 +				(~ZYNQ_QSPI_CONFIG_CPOL_MASK);
 +	if (qspi->mode & SPI_CPHA)
 +		config_reg |= ZYNQ_QSPI_CONFIG_CPHA_MASK;
 +	if (qspi->mode & SPI_CPOL)
 +		config_reg |= ZYNQ_QSPI_CONFIG_CPOL_MASK;
 +
 +	/* Set the clock frequency */
 +	if (zqspi->speed_hz != req_hz) {
 +		baud_rate_val = 0;
 +		while ((baud_rate_val < 8) &&
 +			(zqspi->input_clk_hz / (2 << baud_rate_val)) > req_hz) {
 +				baud_rate_val++;
 +		}
 +		config_reg &= 0xFFFFFFC7;
 +		config_reg |= (baud_rate_val << 3);
 +		zqspi->speed_hz = req_hz;
 +	}
 +
 +	writel(config_reg, &zynq_qspi_base->confr);
 +
 +	debug("%s: mode %d, %u bits/w, %u clock speed\n", __func__,
 +	      qspi->mode & MODEBITS, qspi->bits_per_word, zqspi->speed_hz);
 +
 +	return 0;
 +}
 +
 +/*
 + * zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
 + * @zqspi:	Pointer to the zynq_qspi structure
 + */
 +static void zynq_qspi_fill_tx_fifo(struct zynq_qspi *zqspi, u32 size)
 +{
 +	u32 data = 0;
 +	u32 fifocount = 0;
 +	unsigned len, offset;
 +	static const unsigned offsets[4] = {
 +		ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET,
 +		ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET };
 +
 +	while ((fifocount < size) &&
 +			(zqspi->bytes_to_transfer > 0)) {
 +		if (zqspi->bytes_to_transfer >= 4) {
 +			if (zqspi->txbuf) {
 +				memcpy(&data, zqspi->txbuf, 4);
 +				zqspi->txbuf += 4;
 +			} else {
 +				data = 0;
 +			}
 +			writel(data, &zynq_qspi_base->txd0r);
 +			zqspi->bytes_to_transfer -= 4;
 +			fifocount++;
 +		} else {
 +			/* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */
 +			if (!(readl(&zynq_qspi_base->isr)
 +					& ZYNQ_QSPI_IXR_TXNFULL_MASK) &&
 +					!zqspi->rxbuf)
 +				return;
 +			len = zqspi->bytes_to_transfer;
 +			zynq_qspi_copy_write_data(zqspi, &data, len);
 +			offset = (zqspi->rxbuf) ? offsets[0] : offsets[len];
 +			writel(data, &zynq_qspi_base->confr + (offset / 4));
 +		}
 +	}
 +}
 +
 +/*
 + * zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller
 + * @zqspi:	Pointer to the zynq_qspi structure
 + *
 + * This function handles TX empty and Mode Fault interrupts only.
 + * On TX empty interrupt this function reads the received data from RX FIFO and
 + * fills the TX FIFO if there is any data remaining to be transferred.
 + * On Mode Fault interrupt this function indicates that transfer is completed,
 + * the SPI subsystem will identify the error as the remaining bytes to be
 + * transferred is non-zero.
 + *
 + * returns:	0 for poll timeout
 + *		1 transfer operation complete
 + */
 +static int zynq_qspi_irq_poll(struct zynq_qspi *zqspi)
 +{
 +	int max_loop;
 +	u32 intr_status;
 +	u32 rxindex = 0;
 +	u32 rxcount;
 +
 +	debug("%s: zqspi: 0x%08x\n", __func__, (u32)zqspi);
 +
 +	/* Poll until any of the interrupt status bits are set */
 +	max_loop = 0;
 +	do {
 +		intr_status = readl(&zynq_qspi_base->isr);
 +		max_loop++;
 +	} while ((intr_status == 0) && (max_loop < 100000));
 +
 +	if (intr_status == 0) {
 +		printf("%s: Timeout\n", __func__);
 +		return 0;
 +	}
 +
 +	writel(intr_status, &zynq_qspi_base->isr);
 +
 +	/* Disable all interrupts */
 +	writel(ZYNQ_QSPI_IXR_ALL_MASK, &zynq_qspi_base->idisr);
 +	if ((intr_status & ZYNQ_QSPI_IXR_TXNFULL_MASK) ||
 +	    (intr_status & ZYNQ_QSPI_IXR_RXNEMTY_MASK)) {
 +		/*
 +		 * This bit is set when Tx FIFO has < THRESHOLD entries. We have
 +		 * the THRESHOLD value set to 1, so this bit indicates Tx FIFO
 +		 * is empty
 +		 */
 +		rxcount = zqspi->bytes_to_receive - zqspi->bytes_to_transfer;
 +		rxcount = (rxcount % 4) ? ((rxcount/4)+1) : (rxcount/4);
 +		while ((rxindex < rxcount) &&
 +				(rxindex < ZYNQ_QSPI_RXFIFO_THRESHOLD)) {
 +			/* Read out the data from the RX FIFO */
 +				u32 data;
 +
 +				data = readl(&zynq_qspi_base->drxr);
 +
 +				if ((zqspi->inst_response) &&
 +				    (!((zqspi->curr_inst->opcode ==
 +				    ZYNQ_QSPI_FLASH_OPCODE_RDSR1) ||
 +				    (zqspi->curr_inst->opcode ==
 +				    ZYNQ_QSPI_FLASH_OPCODE_RDSR2)))) {
 +					zqspi->inst_response = 0;
 +					zynq_qspi_copy_read_data(zqspi, data,
 +						zqspi->curr_inst->inst_size);
 +				} else if (zqspi->bytes_to_receive < 4) {
 +					zynq_qspi_copy_read_data(zqspi, data,
 +						zqspi->bytes_to_receive);
 +				} else {
 +				if (zqspi->rxbuf) {
 +					memcpy(zqspi->rxbuf, &data, 4);
 +					zqspi->rxbuf += 4;
 +				}
 +				zqspi->bytes_to_receive -= 4;
 +			}
 +			rxindex++;
 +		}
 +
 +		if (zqspi->bytes_to_transfer) {
 +			/* There is more data to send */
 +			zynq_qspi_fill_tx_fifo(zqspi,
 +					       ZYNQ_QSPI_RXFIFO_THRESHOLD);
 +
 +			writel(ZYNQ_QSPI_IXR_ALL_MASK, &zynq_qspi_base->ier);
 +		} else {
 +			/*
 +			 * If transfer and receive is completed then only send
 +			 * complete signal
 +			 */
 +			if (!zqspi->bytes_to_receive) {
 +				/* return operation complete */
 +				writel(ZYNQ_QSPI_IXR_ALL_MASK,
 +				       &zynq_qspi_base->idisr);
 +				return 1;
 +			}
 +		}
 +	}
 +
 +	return 0;
 +}
 +
 +/*
 + * zynq_qspi_start_transfer - Initiates the QSPI transfer
 + * @qspi:	Pointer to the spi_device structure
 + * @transfer:	Pointer to the spi_transfer structure which provide information
 + *		about next transfer parameters
 + *
 + * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
 + * transfer to be completed.
 + *
 + * returns:	Number of bytes transferred in the last transfer
 + */
 +static int zynq_qspi_start_transfer(struct spi_device *qspi,
 +			struct spi_transfer *transfer)
 +{
 +	struct zynq_qspi *zqspi = &qspi->master;
 +	static u8 current_u_page;
 +	u32 data = 0;
 +	u8 instruction = 0;
 +	u8 index;
 +
 +	debug("%s: qspi: 0x%08x transfer: 0x%08x len: %d\n", __func__,
 +	      (u32)qspi, (u32)transfer, transfer->len);
 +
 +	zqspi->txbuf = transfer->tx_buf;
 +	zqspi->rxbuf = transfer->rx_buf;
 +	zqspi->bytes_to_transfer = transfer->len;
 +	zqspi->bytes_to_receive = transfer->len;
 +
 +	if (zqspi->txbuf)
 +		instruction = *(u8 *)zqspi->txbuf;
 +
 +	if (instruction && zqspi->is_inst) {
 +		for (index = 0; index < ARRAY_SIZE(flash_inst); index++)
 +			if (instruction == flash_inst[index].opcode)
 +				break;
 +
 +		/*
 +		 * Instruction might have already been transmitted. This is a
 +		 * 'data only' transfer
 +		 */
 +		if (index == ARRAY_SIZE(flash_inst))
 +			goto xfer_data;
 +
 +		zqspi->curr_inst = &flash_inst[index];
 +		zqspi->inst_response = 1;
 +
- 		if ((zqspi->is_dual == MODE_DUAL_STACKED) &&
++		if ((zqspi->is_dual == SF_DUAL_STACKED_FLASH) &&
 +				(current_u_page != zqspi->u_page)) {
 +			if (zqspi->u_page) {
 +				/* Configure two memories on shared bus
 +				 * by enabling upper mem
 +				 */
 +				writel((ZYNQ_QSPI_LCFG_TWO_MEM_MASK |
 +					ZYNQ_QSPI_LCFG_U_PAGE |
 +					(1 << ZYNQ_QSPI_LCFG_DUMMY_SHIFT) |
 +					ZYNQ_QSPI_FR_QOUT_CODE),
 +					&zynq_qspi_base->lcr);
 +			} else {
 +				/* Configure two memories on shared bus
 +				 * by enabling lower mem
 +				 */
 +				writel((ZYNQ_QSPI_LCFG_TWO_MEM_MASK |
 +					(1 << ZYNQ_QSPI_LCFG_DUMMY_SHIFT) |
 +					ZYNQ_QSPI_FR_QOUT_CODE),
 +					&zynq_qspi_base->lcr);
 +			}
 +
 +			current_u_page = zqspi->u_page;
 +		}
 +
 +		/* Get the instruction */
 +		data = 0;
 +		zynq_qspi_copy_write_data(zqspi, &data,
 +					zqspi->curr_inst->inst_size);
 +
 +		/*
 +		 * Write the instruction to LSB of the FIFO. The core is
 +		 * designed such that it is not necessary to check whether the
 +		 * write FIFO is full before writing. However, write would be
 +		 * delayed if the user tries to write when write FIFO is full
 +		 */
 +		writel(data, &zynq_qspi_base->confr +
 +				(zqspi->curr_inst->offset / 4));
 +
 +		/*
 +		 * Read status register and Read ID instructions don't require
 +		 * to ignore the extra bytes in response of instruction as
 +		 * response contains the value
 +		 */
 +		if ((instruction == ZYNQ_QSPI_FLASH_OPCODE_RDSR1) ||
 +		    (instruction == ZYNQ_QSPI_FLASH_OPCODE_RDSR2) ||
 +		    (instruction == ZYNQ_QSPI_FLASH_OPCODE_RDID) ||
 +		    (instruction == ZYNQ_QSPI_FLASH_OPCODE_BRRD) ||
 +		    (instruction == ZYNQ_QSPI_FLASH_OPCODE_RDEAR)) {
 +			if (zqspi->bytes_to_transfer < 4)
 +				zqspi->bytes_to_transfer = 0;
 +			else
 +				zqspi->bytes_to_transfer -= 3;
 +		}
 +	}
 +
 +xfer_data:
 +	/*
 +	 * In case of Fast, Dual and Quad reads, transmit the instruction first.
 +	 * Address and dummy byte should be transmitted after instruction
 +	 * is transmitted
 +	 */
 +	if (((zqspi->is_inst == 0) && (zqspi->bytes_to_transfer)) ||
 +	    ((zqspi->bytes_to_transfer) &&
 +	     (instruction != ZYNQ_QSPI_FLASH_OPCODE_FR) &&
 +	     (instruction != ZYNQ_QSPI_FLASH_OPCODE_DR) &&
 +	     (instruction != ZYNQ_QSPI_FLASH_OPCODE_QR) &&
 +	     (instruction != ZYNQ_QSPI_FLASH_OPCODE_DIOR)))
 +		zynq_qspi_fill_tx_fifo(zqspi, ZYNQ_QSPI_FIFO_DEPTH);
 +
 +	writel(ZYNQ_QSPI_IXR_ALL_MASK, &zynq_qspi_base->ier);
 +	/* Start the transfer by enabling manual start bit */
 +
 +	/* wait for completion */
 +	do {
 +		data = zynq_qspi_irq_poll(zqspi);
 +	} while (data == 0);
 +
 +	return (transfer->len) - (zqspi->bytes_to_transfer);
 +}
 +
 +static int zynq_qspi_transfer(struct spi_device *qspi,
 +		struct spi_transfer *transfer)
 +{
 +	struct zynq_qspi *zqspi = &qspi->master;
 +	unsigned cs_change = 1;
 +	int status = 0;
 +
 +	debug("%s\n", __func__);
 +
 +	while (1) {
 +		if (transfer->bits_per_word || transfer->speed_hz) {
 +			status = zynq_qspi_setup_transfer(qspi, transfer);
 +			if (status < 0)
 +				break;
 +		}
 +
 +		/* Select the chip if required */
 +		if (cs_change)
 +			zynq_qspi_chipselect(qspi, 1);
 +
 +		cs_change = transfer->cs_change;
 +
 +		if (!transfer->tx_buf && !transfer->rx_buf && transfer->len) {
 +			status = -1;
 +			break;
 +		}
 +
 +		/* Request the transfer */
 +		if (transfer->len) {
 +			status = zynq_qspi_start_transfer(qspi, transfer);
 +			zqspi->is_inst = 0;
 +		}
 +
 +		if (status != transfer->len) {
 +			if (status > 0)
 +				status = -EMSGSIZE;
 +			break;
 +		}
 +		status = 0;
 +
 +		if (transfer->delay_usecs)
 +			udelay(transfer->delay_usecs);
 +
 +		if (cs_change)
 +			/* Deselect the chip */
 +			zynq_qspi_chipselect(qspi, 0);
 +
 +		break;
 +	}
 +
 +	zynq_qspi_setup_transfer(qspi, NULL);
 +
 +	return 0;
 +}
 +
 +/*
 + * zynq_qspi_check_is_dual_flash - checking for dual or single qspi
 + *
 + * This function will check the type of the flash whether it supports
 + * single or dual qspi based on the MIO configuration done by FSBL.
 + *
 + * User needs to correctly configure the MIO's based on the
 + * number of qspi flashes present on the board.
 + *
 + * function will return -1, if there is no MIO configuration for
 + * qspi flash.
 + */
 +static int zynq_qspi_check_is_dual_flash(void)
 +{
- 	int is_dual = MODE_UNKNOWN;
++	int is_dual = -1;
 +	int lower_mio = 0, upper_mio = 0, upper_mio_cs1 = 0;
 +
 +	lower_mio = zynq_slcr_get_mio_pin_status("qspi0");
 +	if (lower_mio == ZYNQ_QSPI_MIO_NUM_QSPI0)
- 		is_dual = MODE_SINGLE;
++		is_dual = SF_SINGLE_FLASH;
 +
 +	upper_mio_cs1 = zynq_slcr_get_mio_pin_status("qspi1_cs");
 +	if ((lower_mio == ZYNQ_QSPI_MIO_NUM_QSPI0) &&
 +	    (upper_mio_cs1 == ZYNQ_QSPI_MIO_NUM_QSPI1_CS))
- 		is_dual = MODE_DUAL_STACKED;
++		is_dual = SF_DUAL_STACKED_FLASH;
 +
 +	upper_mio = zynq_slcr_get_mio_pin_status("qspi1");
 +	if ((lower_mio == ZYNQ_QSPI_MIO_NUM_QSPI0) &&
 +	    (upper_mio_cs1 == ZYNQ_QSPI_MIO_NUM_QSPI1_CS) &&
 +	    (upper_mio == ZYNQ_QSPI_MIO_NUM_QSPI1))
- 		is_dual = MODE_DUAL_PARALLEL;
++		is_dual = SF_DUAL_PARALLEL_FLASH;
 +
 +	return is_dual;
 +}
 +
 +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 +{
 +	/* 1 bus with 2 chipselect */
 +	return bus == 0 && cs < 2;
 +}
 +
 +void spi_cs_activate(struct spi_slave *slave)
 +{
 +	debug("%s: slave 0x%08x\n", __func__, (unsigned)slave);
 +}
 +
 +void spi_cs_deactivate(struct spi_slave *slave)
 +{
 +	debug("%s: slave 0x%08x\n", __func__, (unsigned)slave);
 +}
 +
 +void spi_init()
 +{
 +	debug("%s\n", __func__);
 +}
 +
 +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 +		unsigned int max_hz, unsigned int mode)
 +{
 +	int is_dual;
 +	unsigned long lqspi_frequency;
 +	struct zynq_qspi_slave *qspi;
 +
 +	debug("%s: bus: %d cs: %d max_hz: %d mode: %d\n",
 +	      __func__, bus, cs, max_hz, mode);
 +
 +	if (!spi_cs_is_valid(bus, cs))
 +		return NULL;
 +
 +	is_dual = zynq_qspi_check_is_dual_flash();
 +
- 	if (is_dual == MODE_UNKNOWN) {
++	if (is_dual == -1) {
 +		printf("%s: No QSPI device detected based on MIO settings\n",
 +		       __func__);
 +		return NULL;
 +	}
 +
 +	zynq_qspi_init_hw(is_dual, cs);
 +
 +	qspi = spi_alloc_slave(struct zynq_qspi_slave, bus, cs);
 +	if (!qspi) {
 +		printf("%s: Fail to allocate zynq_qspi_slave\n", __func__);
 +		return NULL;
 +	}
 +
 +	lqspi_frequency = zynq_clk_get_rate(lqspi_clk);
 +	if (!lqspi_frequency) {
 +		debug("Defaulting to 200000000 Hz qspi clk");
 +		qspi->qspi.master.input_clk_hz = 200000000;
 +	} else {
 +		qspi->qspi.master.input_clk_hz = lqspi_frequency;
 +		debug("Qspi clk frequency set to %ld Hz\n", lqspi_frequency);
 +	}
 +
- 	qspi->slave.is_dual = is_dual;
- 	qspi->slave.rd_cmd = READ_CMD_FULL;
- 	qspi->slave.wr_cmd = PAGE_PROGRAM | QUAD_PAGE_PROGRAM;
 +	qspi->qspi.master.speed_hz = qspi->qspi.master.input_clk_hz / 2;
 +	qspi->qspi.max_speed_hz = (max_hz < qspi->qspi.master.speed_hz) ?
 +								max_hz : qspi->qspi.master.speed_hz;
 +	qspi->qspi.master.is_dual = is_dual;
 +	qspi->qspi.mode = mode;
 +	qspi->qspi.chip_select = 0;
 +	qspi->qspi.bits_per_word = 32;
 +	zynq_qspi_setup_transfer(&qspi->qspi, NULL);
 +
 +	return &qspi->slave;
 +}
 +
 +void spi_free_slave(struct spi_slave *slave)
 +{
 +	struct zynq_qspi_slave *qspi;
 +
 +	debug("%s: slave: 0x%08x\n", __func__, (u32)slave);
 +
 +	qspi = to_zynq_qspi_slave(slave);
 +	free(qspi);
 +}
 +
 +int spi_claim_bus(struct spi_slave *slave)
 +{
 +	debug("%s: slave: 0x%08x\n", __func__, (u32)slave);
 +	return 0;
 +}
 +
 +void spi_release_bus(struct spi_slave *slave)
 +{
 +	debug("%s: slave: 0x%08x\n", __func__, (u32)slave);
 +}
 +
 +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 +		void *din, unsigned long flags)
 +{
 +	struct zynq_qspi_slave *qspi;
 +	struct spi_transfer transfer;
 +
 +	debug("%s: slave: 0x%08x bitlen: %d dout: 0x%08x ", __func__,
 +	      (u32)slave, bitlen, (u32)dout);
 +	debug("din: 0x%08x flags: 0x%lx\n", (u32)din, flags);
 +
 +	qspi = (struct zynq_qspi_slave *)slave;
 +	transfer.tx_buf = dout;
 +	transfer.rx_buf = din;
 +	transfer.len = bitlen / 8;
 +
 +	/*
 +	 * Festering sore.
 +	 * Assume that the beginning of a transfer with bits to
 +	 * transmit must contain a device command.
 +	 */
 +	if (dout && flags & SPI_XFER_BEGIN)
 +		qspi->qspi.master.is_inst = 1;
 +	else
 +		qspi->qspi.master.is_inst = 0;
 +
 +	if (flags & SPI_XFER_END)
 +		transfer.cs_change = 1;
 +	else
 +		transfer.cs_change = 0;
 +
- 	if (flags & SPI_FLASH_U_PAGE)
++	if (flags & SPI_XFER_U_PAGE)
 +		qspi->qspi.master.u_page = 1;
 +	else
 +		qspi->qspi.master.u_page = 0;
 +
 +	transfer.delay_usecs = 0;
 +	transfer.bits_per_word = 32;
 +	transfer.speed_hz = qspi->qspi.max_speed_hz;
 +
 +	zynq_qspi_transfer(&qspi->qspi, &transfer);
 +
 +	return 0;
 +}
diff --cc include/configs/microblaze-generic.h
index 65433a46858,aa8d59d6e91..91af2b8325d
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@@ -281,13 -399,18 +281,14 @@@
  
  /* architecture dependent code */
  #define	CONFIG_SYS_USR_EXCEP	/* user exception */
- #define	CONFIG_SYS_HZ	1000
+ 
+ #define	CONFIG_PREBOOT	"echo U-BOOT for ${hostname};setenv preboot;echo"
  
 -#define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" \
 -					"nor0=flash-0\0"\
 -					"mtdparts=mtdparts=flash-0:"\
 -					"256k(u-boot),256k(env),3m(kernel),"\
 -					"1m(romfs),1m(cramfs),-(jffs2)\0"\
 -					"nc=setenv stdout nc;"\
 -					"setenv stdin nc\0" \
 -					"serial=setenv stdout serial;"\
 -					"setenv stdin serial\0"
 +#define CONFIG_ENV_OVERWRITE	/* Allow to overwrite the u-boot environment variables */
 +#define	CONFIG_IPADDR		192.168.0.90
 +#define	CONFIG_SERVERIP		192.168.0.101
 +#define	CONFIG_ETHADDR		00:0a:35:00:92:d4
 +#define CONFIG_BOOTP_SERVERIP
  
  #define CONFIG_CMDLINE_EDITING
  
diff --cc include/configs/zynq-common.h
index 2acf3ee3d43,e7a8e9fb11b..f71016a4857
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@@ -5,51 -7,51 +7,33 @@@
   * SPDX-License-Identifier:	GPL-2.0+
   */
  
- #ifndef __CONFIG_ZYNQ_H
- #define __CONFIG_ZYNQ_H
- 
- /* High Level Configuration Options */
- #define CONFIG_ARMV7 /* CPU */
- #define CONFIG_ZYNQ /* SoC */
+ #ifndef __CONFIG_ZYNQ_COMMON_H
+ #define __CONFIG_ZYNQ_COMMON_H
  
- /* Default environment */
- #define CONFIG_IPADDR	10.10.70.102
- #define CONFIG_SERVERIP	10.10.70.101
+ /* High Level configuration Options */
+ #define CONFIG_ARMV7
+ #define CONFIG_ZYNQ
  
- #define CONFIG_SYS_SDRAM_BASE	0
- #define CONFIG_SYS_SDRAM_SIZE	PHYS_SDRAM_1_SIZE
 -/* CPU clock */
 -#ifndef CONFIG_CPU_FREQ_HZ
 -# define CONFIG_CPU_FREQ_HZ	800000000
 -#endif
 -
+ /* Cache options */
+ #define CONFIG_CMD_CACHE
+ #define CONFIG_SYS_CACHELINE_SIZE	32
  
- /* TEXT BASE defines */
- #if defined(CONFIG_CSE_QSPI) || defined(CONFIG_CSE_NOR)
- # define CONFIG_SYS_TEXT_BASE		0xFFFC4800
- #elif defined(CONFIG_CSE_NAND)
- # define CONFIG_SYS_TEXT_BASE		0x00100000
- #else
- # define CONFIG_SYS_TEXT_BASE		0x04000000
+ #define CONFIG_SYS_L2CACHE_OFF
+ #ifndef CONFIG_SYS_L2CACHE_OFF
 -# define CONFIG_SYS_L2_PL310
 -# define CONFIG_SYS_PL310_BASE		0xf8f02000
++#define CONFIG_SYS_L2_PL310
++#define CONFIG_SYS_PL310_BASE	0xf8f02000
  #endif
  
- /* Total Size of Environment Sector */
- #define CONFIG_ENV_SIZE			(128 << 10)
- 
- /* allow to overwrite serial and ethaddr */
- #define CONFIG_ENV_OVERWRITE
- 
- /* Size of malloc() pool */
- #define CONFIG_SYS_MALLOC_LEN		0x400000
- 
  /* Serial drivers */
 -#define CONFIG_BAUDRATE		115200
 +#define CONFIG_BAUDRATE			115200
- #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 38400, 115200 }
+ /* The following table includes the supported baudrates */
+ #define CONFIG_SYS_BAUDRATE_TABLE  \
+ 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
  
 -/* Zynq Serial driver */
 -#ifdef CONFIG_ZYNQ_SERIAL_UART0
 -# define CONFIG_ZYNQ_SERIAL_BASEADDR0	0xE0000000
 -# define CONFIG_ZYNQ_SERIAL_BAUDRATE0	CONFIG_BAUDRATE
 -# define CONFIG_ZYNQ_SERIAL_CLOCK0	50000000
 -#endif
 -
 -#ifdef CONFIG_ZYNQ_SERIAL_UART1
 -# define CONFIG_ZYNQ_SERIAL_BASEADDR1	0xE0001000
 -# define CONFIG_ZYNQ_SERIAL_BAUDRATE1	CONFIG_BAUDRATE
 -# define CONFIG_ZYNQ_SERIAL_CLOCK1	50000000
 -#endif
 -
  #if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1)
 -# define CONFIG_ZYNQ_SERIAL
 +#define CONFIG_ZYNQ_SERIAL
  #endif
  
- #if defined(CONFIG_CMD_ZYNQ_RSA)
- #define CONFIG_SHA256
- #define CONFIG_CMD_ZYNQ_AES
- #endif
- 
  /* DCC driver */
  #if defined(CONFIG_ZYNQ_DCC)
  # define CONFIG_ARM_DCC
@@@ -64,38 -66,13 +48,15 @@@
  # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  # define CONFIG_PHYLIB
  # define CONFIG_PHY_MARVELL
 +# define CONFIG_SYS_ENET
  #endif
  
- #define CONFIG_SYS_HZ			1000
- 
- /* Miscellaneous configurable options */
- #define CONFIG_SYS_PROMPT		"zynq-uboot> "
- #define CONFIG_SYS_HUSH_PARSER	/* use "hush" command parser */
- #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
- 
- #define CONFIG_CMDLINE_EDITING
- #define CONFIG_AUTO_COMPLETE
- #define CONFIG_SYS_LONGHELP
- #define CONFIG_CLOCKS
- #define CONFIG_CMD_CLK
- #define CONFIG_BOARD_LATE_INIT
- #define CONFIG_SYS_MAXARGS		32
- #define CONFIG_SYS_CBSIZE		2048
- #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
- 					sizeof(CONFIG_SYS_PROMPT) + 16)
- 
- /* Open Firmware flat tree */
- #define CONFIG_OF_LIBFDT
- 
- #include <config_cmd_default.h>
- 
- #ifdef CONFIG_SYS_ENET
- # define CONFIG_CMD_PING
- # define CONFIG_CMD_MII
- #else
- # undef CONFIG_CMD_NET
- # undef CONFIG_CMD_NFS
+ /* SPI */
+ #ifdef CONFIG_ZYNQ_SPI
+ # define CONFIG_SPI_FLASH
+ # define CONFIG_SPI_FLASH_SST
++# define CONFIG_CMD_SPI
+ # define CONFIG_CMD_SF
  #endif
  
  /* NOR */
@@@ -111,63 -87,30 +71,54 @@@
  # define CONFIG_SYS_FLASH_CFI
  # undef CONFIG_SYS_FLASH_EMPTY_INFO
  # define CONFIG_FLASH_CFI_DRIVER
- # undef CONFIG_SYS_FLASH_PROTECTION /* don't use hardware protection */
- /* use buffered writes (20x faster) */
+ # undef CONFIG_SYS_FLASH_PROTECTION
  # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 +# define CONFIG_ZYNQ_M29EW_WB_HACK
  #endif
  
- /* SPI */
- #ifdef CONFIG_ZYNQ_SPI
- # define CONFIG_SPI_FLASH
- # define CONFIG_SPI_FLASH_SST
- # define CONFIG_CMD_SPI
- # define CONFIG_CMD_SF
+ /* MMC */
+ #if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
+ # define CONFIG_MMC
+ # define CONFIG_GENERIC_MMC
+ # define CONFIG_SDHCI
+ # define CONFIG_ZYNQ_SDHCI
+ # define CONFIG_CMD_MMC
+ # define CONFIG_CMD_FAT
+ # define CONFIG_SUPPORT_VFAT
+ # define CONFIG_CMD_EXT2
+ # define CONFIG_DOS_PARTITION
  #endif
  
++
 +/* QSPI */
 +#ifdef CONFIG_ZYNQ_QSPI
 +# define CONFIG_SF_DEFAULT_SPEED	30000000
 +# define CONFIG_SPI_FLASH
 +# define CONFIG_SPI_FLASH_BAR
 +# define CONFIG_SPI_FLASH_SPANSION
 +# define CONFIG_SPI_FLASH_STMICRO
 +# define CONFIG_SPI_FLASH_WINBOND
 +# define CONFIG_CMD_SPI
 +# define CONFIG_CMD_SF
 +#endif
 +
- /* MMC */
- #if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
- # define CONFIG_MMC
- # define CONFIG_GENERIC_MMC
- # define CONFIG_SDHCI
- # define CONFIG_ZYNQ_SDHCI
- # define CONFIG_CMD_MMC
- # define CONFIG_CMD_FAT
- # define CONFIG_SUPPORT_VFAT
- # define CONFIG_CMD_EXT2
- # define CONFIG_DOS_PARTITION
- #endif
- 
 +/* NAND */
 +#ifdef CONFIG_NAND_ZYNQ
 +# define CONFIG_CMD_NAND
 +# define CONFIG_CMD_NAND_LOCK_UNLOCK
 +# define CONFIG_SYS_MAX_NAND_DEVICE 1
 +# define CONFIG_SYS_NAND_SELF_INIT
 +# define CONFIG_SYS_NAND_ONFI_DETECTION
 +# define CONFIG_MTD_DEVICE
 +#endif
 +
  /* I2C */
  #if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1)
  # define CONFIG_CMD_I2C
  # define CONFIG_SYS_I2C
  # define CONFIG_SYS_I2C_ZYNQ
- /* # define CONFIG_SYS_I2C */
 -# define CONFIG_SYS_I2C_ZYNQ_SPEED		100000
 -# define CONFIG_SYS_I2C_ZYNQ_SLAVE		1
 +# define CONFIG_SYS_I2C_ZYNQ_SPEED	100000
 +# define CONFIG_SYS_I2C_ZYNQ_SLAVE	1
  #endif
  
  /* EEPROM */
@@@ -180,150 -123,78 +131,166 @@@
  # define CONFIG_SYS_EEPROM_SIZE			1024 /* Bytes */
  #endif
  
 -#define CONFIG_BOOTP_SERVERIP
 -#define CONFIG_BOOTP_BOOTPATH
 -#define CONFIG_BOOTP_GATEWAY
 -#define CONFIG_BOOTP_HOSTNAME
 -#define CONFIG_BOOTP_MAY_FAIL
 -
+ /* Total Size of Environment Sector */
+ #define CONFIG_ENV_SIZE			(128 << 10)
+ 
+ /* Allow to overwrite serial and ethaddr */
+ #define CONFIG_ENV_OVERWRITE
+ 
+ /* Environment */
  #ifndef CONFIG_ENV_IS_NOWHERE
  # ifndef CONFIG_SYS_NO_FLASH
 +/* Environment in NOR flash */
  #  define CONFIG_ENV_IS_IN_FLASH
 +# elif defined(CONFIG_ZYNQ_QSPI)
 +/* Environment in Serial Flash */
 +#  define CONFIG_ENV_IS_IN_SPI_FLASH
 +# elif defined(CONFIG_NAND_ZYNQ)
 +/* Environment in NAND flash */
 +#  define CONFIG_ENV_IS_IN_NAND
  # elif defined(CONFIG_SYS_NO_FLASH)
  #  define CONFIG_ENV_IS_NOWHERE
  # endif
  
  # define CONFIG_ENV_SECT_SIZE		CONFIG_ENV_SIZE
 -# define CONFIG_ENV_OFFSET		0xE0000
 +# ifndef CONFIG_ENV_OFFSET
 +#  define CONFIG_ENV_OFFSET		0xE0000
 +# endif
- # define CONFIG_CMD_SAVEENV	/* Command to save ENV to Flash */
- #endif
- 
- /* For development/debugging */
- #ifdef DEBUG
- # define CONFIG_CMD_REGINFO
- # define CONFIG_PANIC_HANG
+ # define CONFIG_CMD_SAVEENV
  #endif
  
  /* Default environment */
  #define CONFIG_EXTRA_ENV_SETTINGS	\
 -	"fit_image=fit.itb\0"		\
 -	"load_addr=0x2000000\0"		\
 -	"fit_size=0x800000\0"		\
 -	"flash_off=0x100000\0"		\
 -	"nor_flash_off=0xE2100000\0"	\
 -	"fdt_high=0x20000000\0"		\
 +	"ethaddr=00:0a:35:00:01:22\0"	\
 +	"kernel_image=uImage\0"	\
 +	"ramdisk_image=uramdisk.image.gz\0"	\
 +	"devicetree_image=devicetree.dtb\0"	\
 +	"bitstream_image=system.bit.bin\0"	\
 +	"boot_image=BOOT.bin\0"	\
 +	"loadbit_addr=0x100000\0"	\
 +	"loadbootenv_addr=0x2000000\0" \
 +	"kernel_size=0x500000\0"	\
 +	"devicetree_size=0x20000\0"	\
 +	"ramdisk_size=0x5E0000\0"	\
 +	"boot_size=0xF00000\0"	\
 +	"fdt_high=0x20000000\0"	\
  	"initrd_high=0x20000000\0"	\
 -	"norboot=echo Copying FIT from NOR flash to RAM... && " \
 -		"cp.b ${nor_flash_off} ${load_addr} ${fit_size} && " \
 -		"bootm ${load_addr}\0" \
 -	"sdboot=echo Copying FIT from SD to RAM... && " \
 -		"fatload mmc 0 ${load_addr} ${fit_image} && " \
 -		"bootm ${load_addr}\0" \
 -	"jtagboot=echo TFTPing FIT to RAM... && " \
 -		"tftp ${load_addr} ${fit_image} && " \
 -		"bootm ${load_addr}\0"
 +	"bootenv=uEnv.txt\0" \
 +	"loadbootenv=fatload mmc 0 ${loadbootenv_addr} ${bootenv}\0" \
 +	"importbootenv=echo Importing environment from SD ...; " \
 +		"env import -t ${loadbootenv_addr} $filesize\0" \
 +	"mmc_loadbit_fat=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \
 +		"mmcinfo && " \
 +		"fatload mmc 0 ${loadbit_addr} ${bitstream_image} && " \
 +		"fpga load 0 ${loadbit_addr} ${filesize}\0" \
 +	"norboot=echo Copying Linux from NOR flash to RAM... && " \
 +		"cp.b 0xE2100000 0x3000000 ${kernel_size} && " \
 +		"cp.b 0xE2600000 0x2A00000 ${devicetree_size} && " \
 +		"echo Copying ramdisk... && " \
 +		"cp.b 0xE2620000 0x2000000 ${ramdisk_size} && " \
 +		"bootm 0x3000000 0x2000000 0x2A00000\0" \
 +	"qspiboot=echo Copying Linux from QSPI flash to RAM... && " \
 +		"sf probe 0 0 0 && " \
 +		"sf read 0x3000000 0x100000 ${kernel_size} && " \
 +		"sf read 0x2A00000 0x600000 ${devicetree_size} && " \
 +		"echo Copying ramdisk... && " \
 +		"sf read 0x2000000 0x620000 ${ramdisk_size} && " \
 +		"bootm 0x3000000 0x2000000 0x2A00000\0" \
 +	"uenvboot=" \
 +		"if run loadbootenv; then " \
 +			"echo Loaded environment from ${bootenv}; " \
 +			"run importbootenv; " \
 +		"fi; " \
 +		"if test -n $uenvcmd; then " \
 +			"echo Running uenvcmd ...; " \
 +			"run uenvcmd; " \
 +		"fi\0" \
 +	"sdboot=if mmcinfo; then " \
 +			"run uenvboot; " \
 +			"echo Copying Linux from SD to RAM... && " \
 +			"fatload mmc 0 0x3000000 ${kernel_image} && " \
 +			"fatload mmc 0 0x2A00000 ${devicetree_image} && " \
 +			"fatload mmc 0 0x2000000 ${ramdisk_image} && " \
 +			"bootm 0x3000000 0x2000000 0x2A00000; " \
 +		"fi\0" \
 +	"nandboot=echo Copying Linux from NAND flash to RAM... && " \
 +		"nand read 0x3000000 0x100000 ${kernel_size} && " \
 +		"nand read 0x2A00000 0x600000 ${devicetree_size} && " \
 +		"echo Copying ramdisk... && " \
 +		"nand read 0x2000000 0x620000 ${ramdisk_size} && " \
 +		"bootm 0x3000000 0x2000000 0x2A00000\0" \
 +	"jtagboot=echo TFTPing Linux to RAM... && " \
 +		"tftp 0x3000000 ${kernel_image} && " \
 +		"tftp 0x2A00000 ${devicetree_image} && " \
 +		"tftp 0x2000000 ${ramdisk_image} && " \
 +		"bootm 0x3000000 0x2000000 0x2A00000\0" \
 +	"rsa_norboot=echo Copying Image from NOR flash to RAM... && " \
 +		"cp.b 0xE2100000 0x100000 ${boot_size} && " \
 +		"zynqrsa 0x100000 && " \
 +		"bootm 0x3000000 0x2000000 0x2A00000\0" \
 +	"rsa_nandboot=echo Copying Image from NAND flash to RAM... && " \
 +		"nand read 0x100000 0x0 ${boot_size} && " \
 +		"zynqrsa 0x100000 && " \
 +		"bootm 0x3000000 0x2000000 0x2A00000\0" \
 +	"rsa_qspiboot=echo Copying Image from QSPI flash to RAM... && " \
 +		"sf probe 0 0 0 && " \
 +		"sf read 0x100000 0x0 ${boot_size} && " \
 +		"zynqrsa 0x100000 && " \
 +		"bootm 0x3000000 0x2000000 0x2A00000\0" \
 +	"rsa_sdboot=echo Copying Image from SD to RAM... && " \
 +		"fatload mmc 0 0x100000 ${boot_image} && " \
 +		"zynqrsa 0x100000 && " \
 +		"bootm 0x3000000 0x2000000 0x2A00000\0" \
 +	"rsa_jtagboot=echo TFTPing Image to RAM... && " \
 +		"tftp 0x100000 ${boot_image} && " \
 +		"zynqrsa 0x100000 && " \
 +		"bootm 0x3000000 0x2000000 0x2A00000\0"
 +
++/* Default environment */
++#define CONFIG_IPADDR	10.10.70.102
++#define CONFIG_SERVERIP	10.10.70.101
++
 +/* default boot is according to the bootmode switch settings */
 +#if defined(CONFIG_CMD_ZYNQ_RSA)
 +#define CONFIG_BOOTCOMMAND		"run rsa_$modeboot"
 +#else
  #define CONFIG_BOOTCOMMAND		"run $modeboot"
 +#endif
  #define CONFIG_BOOTDELAY		3 /* -1 to Disable autoboot */
  #define CONFIG_SYS_LOAD_ADDR		0 /* default? */
  
- #define CONFIG_CMD_CACHE
+ /* Miscellaneous configurable options */
+ #define CONFIG_SYS_PROMPT		"zynq-uboot> "
+ #define CONFIG_SYS_HUSH_PARSER
  
- /* Keep L2 Cache Disabled */
- #define CONFIG_SYS_L2CACHE_OFF
- #define CONFIG_SYS_CACHELINE_SIZE	32
+ #define CONFIG_CMDLINE_EDITING
+ #define CONFIG_AUTO_COMPLETE
+ #define CONFIG_BOARD_LATE_INIT
+ #define CONFIG_SYS_LONGHELP
 -#define CONFIG_SYS_MAXARGS		15 /* max number of command args */
 -#define CONFIG_SYS_CBSIZE		256 /* Console I/O Buffer Size */
++#define CONFIG_SYS_MAXARGS		32 /* max number of command args */
++#define CONFIG_SYS_CBSIZE		2048 /* Console I/O Buffer Size */
+ #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+ 					sizeof(CONFIG_SYS_PROMPT) + 16)
  
- #ifndef CONFIG_SYS_L2CACHE_OFF
- #define CONFIG_SYS_L2_PL310
- #define CONFIG_SYS_PL310_BASE	0xf8f02000
+ /* Physical Memory map */
 -#define CONFIG_SYS_TEXT_BASE		0x4000000
++#if defined(CONFIG_CSE_QSPI) || defined(CONFIG_CSE_NOR)
++# define CONFIG_SYS_TEXT_BASE		0xFFFC4800
++#elif defined(CONFIG_CSE_NAND)
++# define CONFIG_SYS_TEXT_BASE		0x00100000
++#else
++# define CONFIG_SYS_TEXT_BASE		0x4000000
 +#endif
  
- /* Physical Memory map */
  #define CONFIG_NR_DRAM_BANKS		1
- #define PHYS_SDRAM_1			0
+ #define CONFIG_SYS_SDRAM_BASE		0
  
- #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
- #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
- 					PHYS_SDRAM_1_SIZE - (16 * 1024 * 1024))
+ #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+ #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)
+ 
+ #define CONFIG_SYS_MALLOC_LEN		0x400000
 -#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SDRAM_BASE
 -#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
 +
 +#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
 +#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
  #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
  					CONFIG_SYS_INIT_RAM_SIZE - \
  					GENERATED_GBL_DATA_SIZE)
@@@ -334,10 -205,22 +301,13 @@@
  #define CONFIG_FPGA_ZYNQPL
  #define CONFIG_CMD_FPGA
  
+ /* Open Firmware flat tree */
+ #define CONFIG_OF_LIBFDT
+ 
  /* FIT support */
- #define CONFIG_FIT		1
+ #define CONFIG_FIT
  #define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
  
 -/* FDT support */
 -#define CONFIG_OF_CONTROL
 -#define CONFIG_OF_SEPARATE
 -#define CONFIG_DISPLAY_BOARDINFO_LATE
 -
 -/* RSA support */
 -#define CONFIG_FIT_SIGNATURE
 -#define CONFIG_RSA
 -
  /* Boot FreeBSD/vxWorks from an ELF image */
  #if defined(CONFIG_ZYNQ_BOOT_FREEBSD)
  # define CONFIG_API
@@@ -345,7 -228,11 +315,35 @@@
  # define CONFIG_SYS_MMC_MAX_DEVICE	1
  #endif
  
 -/* Commands */
+ #include <config_cmd_default.h>
+ 
 -#define CONFIG_CMD_PING
 -#define CONFIG_CMD_DHCP
 -#define CONFIG_CMD_MII
++#ifdef CONFIG_SYS_ENET
++# define CONFIG_CMD_PING
++# define CONFIG_CMD_DHCP
++# define CONFIG_CMD_MII
++#else
++# undef CONFIG_CMD_NET
++# undef CONFIG_CMD_NFS
++#endif
++
++#define CONFIG_CLOCKS
++#define CONFIG_CMD_CLK
++
++#if defined(CONFIG_CMD_ZYNQ_RSA)
++#define CONFIG_RSA
++#define CONFIG_SHA256
++#define CONFIG_CMD_ZYNQ_AES
++#endif
++
 +#define CONFIG_CMD_BOOTZ
 +#undef CONFIG_BOOTM_NETBSD
 +
- #endif /* __CONFIG_ZYNQ_H */
++#define CONFIG_SYS_HZ			1000
++
++/* For development/debugging */
++#ifdef DEBUG
++# define CONFIG_CMD_REGINFO
++# define CONFIG_PANIC_HANG
++#endif
+ 
+ #endif /* __CONFIG_ZYNQ_COMMON_H */
diff --cc include/configs/zynq_afx.h
index b677585dab7,00000000000..dd211135699
mode 100644,000000..100644
--- a/include/configs/zynq_afx.h
+++ b/include/configs/zynq_afx.h
@@@ -1,28 -1,0 +1,28 @@@
 +/*
 + * (C) Copyright 2012 Xilinx
 + *
 + * Configuration settings for the Xilinx Zynq AFX board.
-  * See zynq_common.h for Zynq common configs
++ * See zynq-common.h for Zynq common configs
 + *
 + * SPDX-License-Identifier:	GPL-2.0+
 + */
 +
 +#ifndef __CONFIG_ZYNQ_AFX_H
 +#define __CONFIG_ZYNQ_AFX_H
 +
- #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
++#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
 +
 +#define CONFIG_ZYNQ_SERIAL_UART1
 +
 +#define CONFIG_SYS_NO_FLASH
 +#if defined(CONFIG_AFX_NOR)
 +# undef CONFIG_SYS_NO_FLASH
 +#elif defined(CONFIG_AFX_QSPI)
 +# define CONFIG_ZYNQ_QSPI
 +#elif defined(CONFIG_AFX_NAND)
 +# define CONFIG_NAND_ZYNQ
 +#endif
 +
- #include <configs/zynq_common.h>
++#include <configs/zynq-common.h>
 +
 +#endif /* __CONFIG_ZYNQ_AFX_H */
diff --cc include/configs/zynq_cc108.h
index 46deaae35ad,00000000000..f5326e37eef
mode 100644,000000..100644
--- a/include/configs/zynq_cc108.h
+++ b/include/configs/zynq_cc108.h
@@@ -1,42 -1,0 +1,42 @@@
 +/*
 + * (C) Copyright 2013 Xilinx
 + *
 + * Configuration settings for the Xilinx Zynq CC108 boards
-  * See zynq_common.h for Zynq common configs
++ * See zynq-common.h for Zynq common configs
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 of
 + * the License, or (at your option) any later version.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program; if not, write to the Free Software
 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 + * MA 02111-1307 USA
 + */
 +
 +#ifndef __CONFIG_ZYNQ_CC108_H
 +#define __CONFIG_ZYNQ_CC108_H
 +
- #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
++#define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024)
 +
 +/*
 + * UART is connected to EMIO, making it very likely that this board uses a
 + * boot.bin which includes a bitstream, whose file size  exceeds the default
 + * env offset. Hence the env offset is moved to the last MB of the QSPI.
 + */
 +#define CONFIG_ENV_OFFSET	0xF00000
 +
 +#define CONFIG_ZYNQ_SERIAL_UART1
 +#define CONFIG_ZYNQ_GEM0
 +#define CONFIG_ZYNQ_GEM_PHY_ADDR0	7
 +
 +#define CONFIG_SYS_NO_FLASH
 +
 +#define CONFIG_ZYNQ_SDHCI1
 +#define CONFIG_ZYNQ_QSPI
 +#define CONFIG_ZYNQ_BOOT_FREEBSD
 +
- #include <configs/zynq_common.h>
++#include <configs/zynq-common.h>
 +
 +#endif /* __CONFIG_ZYNQ_CC108_H */
diff --cc include/configs/zynq_cse.h
index e85fc017acb,00000000000..d4bfc5c58bf
mode 100644,000000..100644
--- a/include/configs/zynq_cse.h
+++ b/include/configs/zynq_cse.h
@@@ -1,80 -1,0 +1,80 @@@
 +/*
 + * (C) Copyright 2013 Xilinx.
 + *
 + * Configuration settings for the Xilinx Zynq CSE board.
-  * See zynq_common.h for Zynq common configs
++ * See zynq-common.h for Zynq common configs
 + *
 + * SPDX-License-Identifier:     GPL-2.0+
 + */
 +
 +#ifndef __CONFIG_ZYNQ_CSE_H
 +#define __CONFIG_ZYNQ_CSE_H
 +
 +#define CONFIG_SYS_NO_FLASH
 +#define CONFIG_ZYNQ_DCC
 +#define _CONFIG_CMD_DEFAULT_H
 +#define CONFIG_SKIP_LOWLEVEL_INIT
 +#define CONFIG_ENV_IS_NOWHERE
 +#define CONFIG_SYS_DCACHE_OFF
 +
 +#if defined(CONFIG_CSE_QSPI)
 +# define CONFIG_ZYNQ_QSPI
 +
 +#elif defined(CONFIG_CSE_NAND)
 +# define CONFIG_NAND_ZYNQ
 +
 +#elif defined(CONFIG_CSE_NOR)
 +#undef CONFIG_SYS_NO_FLASH
 +
 +#endif
 +
- #include <configs/zynq_common.h>
++#include <configs/zynq-common.h>
 +
 +/* Undef unneeded configs */
 +#undef CONFIG_SYS_SDRAM_BASE
 +#undef CONFIG_OF_LIBFDT
 +#undef CONFIG_EXTRA_ENV_SETTINGS
 +#undef CONFIG_BOARD_LATE_INIT
 +#undef CONFIG_FPGA
 +#undef CONFIG_FPGA_XILINX
 +#undef CONFIG_FPGA_ZYNQPL
 +#undef CONFIG_CMD_FPGA
 +#undef CONFIG_FIT
 +#undef CONFIG_FIT_VERBOSE
 +#undef CONFIG_CMD_GO
 +#undef CONFIG_CMD_BOOTM
 +#undef CONFIG_CMD_BOOTZ
 +#undef CONFIG_BOOTCOMMAND
 +#undef CONFIG_SYS_HUSH_PARSER
 +#undef CONFIG_SYS_PROMPT_HUSH_PS2
 +#undef CONFIG_BOOTDELAY
 +#undef CONFIG_SYS_MALLOC_LEN
 +#undef CONFIG_ENV_SIZE
 +#undef CONFIG_CMDLINE_EDITING
 +#undef CONFIG_AUTO_COMPLETE
 +#undef CONFIG_ZLIB
 +#undef CONFIG_GZIP
 +
 +/* Define needed configs */
 +#define CONFIG_CMD_MEMORY
 +#define CONFIG_BOOTDELAY	-1 /* -1 to Disable autoboot */
 +#define CONFIG_SYS_MALLOC_LEN	0x4000
 +
 +#if defined(CONFIG_CSE_QSPI)
- # define PHYS_SDRAM_1_SIZE		(256 * 1024)
++# define CONFIG_SYS_SDRAM_SIZE		(256 * 1024)
 +# define CONFIG_SYS_SDRAM_BASE		0xFFFD0000
 +# define CONFIG_ENV_SIZE		1400
 +
 +#elif defined(CONFIG_CSE_NAND)
- # define PHYS_SDRAM_1_SIZE		(4 * 1024 * 1024)
++# define CONFIG_SYS_SDRAM_SIZE		(4 * 1024 * 1024)
 +# define CONFIG_SYS_SDRAM_BASE		0
 +# define CONFIG_ENV_SIZE		0x10000
 +
 +#elif defined(CONFIG_CSE_NOR)
- # define PHYS_SDRAM_1_SIZE		(256 * 1024)
++# define CONFIG_SYS_SDRAM_SIZE		(256 * 1024)
 +# define CONFIG_SYS_SDRAM_BASE		0xFFFD0000
 +# define CONFIG_ENV_SIZE		1400
 +
 +#endif
 +
 +#endif /* __CONFIG_ZYNQ_CSE_H */
diff --cc include/configs/zynq_zc70x.h
index 206ffd35518,673660e6596..9bc995d0c8d
--- a/include/configs/zynq_zc70x.h
+++ b/include/configs/zynq_zc70x.h
@@@ -1,8 -1,8 +1,8 @@@
  /*
-  * (C) Copyright 2012 Xilinx
+  * (C) Copyright 2013 Xilinx, Inc.
   *
   * Configuration settings for the Xilinx Zynq ZC702 and ZC706 boards
-- * See zynq_common.h for Zynq common configs
++ * See zynq-common.h for Zynq common configs
   *
   * SPDX-License-Identifier:	GPL-2.0+
   */
diff --cc include/configs/zynq_zc770.h
index 1df5b7a7877,8aa96e7121b..d17217c7e2c
--- a/include/configs/zynq_zc770.h
+++ b/include/configs/zynq_zc770.h
@@@ -19,12 -19,9 +19,14 @@@
  # define CONFIG_ZYNQ_GEM0
  # define CONFIG_ZYNQ_GEM_PHY_ADDR0	7
  # define CONFIG_ZYNQ_SDHCI0
 -# define CONFIG_ZYNQ_SPI
 +# define CONFIG_ZYNQ_QSPI
+ # define CONFIG_DEFAULT_DEVICE_TREE	zynq-zc770-xm010
  
 +#elif defined(CONFIG_ZC770_XM011)
 +# define CONFIG_ZYNQ_SERIAL_UART1
 +# define CONFIG_NAND_ZYNQ
++# define CONFIG_DEFAULT_DEVICE_TREE	zynq-zc770-xm011
 +
  #elif defined(CONFIG_ZC770_XM012)
  # define CONFIG_ZYNQ_SERIAL_UART1
  # undef CONFIG_SYS_NO_FLASH
@@@ -33,7 -31,7 +36,8 @@@
  # define CONFIG_ZYNQ_SERIAL_UART0
  # define CONFIG_ZYNQ_GEM1
  # define CONFIG_ZYNQ_GEM_PHY_ADDR1	7
 +# define CONFIG_ZYNQ_QSPI
+ # define CONFIG_DEFAULT_DEVICE_TREE	zynq-zc770-xm013
  
  #else
  # define CONFIG_ZYNQ_SERIAL_UART0
diff --cc include/configs/zynq_zed.h
index 71a1beffb95,412dede5331..2399c8f67e7
--- a/include/configs/zynq_zed.h
+++ b/include/configs/zynq_zed.h
@@@ -1,8 -1,8 +1,8 @@@
  /*
-  * (C) Copyright 2012 Xilinx
+  * (C) Copyright 2013 Xilinx, Inc.
   *
   * Configuration for Zynq Evaluation and Development Board - ZedBoard
-- * See zynq_common.h for Zynq common configs
++ * See zynq-common.h for Zynq common configs
   *
   * SPDX-License-Identifier:	GPL-2.0+
   */
@@@ -19,9 -19,9 +19,11 @@@
  #define CONFIG_SYS_NO_FLASH
  
  #define CONFIG_ZYNQ_SDHCI0
 +#define CONFIG_ZYNQ_QSPI
++
  #define CONFIG_ZYNQ_BOOT_FREEBSD
+ #define CONFIG_DEFAULT_DEVICE_TREE	zynq-zed
  
- #include <configs/zynq_common.h>
+ #include <configs/zynq-common.h>
  
  #endif /* __CONFIG_ZYNQ_ZED_H */
diff --cc lib/rsa/Makefile
index 27c3bc3f9cd,164ab399645..275c5fd2c7d
--- a/lib/rsa/Makefile
+++ b/lib/rsa/Makefile
@@@ -7,28 -7,4 +7,5 @@@
  # SPDX-License-Identifier:	GPL-2.0+
  #
  
- include $(TOPDIR)/config.mk
- 
- LIB	= $(obj)librsa.o
- 
- ifdef CONFIG_FIT_SIGNATURE
- COBJS-$(CONFIG_RSA) += rsa-verify.o
- endif
- 
- COBJS-$(CONFIG_CMD_ZYNQ_RSA) += rsa-verify.o
- 
- COBJS	:= $(sort $(COBJS-y))
- SRCS	:= $(COBJS:.o=.c)
- OBJS	:= $(addprefix $(obj),$(COBJS))
- 
- $(LIB):	$(obj).depend $(OBJS)
- 	$(call cmd_link_o_target, $(OBJS))
- 
- #########################################################################
- 
- # defines $(obj).depend target
- include $(SRCTREE)/rules.mk
- 
- sinclude $(obj).depend
- 
- #########################################################################
+ obj-$(CONFIG_FIT_SIGNATURE) += rsa-verify.o
++obj-$(CONFIG_CMD_ZYNQ_RSA) += rsa-verify.o