From: Matt Roper Date: Fri, 6 Feb 2026 18:36:05 +0000 (-0300) Subject: drm/xe/xe3p_lpg: Extend 'group ID' mask size X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=60fcdf645c47699c04e421382d5b36130b476262;p=thirdparty%2Flinux.git drm/xe/xe3p_lpg: Extend 'group ID' mask size Xe3p_LPG extends the 'group ID' register mask by one bit. Since the new upper bit (12) was unused on previous platforms, we can safely extend the existing mask size without worrying about adding conditional version checks to the register programming. Bspec: 67175 Signed-off-by: Matt Roper Reviewed-by: Dnyaneshwar Bhadane Link: https://patch.msgid.link/20260206-nvl-p-upstreaming-v3-9-636e1ad32688@intel.com Signed-off-by: Gustavo Sousa --- diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index d593331202e8f..ff77523e823ed 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -58,7 +58,7 @@ #define MCR_SLICE(slice) REG_FIELD_PREP(MCR_SLICE_MASK, slice) #define MCR_SUBSLICE_MASK REG_GENMASK(26, 24) #define MCR_SUBSLICE(subslice) REG_FIELD_PREP(MCR_SUBSLICE_MASK, subslice) -#define MTL_MCR_GROUPID REG_GENMASK(11, 8) +#define MTL_MCR_GROUPID REG_GENMASK(12, 8) #define MTL_MCR_INSTANCEID REG_GENMASK(3, 0) #define PS_INVOCATION_COUNT XE_REG(0x2348)