From: Greg Kroah-Hartman Date: Thu, 31 Aug 2023 10:36:15 +0000 (+0200) Subject: 4.14-stable patches X-Git-Tag: v6.5.1~15 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=62431bf7a29042ef436a72e1740f39bef92375bb;p=thirdparty%2Fkernel%2Fstable-queue.git 4.14-stable patches added patches: revert-arm-ep93xx-fix-missing-prototype-warnings.patch revert-mips-alchemy-fix-dbdma2.patch --- diff --git a/queue-4.14/revert-arm-ep93xx-fix-missing-prototype-warnings.patch b/queue-4.14/revert-arm-ep93xx-fix-missing-prototype-warnings.patch new file mode 100644 index 00000000000..acb5a624cb4 --- /dev/null +++ b/queue-4.14/revert-arm-ep93xx-fix-missing-prototype-warnings.patch @@ -0,0 +1,41 @@ +From 44dd0c7e02bab3b1f9d8f64b4271e5837b0e7839 Mon Sep 17 00:00:00 2001 +From: Greg Kroah-Hartman +Date: Thu, 31 Aug 2023 12:34:09 +0200 +Subject: Revert "ARM: ep93xx: fix missing-prototype warnings" + +From: Greg Kroah-Hartman + +This reverts commit 2e50d55578b05664b11538f0a280541c100caefe which is +commit 419013740ea1e4343d8ade535d999f59fa28e460 upstream. + +It breaks the build, so should be reverted. + +Reported-by: Guenter Roeck +Link: https://lore.kernel.org/r/98dbc981-56fa-4919-afcc-fdf63e0a1c53@roeck-us.net +Cc: Alexander Sverdlin +Cc: Arnd Bergmann +Cc: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm/mach-ep93xx/timer-ep93xx.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/arch/arm/mach-ep93xx/timer-ep93xx.c ++++ b/arch/arm/mach-ep93xx/timer-ep93xx.c +@@ -9,7 +9,6 @@ + #include + #include + #include "soc.h" +-#include "platform.h" + + /************************************************************************* + * Timer handling for EP93xx +@@ -61,7 +60,7 @@ static u64 notrace ep93xx_read_sched_clo + return ret; + } + +-static u64 ep93xx_clocksource_read(struct clocksource *c) ++u64 ep93xx_clocksource_read(struct clocksource *c) + { + u64 ret; + diff --git a/queue-4.14/revert-mips-alchemy-fix-dbdma2.patch b/queue-4.14/revert-mips-alchemy-fix-dbdma2.patch new file mode 100644 index 00000000000..baf1e6e1184 --- /dev/null +++ b/queue-4.14/revert-mips-alchemy-fix-dbdma2.patch @@ -0,0 +1,81 @@ +From 1a4039bdcf972a7d2e469bb1a5ea616c4c2216fb Mon Sep 17 00:00:00 2001 +From: Greg Kroah-Hartman +Date: Thu, 31 Aug 2023 12:30:23 +0200 +Subject: Revert "MIPS: Alchemy: fix dbdma2" + +From: Greg Kroah-Hartman + +This reverts commit 10130470bb0003b784f4656cc3ef2b9dc396ebdd which is +commit 2d645604f69f3a772d58ead702f9a8e84ab2b342 upstream. + +It breaks the build, so should be dropped. + +Reported-by: Guenter Roeck +Link: https://lore.kernel.org/r/5b30ff73-46cb-1d1e-3823-f175dbfbd91b@roeck-us.net +Cc: Thomas Bogendoerfer +Cc: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + arch/mips/alchemy/common/dbdma.c | 27 ++++++++++++--------------- + 1 file changed, 12 insertions(+), 15 deletions(-) + +--- a/arch/mips/alchemy/common/dbdma.c ++++ b/arch/mips/alchemy/common/dbdma.c +@@ -30,7 +30,6 @@ + * + */ + +-#include /* for dma_default_coherent */ + #include + #include + #include +@@ -624,18 +623,17 @@ u32 au1xxx_dbdma_put_source(u32 chanid, + dp->dscr_cmd0 &= ~DSCR_CMD0_IE; + + /* +- * There is an erratum on certain Au1200/Au1550 revisions that could +- * result in "stale" data being DMA'ed. It has to do with the snoop +- * logic on the cache eviction buffer. dma_default_coherent is set +- * to false on these parts. ++ * There is an errata on the Au1200/Au1550 parts that could result ++ * in "stale" data being DMA'ed. It has to do with the snoop logic on ++ * the cache eviction buffer. DMA_NONCOHERENT is on by default for ++ * these parts. If it is fixed in the future, these dma_cache_inv will ++ * just be nothing more than empty macros. See io.h. + */ +- if (!dma_default_coherent) +- dma_cache_wback_inv(KSEG0ADDR(buf), nbytes); ++ dma_cache_wback_inv((unsigned long)buf, nbytes); + dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ + wmb(); /* drain writebuffer */ + dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); + ctp->chan_ptr->ddma_dbell = 0; +- wmb(); /* force doorbell write out to dma engine */ + + /* Get next descriptor pointer. */ + ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); +@@ -687,18 +685,17 @@ u32 au1xxx_dbdma_put_dest(u32 chanid, dm + dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1); + #endif + /* +- * There is an erratum on certain Au1200/Au1550 revisions that could +- * result in "stale" data being DMA'ed. It has to do with the snoop +- * logic on the cache eviction buffer. dma_default_coherent is set +- * to false on these parts. ++ * There is an errata on the Au1200/Au1550 parts that could result in ++ * "stale" data being DMA'ed. It has to do with the snoop logic on the ++ * cache eviction buffer. DMA_NONCOHERENT is on by default for these ++ * parts. If it is fixed in the future, these dma_cache_inv will just ++ * be nothing more than empty macros. See io.h. + */ +- if (!dma_default_coherent) +- dma_cache_inv(KSEG0ADDR(buf), nbytes); ++ dma_cache_inv((unsigned long)buf, nbytes); + dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ + wmb(); /* drain writebuffer */ + dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); + ctp->chan_ptr->ddma_dbell = 0; +- wmb(); /* force doorbell write out to dma engine */ + + /* Get next descriptor pointer. */ + ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); diff --git a/queue-4.14/series b/queue-4.14/series index e69de29bb2d..b679a7390b2 100644 --- a/queue-4.14/series +++ b/queue-4.14/series @@ -0,0 +1,2 @@ +revert-mips-alchemy-fix-dbdma2.patch +revert-arm-ep93xx-fix-missing-prototype-warnings.patch