From: Greg Kroah-Hartman Date: Wed, 19 Jun 2024 07:04:41 +0000 (+0200) Subject: 6.1-stable patches X-Git-Tag: v6.1.95~66 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=643eef590c59d532f396d19a9e179dc1392a7dd1;p=thirdparty%2Fkernel%2Fstable-queue.git 6.1-stable patches added patches: drm-i915-dpt-make-dpt-object-unshrinkable.patch drm-i915-gt-disarm-breadcrumbs-if-engines-are-already-idle.patch intel_th-pci-add-granite-rapids-soc-support.patch intel_th-pci-add-granite-rapids-support.patch intel_th-pci-add-lunar-lake-support.patch intel_th-pci-add-meteor-lake-s-support.patch intel_th-pci-add-sapphire-rapids-soc-support.patch riscv-rewrite-__kernel_map_pages-to-fix-sleeping-in-invalid-context.patch --- diff --git a/queue-6.1/drm-i915-dpt-make-dpt-object-unshrinkable.patch b/queue-6.1/drm-i915-dpt-make-dpt-object-unshrinkable.patch new file mode 100644 index 00000000000..4049dea86ad --- /dev/null +++ b/queue-6.1/drm-i915-dpt-make-dpt-object-unshrinkable.patch @@ -0,0 +1,44 @@ +From 43e2b37e2ab660c3565d4cff27922bc70e79c3f1 Mon Sep 17 00:00:00 2001 +From: Vidya Srinivas +Date: Mon, 20 May 2024 22:26:34 +0530 +Subject: drm/i915/dpt: Make DPT object unshrinkable +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Vidya Srinivas + +commit 43e2b37e2ab660c3565d4cff27922bc70e79c3f1 upstream. + +In some scenarios, the DPT object gets shrunk but +the actual framebuffer did not and thus its still +there on the DPT's vm->bound_list. Then it tries to +rewrite the PTEs via a stale CPU mapping. This causes panic. + +Cc: stable@vger.kernel.org +Reported-by: Shawn Lee +Fixes: 0dc987b699ce ("drm/i915/display: Add smem fallback allocation for dpt") +Signed-off-by: Vidya Srinivas +[vsyrjala: Add TODO comment] +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20240520165634.1162470-1-vidya.srinivas@intel.com +(cherry picked from commit 51064d471c53dcc8eddd2333c3f1c1d9131ba36c) +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/gem/i915_gem_object.h | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h ++++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h +@@ -295,7 +295,9 @@ bool i915_gem_object_has_iomem(const str + static inline bool + i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj) + { +- return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE); ++ /* TODO: make DPT shrinkable when it has no bound vmas */ ++ return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE) && ++ !obj->is_dpt; + } + + static inline bool diff --git a/queue-6.1/drm-i915-gt-disarm-breadcrumbs-if-engines-are-already-idle.patch b/queue-6.1/drm-i915-gt-disarm-breadcrumbs-if-engines-are-already-idle.patch new file mode 100644 index 00000000000..9b08480f4e4 --- /dev/null +++ b/queue-6.1/drm-i915-gt-disarm-breadcrumbs-if-engines-are-already-idle.patch @@ -0,0 +1,107 @@ +From 70cb9188ffc75e643debf292fcddff36c9dbd4ae Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Tue, 23 Apr 2024 18:23:10 +0200 +Subject: drm/i915/gt: Disarm breadcrumbs if engines are already idle + +From: Chris Wilson + +commit 70cb9188ffc75e643debf292fcddff36c9dbd4ae upstream. + +The breadcrumbs use a GT wakeref for guarding the interrupt, but are +disarmed during release of the engine wakeref. This leaves a hole where +we may attach a breadcrumb just as the engine is parking (after it has +parked its breadcrumbs), execute the irq worker with some signalers still +attached, but never be woken again. + +That issue manifests itself in CI with IGT runner timeouts while tests +are waiting indefinitely for release of all GT wakerefs. + +<6> [209.151778] i915: Running live_engine_pm_selftests/live_engine_busy_stats +<7> [209.231628] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling PW_5 +<7> [209.231816] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling PW_4 +<7> [209.231944] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling PW_3 +<7> [209.232056] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling PW_2 +<7> [209.232166] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling DC_off +<7> [209.232270] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6 +<7> [209.232368] i915 0000:00:02.0: [drm:gen9_set_dc_state.part.0 [i915]] Setting DC state from 00 to 02 +<4> [299.356116] [IGT] Inactivity timeout exceeded. Killing the current test with SIGQUIT. +... +<6> [299.356526] sysrq: Show State +... +<6> [299.373964] task:i915_selftest state:D stack:11784 pid:5578 tgid:5578 ppid:873 flags:0x00004002 +<6> [299.373967] Call Trace: +<6> [299.373968] +<6> [299.373970] __schedule+0x3bb/0xda0 +<6> [299.373974] schedule+0x41/0x110 +<6> [299.373976] intel_wakeref_wait_for_idle+0x82/0x100 [i915] +<6> [299.374083] ? __pfx_var_wake_function+0x10/0x10 +<6> [299.374087] live_engine_busy_stats+0x9b/0x500 [i915] +<6> [299.374173] __i915_subtests+0xbe/0x240 [i915] +<6> [299.374277] ? __pfx___intel_gt_live_setup+0x10/0x10 [i915] +<6> [299.374369] ? __pfx___intel_gt_live_teardown+0x10/0x10 [i915] +<6> [299.374456] intel_engine_live_selftests+0x1c/0x30 [i915] +<6> [299.374547] __run_selftests+0xbb/0x190 [i915] +<6> [299.374635] i915_live_selftests+0x4b/0x90 [i915] +<6> [299.374717] i915_pci_probe+0x10d/0x210 [i915] + +At the end of the interrupt worker, if there are no more engines awake, +disarm the breadcrumb and go to sleep. + +Fixes: 9d5612ca165a ("drm/i915/gt: Defer enabling the breadcrumb interrupt to after submission") +Closes: https://gitlab.freedesktop.org/drm/intel/issues/10026 +Signed-off-by: Chris Wilson +Cc: Andrzej Hajda +Cc: # v5.12+ +Signed-off-by: Janusz Krzysztofik +Acked-by: Nirmoy Das +Reviewed-by: Andrzej Hajda +Reviewed-by: Andi Shyti +Signed-off-by: Andi Shyti +Link: https://patchwork.freedesktop.org/patch/msgid/20240423165505.465734-2-janusz.krzysztofik@linux.intel.com +(cherry picked from commit fbad43eccae5cb14594195c20113369aabaa22b5) +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 15 +++++++-------- + 1 file changed, 7 insertions(+), 8 deletions(-) + +--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c ++++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c +@@ -258,8 +258,13 @@ static void signal_irq_work(struct irq_w + i915_request_put(rq); + } + ++ /* Lazy irq enabling after HW submission */ + if (!READ_ONCE(b->irq_armed) && !list_empty(&b->signalers)) + intel_breadcrumbs_arm_irq(b); ++ ++ /* And confirm that we still want irqs enabled before we yield */ ++ if (READ_ONCE(b->irq_armed) && !atomic_read(&b->active)) ++ intel_breadcrumbs_disarm_irq(b); + } + + struct intel_breadcrumbs * +@@ -310,13 +315,7 @@ void __intel_breadcrumbs_park(struct int + return; + + /* Kick the work once more to drain the signalers, and disarm the irq */ +- irq_work_sync(&b->irq_work); +- while (READ_ONCE(b->irq_armed) && !atomic_read(&b->active)) { +- local_irq_disable(); +- signal_irq_work(&b->irq_work); +- local_irq_enable(); +- cond_resched(); +- } ++ irq_work_queue(&b->irq_work); + } + + void intel_breadcrumbs_free(struct kref *kref) +@@ -399,7 +398,7 @@ static void insert_breadcrumb(struct i91 + * the request as it may have completed and raised the interrupt as + * we were attaching it into the lists. + */ +- if (!b->irq_armed || __i915_request_is_complete(rq)) ++ if (!READ_ONCE(b->irq_armed) || __i915_request_is_complete(rq)) + irq_work_queue(&b->irq_work); + } + diff --git a/queue-6.1/intel_th-pci-add-granite-rapids-soc-support.patch b/queue-6.1/intel_th-pci-add-granite-rapids-soc-support.patch new file mode 100644 index 00000000000..12a95d97fa0 --- /dev/null +++ b/queue-6.1/intel_th-pci-add-granite-rapids-soc-support.patch @@ -0,0 +1,34 @@ +From 854afe461b009801a171b3a49c5f75ea43e4c04c Mon Sep 17 00:00:00 2001 +From: Alexander Shishkin +Date: Mon, 29 Apr 2024 16:01:15 +0300 +Subject: intel_th: pci: Add Granite Rapids SOC support + +From: Alexander Shishkin + +commit 854afe461b009801a171b3a49c5f75ea43e4c04c upstream. + +Add support for the Trace Hub in Granite Rapids SOC. + +Signed-off-by: Alexander Shishkin +Reviewed-by: Andy Shevchenko +Cc: stable@kernel.org +Link: https://lore.kernel.org/r/20240429130119.1518073-12-alexander.shishkin@linux.intel.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/hwtracing/intel_th/pci.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/hwtracing/intel_th/pci.c ++++ b/drivers/hwtracing/intel_th/pci.c +@@ -310,6 +310,11 @@ static const struct pci_device_id intel_ + .driver_data = (kernel_ulong_t)&intel_th_2x, + }, + { ++ /* Granite Rapids SOC */ ++ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3256), ++ .driver_data = (kernel_ulong_t)&intel_th_2x, ++ }, ++ { + /* Alder Lake CPU */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x466f), + .driver_data = (kernel_ulong_t)&intel_th_2x, diff --git a/queue-6.1/intel_th-pci-add-granite-rapids-support.patch b/queue-6.1/intel_th-pci-add-granite-rapids-support.patch new file mode 100644 index 00000000000..ffca019cf44 --- /dev/null +++ b/queue-6.1/intel_th-pci-add-granite-rapids-support.patch @@ -0,0 +1,34 @@ +From e44937889bdf4ecd1f0c25762b7226406b9b7a69 Mon Sep 17 00:00:00 2001 +From: Alexander Shishkin +Date: Mon, 29 Apr 2024 16:01:14 +0300 +Subject: intel_th: pci: Add Granite Rapids support + +From: Alexander Shishkin + +commit e44937889bdf4ecd1f0c25762b7226406b9b7a69 upstream. + +Add support for the Trace Hub in Granite Rapids. + +Signed-off-by: Alexander Shishkin +Reviewed-by: Andy Shevchenko +Cc: stable@kernel.org +Link: https://lore.kernel.org/r/20240429130119.1518073-11-alexander.shishkin@linux.intel.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/hwtracing/intel_th/pci.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/hwtracing/intel_th/pci.c ++++ b/drivers/hwtracing/intel_th/pci.c +@@ -305,6 +305,11 @@ static const struct pci_device_id intel_ + .driver_data = (kernel_ulong_t)&intel_th_2x, + }, + { ++ /* Granite Rapids */ ++ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0963), ++ .driver_data = (kernel_ulong_t)&intel_th_2x, ++ }, ++ { + /* Alder Lake CPU */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x466f), + .driver_data = (kernel_ulong_t)&intel_th_2x, diff --git a/queue-6.1/intel_th-pci-add-lunar-lake-support.patch b/queue-6.1/intel_th-pci-add-lunar-lake-support.patch new file mode 100644 index 00000000000..637925372d6 --- /dev/null +++ b/queue-6.1/intel_th-pci-add-lunar-lake-support.patch @@ -0,0 +1,34 @@ +From f866b65322bfbc8fcca13c25f49e1a5c5a93ae4d Mon Sep 17 00:00:00 2001 +From: Alexander Shishkin +Date: Mon, 29 Apr 2024 16:01:19 +0300 +Subject: intel_th: pci: Add Lunar Lake support + +From: Alexander Shishkin + +commit f866b65322bfbc8fcca13c25f49e1a5c5a93ae4d upstream. + +Add support for the Trace Hub in Lunar Lake. + +Signed-off-by: Alexander Shishkin +Reviewed-by: Andy Shevchenko +Cc: stable@kernel.org +Link: https://lore.kernel.org/r/20240429130119.1518073-16-alexander.shishkin@linux.intel.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/hwtracing/intel_th/pci.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/hwtracing/intel_th/pci.c ++++ b/drivers/hwtracing/intel_th/pci.c +@@ -325,6 +325,11 @@ static const struct pci_device_id intel_ + .driver_data = (kernel_ulong_t)&intel_th_2x, + }, + { ++ /* Lunar Lake */ ++ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa824), ++ .driver_data = (kernel_ulong_t)&intel_th_2x, ++ }, ++ { + /* Alder Lake CPU */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x466f), + .driver_data = (kernel_ulong_t)&intel_th_2x, diff --git a/queue-6.1/intel_th-pci-add-meteor-lake-s-support.patch b/queue-6.1/intel_th-pci-add-meteor-lake-s-support.patch new file mode 100644 index 00000000000..45d823a23a6 --- /dev/null +++ b/queue-6.1/intel_th-pci-add-meteor-lake-s-support.patch @@ -0,0 +1,34 @@ +From c4a30def564d75e84718b059d1a62cc79b137cf9 Mon Sep 17 00:00:00 2001 +From: Alexander Shishkin +Date: Mon, 29 Apr 2024 16:01:17 +0300 +Subject: intel_th: pci: Add Meteor Lake-S support + +From: Alexander Shishkin + +commit c4a30def564d75e84718b059d1a62cc79b137cf9 upstream. + +Add support for the Trace Hub in Meteor Lake-S. + +Signed-off-by: Alexander Shishkin +Reviewed-by: Andy Shevchenko +Cc: stable@kernel.org +Link: https://lore.kernel.org/r/20240429130119.1518073-14-alexander.shishkin@linux.intel.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/hwtracing/intel_th/pci.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/hwtracing/intel_th/pci.c ++++ b/drivers/hwtracing/intel_th/pci.c +@@ -295,6 +295,11 @@ static const struct pci_device_id intel_ + .driver_data = (kernel_ulong_t)&intel_th_2x, + }, + { ++ /* Meteor Lake-S */ ++ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7f26), ++ .driver_data = (kernel_ulong_t)&intel_th_2x, ++ }, ++ { + /* Raptor Lake-S */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7a26), + .driver_data = (kernel_ulong_t)&intel_th_2x, diff --git a/queue-6.1/intel_th-pci-add-sapphire-rapids-soc-support.patch b/queue-6.1/intel_th-pci-add-sapphire-rapids-soc-support.patch new file mode 100644 index 00000000000..19659d7e5f7 --- /dev/null +++ b/queue-6.1/intel_th-pci-add-sapphire-rapids-soc-support.patch @@ -0,0 +1,34 @@ +From 2e1da7efabe05cb0cf0b358883b2bc89080ed0eb Mon Sep 17 00:00:00 2001 +From: Alexander Shishkin +Date: Mon, 29 Apr 2024 16:01:16 +0300 +Subject: intel_th: pci: Add Sapphire Rapids SOC support + +From: Alexander Shishkin + +commit 2e1da7efabe05cb0cf0b358883b2bc89080ed0eb upstream. + +Add support for the Trace Hub in Sapphire Rapids SOC. + +Signed-off-by: Alexander Shishkin +Reviewed-by: Andy Shevchenko +Cc: stable@kernel.org +Link: https://lore.kernel.org/r/20240429130119.1518073-13-alexander.shishkin@linux.intel.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/hwtracing/intel_th/pci.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/hwtracing/intel_th/pci.c ++++ b/drivers/hwtracing/intel_th/pci.c +@@ -315,6 +315,11 @@ static const struct pci_device_id intel_ + .driver_data = (kernel_ulong_t)&intel_th_2x, + }, + { ++ /* Sapphire Rapids SOC */ ++ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3456), ++ .driver_data = (kernel_ulong_t)&intel_th_2x, ++ }, ++ { + /* Alder Lake CPU */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x466f), + .driver_data = (kernel_ulong_t)&intel_th_2x, diff --git a/queue-6.1/riscv-rewrite-__kernel_map_pages-to-fix-sleeping-in-invalid-context.patch b/queue-6.1/riscv-rewrite-__kernel_map_pages-to-fix-sleeping-in-invalid-context.patch new file mode 100644 index 00000000000..5f18e00e3e0 --- /dev/null +++ b/queue-6.1/riscv-rewrite-__kernel_map_pages-to-fix-sleeping-in-invalid-context.patch @@ -0,0 +1,99 @@ +From fb1cf0878328fe75d47f0aed0a65b30126fcefc4 Mon Sep 17 00:00:00 2001 +From: Nam Cao +Date: Wed, 15 May 2024 07:50:40 +0200 +Subject: riscv: rewrite __kernel_map_pages() to fix sleeping in invalid context + +From: Nam Cao + +commit fb1cf0878328fe75d47f0aed0a65b30126fcefc4 upstream. + +__kernel_map_pages() is a debug function which clears the valid bit in page +table entry for deallocated pages to detect illegal memory accesses to +freed pages. + +This function set/clear the valid bit using __set_memory(). __set_memory() +acquires init_mm's semaphore, and this operation may sleep. This is +problematic, because __kernel_map_pages() can be called in atomic context, +and thus is illegal to sleep. An example warning that this causes: + +BUG: sleeping function called from invalid context at kernel/locking/rwsem.c:1578 +in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 2, name: kthreadd +preempt_count: 2, expected: 0 +CPU: 0 PID: 2 Comm: kthreadd Not tainted 6.9.0-g1d4c6d784ef6 #37 +Hardware name: riscv-virtio,qemu (DT) +Call Trace: +[] dump_backtrace+0x1c/0x24 +[] show_stack+0x2c/0x38 +[] dump_stack_lvl+0x5a/0x72 +[] dump_stack+0x14/0x1c +[] __might_resched+0x104/0x10e +[] __might_sleep+0x3e/0x62 +[] down_write+0x20/0x72 +[] __set_memory+0x82/0x2fa +[] __kernel_map_pages+0x5a/0xd4 +[] __alloc_pages_bulk+0x3b2/0x43a +[] __vmalloc_node_range+0x196/0x6ba +[] copy_process+0x72c/0x17ec +[] kernel_clone+0x60/0x2fe +[] kernel_thread+0x82/0xa0 +[] kthreadd+0x14a/0x1be +[] ret_from_fork+0xe/0x1c + +Rewrite this function with apply_to_existing_page_range(). It is fine to +not have any locking, because __kernel_map_pages() works with pages being +allocated/deallocated and those pages are not changed by anyone else in the +meantime. + +Fixes: 5fde3db5eb02 ("riscv: add ARCH_SUPPORTS_DEBUG_PAGEALLOC support") +Signed-off-by: Nam Cao +Cc: stable@vger.kernel.org +Reviewed-by: Alexandre Ghiti +Link: https://lore.kernel.org/r/1289ecba9606a19917bc12b6c27da8aa23e1e5ae.1715750938.git.namcao@linutronix.de +Signed-off-by: Palmer Dabbelt +Signed-off-by: Greg Kroah-Hartman +--- + arch/riscv/mm/pageattr.c | 28 ++++++++++++++++++++++------ + 1 file changed, 22 insertions(+), 6 deletions(-) + +--- a/arch/riscv/mm/pageattr.c ++++ b/arch/riscv/mm/pageattr.c +@@ -386,17 +386,33 @@ int set_direct_map_default_noflush(struc + } + + #ifdef CONFIG_DEBUG_PAGEALLOC ++static int debug_pagealloc_set_page(pte_t *pte, unsigned long addr, void *data) ++{ ++ int enable = *(int *)data; ++ ++ unsigned long val = pte_val(ptep_get(pte)); ++ ++ if (enable) ++ val |= _PAGE_PRESENT; ++ else ++ val &= ~_PAGE_PRESENT; ++ ++ set_pte(pte, __pte(val)); ++ ++ return 0; ++} ++ + void __kernel_map_pages(struct page *page, int numpages, int enable) + { + if (!debug_pagealloc_enabled()) + return; + +- if (enable) +- __set_memory((unsigned long)page_address(page), numpages, +- __pgprot(_PAGE_PRESENT), __pgprot(0)); +- else +- __set_memory((unsigned long)page_address(page), numpages, +- __pgprot(0), __pgprot(_PAGE_PRESENT)); ++ unsigned long start = (unsigned long)page_address(page); ++ unsigned long size = PAGE_SIZE * numpages; ++ ++ apply_to_existing_page_range(&init_mm, start, size, debug_pagealloc_set_page, &enable); ++ ++ flush_tlb_kernel_range(start, start + size); + } + #endif + diff --git a/queue-6.1/series b/queue-6.1/series index a2b3755bc27..c4021694669 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -188,3 +188,11 @@ pci-rockchip-ep-remove-wrong-mask-on-subsys_vendor_id.patch dmaengine-axi-dmac-fix-possible-race-in-remove.patch remoteproc-k3-r5-wait-for-core0-power-up-before-powering-up-core1.patch remoteproc-k3-r5-do-not-allow-core1-to-power-up-before-core0-via-sysfs.patch +riscv-rewrite-__kernel_map_pages-to-fix-sleeping-in-invalid-context.patch +drm-i915-gt-disarm-breadcrumbs-if-engines-are-already-idle.patch +drm-i915-dpt-make-dpt-object-unshrinkable.patch +intel_th-pci-add-granite-rapids-support.patch +intel_th-pci-add-granite-rapids-soc-support.patch +intel_th-pci-add-sapphire-rapids-soc-support.patch +intel_th-pci-add-meteor-lake-s-support.patch +intel_th-pci-add-lunar-lake-support.patch